Lines Matching +full:watchdog +full:- +full:timers

23 /* Each Timer Module (TIM) instance holds five 25 MHz timers. */
32 /* The basic watchdog timer period is 2^14 clock cycles. */
35 #define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"
40  * struct NPCM7xxBaseTimer - Basic functionality that both regular timer and
41  * watchdog timer use.
53  * struct NPCM7xxTimer - Individual timer state.
71  * struct NPCM7xxWatchdogTimer - The watchdog timer state.
76  * @wtcr: The Watchdog Timer Control Register.
89  * struct NPCM7xxTimerCtrlState - Timer Module device state.
94  * @timer: The five individual timers managed by this module.
95  * @watchdog_timer: The watchdog timer managed by this module.
109 #define TYPE_NPCM7XX_TIMER "npcm7xx-timer"