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/openbmc/u-boot/doc/device-tree-bindings/rtc/
H A Dbrcm,brcmstb-waketimer.txt1 Broadcom STB wake-up Timer
3 The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
4 ability to wake up the system from low-power suspend/standby modes.
7 - compatible : should contain "brcm,brcmstb-waketimer"
8 - reg : the register start and length for the WKTMR block
9 - interrupts : The TIMER interrupt
10 - interrupt-parent: The phandle to the Always-On (AON) Power Management (PM) L2
12 - clocks : The phandle to the UPG fixed clock (27Mhz domain)
17 compatible = "brcm,brcmstb-waketimer";
20 interrupt-parent = <&aon_pm_l2_intc>;
/openbmc/u-boot/arch/x86/include/asm/
H A Dacpi.h1 /* SPDX-License-Identifier: GPL-2.0+ */
12 * acpi_find_fadt() - find ACPI FADT table in the system memory
21 * acpi_find_wakeup_vector() - find OS installed wake up vector address
23 * This routine parses the ACPI table to locate the wake up vector installed
27 * @return: wake up vector address installed by the OS
32 * enter_acpi_mode() - enter into ACPI mode
34 * This programs the ACPI-defined PM1_CNT register to enable SCI interrupt
H A Dacpi_s3.h1 /* SPDX-License-Identifier: GPL-2.0+ */
49 * acpi_ss_string() - get ACPI-defined sleep state string
51 * @pm1_cnt: ACPI-defined sleep state
62 * acpi_sleep_from_pm1() - get ACPI-defined sleep state from PM1_CNT register
65 * @return: ACPI-defined sleep state if given valid PM1_CNT register value,
66 * -EINVAL otherwise.
83 return -EINVAL; in acpi_sleep_from_pm1()
87 * chipset_prev_sleep_state() - Get chipset previous sleep state
97 * chipset_clear_sleep_state() - Clear chipset sleep state
106 * acpi_resume() - Do ACPI S3 resume
[all …]
/openbmc/u-boot/arch/x86/lib/
H A Dacpi_s3.c1 // SPDX-License-Identifier: GPL-2.0+
31 enter_acpi_mode(fadt->pm1a_cnt_blk); in acpi_resume()
39 memcpy((void *)0x1000, (const void *)gd->arch.backup_mem, in acpi_resume()
49 gd->start_addr_sp -= S3_RESERVE_SIZE; in acpi_s3_reserve()
50 gd->arch.backup_mem = gd->start_addr_sp; in acpi_s3_reserve()
52 gd->start_addr_sp &= ~0xf; in acpi_s3_reserve()
55 * U-Boot sets up the real mode interrupt handler stubs starting from in acpi_s3_reserve()
56 * address 0x1000. In most cases, the first 640K (0x00000 - 0x9ffff) in acpi_s3_reserve()
61 * If U-Boot is in an S3 resume path, care must be taken not to corrupt in acpi_s3_reserve()
63 * Microsoft Windows 10 on Intel Baytrail its wake up vector happens to in acpi_s3_reserve()
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/openbmc/qemu/include/qemu/
H A Dfutex.h10 * See the COPYING file in the top-level directory.
15 * Note that a wake-up can also be caused by common futex usage patterns in
17 * memory location (e.g., typical futex-based implementations of Pthreads
19 * callers should always conservatively assume that it is a spurious wake-up,
20 * and use the futex word's value (i.e., the user-space synchronization scheme)
/openbmc/openbmc/poky/meta-yocto-bsp/recipes-kernel/linux/files/
H A D0001-Revert-serial-8250_omap-Drop-pm_runtime_irq_safe.patch8 Upstream-Status: Inappropriate
9 Signed-off-by: Ross Burton <ross.burton@arm.com>
10 ---
11 drivers/tty/serial/8250/8250_omap.c | 29 ++++++++---------------------
12 1 file changed, 8 insertions(+), 21 deletions(-)
14 diff --git a/drivers/tty/serial/8250/8250_omap.c b/drivers/tty/serial/8250/8250_omap.c
16 --- a/drivers/tty/serial/8250/8250_omap.c
18 @@ -8,7 +8,6 @@
22 -#include <linux/atomic.h>
26 @@ -134,7 +133,6 @@ struct omap8250_priv {
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pxaregs/pxaregs-1.14/
H A Dpxaregs.c2 * pxaregs - tool to display and modify PXA250's registers at runtime
4 * (c) Copyright 2002 by M&N Logistik-Lösungen Online GmbH
9 * Please send patches to h.schurig, working at mn-logistik.de
10 * - added fix from Bernhard Nemec
11 * - i2c registers from Stefan Eletzhofer
25 #include <linux/i2c-dev.h>
29 static int fd = -1;
85 { "PMCR", 0x40F00000, 0, 0xffffffff, 'x', "Power Manager Control Register (3-23)" },
88 { "PSSR", 0x40F00004, 0, 0xffffffff, 'x', "Power Manager Sleep Status Register (3-29)" },
95 { "PSPR", 0x40F00008, 0, 0xffffffff, 'x', "Power Manager Scratch Pad Register (3-30)" },
[all …]
/openbmc/qemu/docs/devel/
H A Dreset.rst18 ----------------
43 have some non-deterministic state they want to reinitialize to a different
45 must not reinitialize on a snapshot-load reset.
48 If the machine supports waking up from a suspended state and needs to reset
49 its devices during wake-up (from the ``MachineClass::wakeup()`` method), this
51 type to differentiate the reset requested during machine wake-up from other
52 reset requests. For example, RAM content must not be lost during wake-up, and
53 memory devices like virtio-mem that provide additional RAM must not reset
54 such state during wake-ups, but might do so during cold resets. However, this
55 reset type should not be used for wake-up detection, as not every machine
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/openbmc/qemu/accel/
H A Daccel-blocker.c30 #include "qemu/main-loop.h"
32 #include "system/accel-blocker.h"
60 /* change event to SET. If event was BUSY, wake up all waiters */ in accel_ioctl_end()
71 qemu_lockcnt_inc(&cpu->in_ioctl_lock); in accel_cpu_ioctl_begin()
80 qemu_lockcnt_dec(&cpu->in_ioctl_lock); in accel_cpu_ioctl_end()
81 /* change event to SET. If event was BUSY, wake up all waiters */ in accel_cpu_ioctl_end()
91 if (qemu_lockcnt_count(&cpu->in_ioctl_lock)) { in accel_has_to_wait()
113 qemu_lockcnt_lock(&cpu->in_ioctl_lock); in accel_ioctl_inhibit_begin()
135 * it will be waken up, but also here the while loop makes sure in accel_ioctl_inhibit_begin()
136 * to re-enter the wait if there are other running ioctls. in accel_ioctl_inhibit_begin()
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/openbmc/slpd-lite/
H A Dsock_channel.cpp32 rc = -errno; in read()
54 rc = -1; in read()
58 rc = -errno; in read()
63 } while ((readDataLen < 0) && (-(rc) == EINTR)); in read()
107 rc = -errno; in write()
114 rc = -1; in write()
118 } while ((writeDataLen < 0) && (-(rc) == EINTR)); in write()
122 // Spurious wake up in write()
123 std::cerr << "Spurious wake up on select (writeset)\n"; in write()
132 rc = -1; in write()
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/openbmc/qemu/util/
H A Duserfaultfd.c2 * Linux UFFD-WP support
10 * later. See the COPYING file in the top-level directory.
15 #include "qemu/error-report.h"
58 return -EINVAL; in uffd_open()
73 int ret = -1; in uffd_query_features()
78 return -1; in uffd_query_features()
99 * Returns non-negative file descriptor or negative value in case of an error
102 * @non_blocking: create UFFD file descriptor for non-blocking operation
115 return -1; in uffd_create_fd()
133 return -1; in uffd_create_fd()
[all …]
H A Dqemu-coroutine-lock.c24 * The lock-free mutex implementation is based on OSv
38 QSIMPLEQ_INIT(&queue->entries); in qemu_co_queue_init()
46 QSIMPLEQ_INSERT_HEAD(&queue->entries, self, co_queue_next); in qemu_co_queue_wait_impl()
48 QSIMPLEQ_INSERT_TAIL(&queue->entries, self, co_queue_next); in qemu_co_queue_wait_impl()
78 next = QSIMPLEQ_FIRST(&queue->entries); in qemu_co_enter_next_impl()
83 QSIMPLEQ_REMOVE_HEAD(&queue->entries, co_queue_next); in qemu_co_enter_next_impl()
115 return QSIMPLEQ_FIRST(&queue->entries) == NULL; in qemu_co_queue_empty()
118 /* The wait records are handled with a multiple-producer, single-consumer
119 * lock-free queue. There cannot be two concurrent pop_waiter() calls
120 * because pop_waiter() can only be called while mutex->handoff is zero.
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun5i-a13-utoo-p66.dts4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "sun5i-a13.dtsi"
45 #include "sun5i-reference-design-tablet.dtsi"
46 #include <dt-bindings/interrupt-controller/irq.h>
50 compatible = "utoo,p66", "allwinner,sun5i-a13";
54 /delete-property/serial0;
58 /delete-property/stdout-path;
62 /* The lcd panel i2c interface is hooked up via gpios */
63 compatible = "i2c-gpio";
[all …]
/openbmc/qemu/include/block/
H A Daio-wait.h29 #include "qemu/main-loop.h"
82 /* Increment wait_->num_waiters before evaluating cond. */ \
83 qatomic_inc(&wait_->num_waiters); \
99 qatomic_dec(&wait_->num_waiters); \
111 * Wake up the main thread if it is waiting on AIO_WAIT_WHILE(). During
114 * aio_wait_kick() call will wake up the main thread.
H A Dblock_int-io.h27 #include "block/block_int-common.h"
29 #include "qemu/main-loop.h"
32 * I/O API functions. These functions are thread-safe.
34 * See include/block/block-io.h for more information about
91 * Wake up the main thread if it is waiting on BDRV_POLL_WHILE. During
94 * waiting for the I/O operation to complete. A bdrv_wakeup will wake
95 * up the main thread if necessary.
169 * Check whether the given offset is in the cached block-status data
173 * `bsc.data_end - offset`, i.e. how many bytes, starting from
181 * block-status region, invalidate the cache.
/openbmc/sdbusplus/src/async/
H A Dmutex.cpp27 // Wake up the next waiting task in unlock()
31 completion->complete(); in unlock()
/openbmc/qemu/block/
H A Dgraph-lock.c22 #include "qemu/main-loop.h"
23 #include "block/graph-lock.h"
37 * Many write-locked sections are also drained sections. There is a convenience
41 * because the aio_poll() call in bdrv_graph_wrlock() might re-enter
43 * bdrv_graph_wrunlock() might also re-enter a write-locked section.
66 * List of BdrvGraphRWlock kept in graph-lock.c
88 ctx->bdrv_graph = g_new0(BdrvGraphRWlock, 1); in register_aiocontext()
90 assert(ctx->bdrv_graph->reader_count == 0); in register_aiocontext()
91 QTAILQ_INSERT_TAIL(&aio_context_list, ctx->bdrv_graph, next_aio); in register_aiocontext()
97 orphaned_reader_count += ctx->bdrv_graph->reader_count; in unregister_aiocontext()
[all …]
/openbmc/u-boot/board/freescale/mpc8536ds/
H A Dddr.c1 // SPDX-License-Identifier: GPL-2.0
17 * - number of chips on bus in fsl_ddr_board_options()
18 * - position of slot in fsl_ddr_board_options()
19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
20 * - ??? in fsl_ddr_board_options()
22 * This needs to be determined on a board-by-board basis. in fsl_ddr_board_options()
26 popts->clk_adjust = 7; in fsl_ddr_board_options()
30 * - frequency in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
33 popts->cpo_override = 10; in fsl_ddr_board_options()
[all …]
/openbmc/qemu/hw/misc/macio/
H A Dmac_dbdma.c2 * PowerMac descriptor-based DMA emulation
4 * Copyright (c) 2005-2007 Fabrice Bellard
8 * some parts from linux-2.6.28, arch/powerpc/include/asm/dbdma.h
10 * Definitions for using the Apple Descriptor-Based DMA controller
19 * Copyright (C) 1998-2004 Samuel Rydh (samuel@ibrium.se)
44 #include "qemu/main-loop.h"
51 #define DEBUG_DBDMA_CHANMASK ((1ull << DBDMA_CHANNELS) - 1)
61 if ((1ul << (ch)->channel) & DEBUG_DBDMA_CHANMASK) { \
62 printf("DBDMA[%02x]: " fmt , (ch)->channel, ## __VA_ARGS__); \
72 return container_of(ch, DBDMAState, channels[ch->channel]); in dbdma_from_ch()
[all …]
/openbmc/u-boot/arch/x86/cpu/intel_common/
H A Dme_status.c1 // SPDX-License-Identifier: GPL-2.0
28 [ME_HFS_STATE_BRINGUP] = "Bring up",
62 [0x00] = "Clean Moff->Mx wake",
63 [0x01] = "Moff->Mx wake after an error",
68 [0x06] = "Pseudo-global reset",
69 [0x07] = "S0/M0->Sx/M3",
70 [0x08] = "Sx/M3->S0/M0",
71 [0x09] = "Non-power cycle reset",
74 [0x0c] = "Sx/Mx->Sx/Moff"
86 [0x01] = "Disable the host wake event",
[all …]
/openbmc/u-boot/board/egnite/ethernut5/
H A Dethernut5_pwrman.h1 /* SPDX-License-Identifier: GPL-2.0+ */
31 #define PWRMAN_RS232 0x10 /* RS-232 driver shutdown */
34 #define PWRMAN_WAKEUP 0x80 /* RTC wake-up */
36 /* Features, which are not essential to keep u-boot alive */
/openbmc/qemu/target/arm/
H A Darm-powerctl.h2 * QEMU support -- ARM Power Control specific functions.
4 * Copyright (c) 2016 Jean-Christophe Dubois
7 * See the COPYING file in the top-level directory.
14 #include "kvm-consts.h"
34 * @cpuid: the id of the CPU we want to start/wake up.
47 * QEMU_ARM_POWERCTL_ON_PENDING if the CPU is still powering up
83 * to start after a power-on reset.
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dsec_entry_cpu1.S1 /* SPDX-License-Identifier: GPL-2.0+ */
34 /* Assembly core where CPU1 is woken up into
35 * No need to save-restore registers, does not use stack.
75 * Assumes that CPU #1 is waiting in ROM code and not yet woken up or used by
76 * u-boot.
94 sev @ Wake up CPU1
/openbmc/u-boot/include/
H A DSA-1100.h2 * FILE SA-1100.h
8 * System StrongARM SA-1100
11 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
13 * StrongARM SA-1100 data sheet version 2.2.
15 * Language-specific definitions are selected by the
33 #include <asm/arch-sa1100/bitfield.h>
195 * Controller (UDC) Control/Status register end-point 0
198 * Controller (UDC) Control/Status register end-point 1
201 * Controller (UDC) Control/Status register end-point 2
204 * Controller (UDC) Data register end-point 0
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/openbmc/smbios-mdr/include/
H A Dspeed_select.hpp7 // http://www.apache.org/licenses/LICENSE-2.0
34 * the info on new D-Bus objects on the given bus connection.
52 * E.g. fn(0x7A) -> {1,3,4,5,6}
81 /** Whether SST-PP is enabled on the processor. */
83 /** Return the current SST-PP configuration level */
85 /** Return the maximum valid SST-PP configuration level */
94 /** Whether SST-BF is supported in a given level. */
96 /** Whether SST-TF is supported in a given level. */
98 /** Whether SST-BF is enabled in a given level. */
100 /** Whether SST-TF is enabled in a given level. */
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