sst: Don't always wake idle CPU

Some parts of SST are important (initial discovery, appliedConfig
change) and should use wake-on-PECI to ensure success even if the CPU is
in an idle PkgC state. Othe

sst: Don't always wake idle CPU

Some parts of SST are important (initial discovery, appliedConfig
change) and should use wake-on-PECI to ensure success even if the CPU is
in an idle PkgC state. Other parts are not important enough to justify
increasing the CPU power draw. Add a WakePolicy parameter to the
SSTInterface infrastructure to use a different policy in different
contexts.

Change-Id: I91435cc0357ab60ca4656e1bc51286e046ae3809
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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clang-format: copy latest and re-format

clang-format-16 has some backwards incompatible changes that require
additional settings for best compatibility and re-running the formatter.
Copy the latest

clang-format: copy latest and re-format

clang-format-16 has some backwards incompatible changes that require
additional settings for best compatibility and re-running the formatter.
Copy the latest .clang-format from the docs repository and reformat the
repository.

Change-Id: I172b14c1a881c734851b7dc6e0e90ee2e11cce03
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>

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sst: Prefer cached values over default values

In anticipation of support for future CPUs, change some assumptions:
* When host is off, return cached property values instead of "default"
values. CP

sst: Prefer cached values over default values

In anticipation of support for future CPUs, change some assumptions:
* When host is off, return cached property values instead of "default"
values. CPUs may not guarantee support for level 0, so there is no
universal default.
* Must always check the backend interface is ready before using it.
* Rename numLevels() to maxLevel() since there may be discontinuities in
the supported levels.
* Also add some more debug prints.

Tested:
* On CPU that supports level 0 - verified that output of sst-info.sh
script was the same before and after these changes.
* On a CPU that only supports level 4 - verified that when host was
powered off, the AppliedConfig showed config4 (valid) instead of
config0 (invalid).

Change-Id: Idffcb9a6534ba32760f6d6b2ac244f47427995ea
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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sst: Rediscover profiles after host reboot

In some cases, host processor reboot may change the static SST-PP
profile information. This commit adds ability to register callbacks to
run upon hostState

sst: Rediscover profiles after host reboot

In some cases, host processor reboot may change the static SST-PP
profile information. This commit adds ability to register callbacks to
run upon hostState changes, and reruns SST discovery whenever the host
exits the power-off state.

Tested:
- Ran tools/sst-compare-redfish-os.py tool on platform with SPR host
CPU, and observed no mismatches before and after a host reboot.
- Confirmed Redfish OperatingConfig properties still populated when host
is off.

Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
Change-Id: I9e7b0ebb8c5ec7a8464346f3476490b765579428

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Refactor SST host processor interface

In order to support future host processors that use a different
interface to SST, separate the SST logic into 1) high-level discovery
logic + D-Bus interfaces,

Refactor SST host processor interface

In order to support future host processors that use a different
interface to SST, separate the SST logic into 1) high-level discovery
logic + D-Bus interfaces, and 2) low-level backend processor interface.

This is a pure refactor with no functional change.

Tested:
Ran sst-compare-redfish-os.py tool on platform with SPR host CPU, and
verified no mismatches reported.
Used sst-info.sh to change configs and verify new config was reflected
in Redfish.

Change-Id: I6825eb7541cbe2214844e7b64d462f2688dedcec
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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cpuinfoapp: Add SST discovery feature

Retrieve Intel Speed Select Technology (SST) configuration values for
all CPUs via PECI (OS-PCode mailbox). Each CPU may have up to three
Performance Profiles (

cpuinfoapp: Add SST discovery feature

Retrieve Intel Speed Select Technology (SST) configuration values for
all CPUs via PECI (OS-PCode mailbox). Each CPU may have up to three
Performance Profiles (PP), each with accompanying Base Frequency (BF)
information.

Discovery is started immediately, but if no CPUs are found or any
unexpected PECI error is encountered, discovery is aborted and scheduled
for periodic retries until complete.

The profile data is published on D-Bus using two predefined interfaces:
- xyz.openbmc_project.Control.Processor.CurrentOperationConfig, which
is implemented on each "cpu" object in the inventory, and contains
mutable properties for OOB configuration (modifiying properties not
supported yet).
- xyz.openbmc_project.Inventory.Item.Cpu.OperationConfig, which is
implemented on separate "config" objects and contains the readonly
properties for each performance profile.

Tested:
- Profiled performance of PECI operations via code instrumentation
(takes ~2 min per CPU on ast2500 during BMC boot, ~2 sec during BMC idle).
- Validated Redfish output against Linux driver using included python
tool.
- Injected PECI failures in code to test error handling, and tested
with Linux OS idling on host to make sure WOP is working.

Change-Id: I0d8ae79655dfd2880cf3bae6abe600597740df7c
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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