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/openbmc/linux/arch/arm/mm/
H A Dcache-tauros2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
8 * - PJ1 CPU Core Datasheet,
9 * Document ID MV-S104837-01, Rev 0.7, January 24 2008.
10 * - PJ4 CPU Core Datasheet,
11 * Document ID MV-S105190-00, Rev 0.7, March 14 2008.
20 #include <asm/hardware/cache-tauros2.h>
29 * When Tauros2 is used on a CPU that supports the v7 hierarchical
30 * cache operations, the cache handling code in proc-v7.S takes care
34 * being used on a pre-v7 CPU, and we only need to build support for
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H A Dproc-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7.S
9 #include <linux/arm-smccc.h>
14 #include <asm/asm-offsets.h>
16 #include <asm/pgtable-hwdef.h>
19 #include "proc-macros.S"
22 #include "proc-v7-3level.S"
24 #include "proc-v7-2level.S"
27 .arch armv7-a
48 * - loc - location to jump to for soft reset
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H A Dnommu.c1 // SPDX-License-Identifier: GPL-2.0-only
32 * zero-initialized data and COW.
54 asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc"); in set_vbar()
59 * 0b0000 - not implemented, 0b0001/0b0010 - implemented
101 * There is no dedicated vector page on V7-M. So nothing needs to be in arm_mm_memblock_reserve()
149 high_memory = __va(end - 1) + 1; in adjust_lowmem_bounds()
200 if (vma->vm_flags & VM_EXEC) in copy_to_user_page()
/openbmc/linux/arch/s390/crypto/
H A Dcrc32le-vx.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of bitreflected CRC-32 checksums for IEEE 802.3 Ethernet
9 * This CRC-32 implementation algorithm is bitreflected and processes
10 * the least-significant bit first (Little-Endian).
17 #include <asm/nospec-insn.h>
18 #include <asm/vx-insn.h>
20 /* Vector register range containing CRC-32 constants */
32 * The CRC-32 constant block contains reduction constants to fold and
35 * For the CRC-32 variants, the constants are precomputed according to
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H A Dcrc32be-vx.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of CRC-32 checksums.
8 * This CRC-32 implementation algorithm processes the most-significant
16 #include <asm/nospec-insn.h>
17 #include <asm/vx-insn.h>
19 /* Vector register range containing CRC-32 constants */
31 * The CRC-32 constant block contains reduction constants to fold and
34 * For the CRC-32 variants, the constants are precomputed according to
55 * CRC-32 (IEEE 802.3 Ethernet, ...) polynomials:
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/openbmc/linux/Documentation/networking/device_drivers/ethernet/dlink/
H A Ddl2k.rst1 .. SPDX-License-Identifier: GPL-2.0
4 D-Link DL2000-based Gigabit Ethernet Adapter Installation
11 - Compatibility List
12 - Quick Install
13 - Compiling the Driver
14 - Installing the Driver
15 - Option parameter
16 - Configuration Script Sample
17 - Troubleshooting
25 - D-Link DGE-550T Gigabit Ethernet Adapter.
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/openbmc/phosphor-webui/app/assets/icons/
H A Dicon-warning.svg3 <path d="M10 1.4L.3 18.3h19.5L10 1.4zM10 4l7.5 13h-15L10 4z" fill="#ffb000"/>
4 <path d="M9.2 7.8v1.4l.4 3.5h.8l.4-3.5V7.8H9.2z"/>
5 <circle cx="10" cy="14.7" r=".8"/>
/openbmc/linux/Documentation/dev-tools/kunit/
H A Dkunit_suitememorydiagram.svg1 <?xml version="1.0" encoding="UTF-8"?>
3 <g transform="translate(-13.724 -17.943)">
4 <g fill="#dad4d4" fill-opacity=".91765" stroke="#1a1a1a">
12 …nt-family="sans-serif" font-size="16px" style="line-height:1.25" xml:space="preserve"><tspan x="32…
14 <g transform="translate(0 -258.6)">
16 …nt-family="sans-serif" font-size="16px" style="line-height:1.25" xml:space="preserve"><tspan x="32…
18 <g transform="translate(0 -217.27)">
20 …nt-family="sans-serif" font-size="16px" style="line-height:1.25" xml:space="preserve"><tspan x="32…
22 <g transform="translate(0 -175.94)">
24 …nt-family="sans-serif" font-size="16px" style="line-height:1.25" xml:space="preserve"><tspan x="32…
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/openbmc/linux/arch/arm/include/asm/
H A Dpercpu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 * Same as asm-generic/percpu.h, except that we store the per cpu offset
14 * in the TPIDRPRW. TPIDRPRW only exists on V6K and V7
25 asm volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (off) : "memory"); in set_my_cpu_offset()
53 " .long 0b - . \n\t" in __my_cpu_offset()
54 " b . + (2b - 0b) \n\t" in __my_cpu_offset()
57 : "=r" (off) in __my_cpu_offset()
68 #include <asm-generic/percpu.h>
H A Dcachetype.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * - v6+ is never VIVT
27 * - v7+ VIPT never aliases on D-side
74 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector)); in set_csselr()
81 asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); in read_ccsidr()
H A Dcacheflush.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1999-2002 Russell King
12 #include <asm/glue-cache.h>
17 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
29 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
35 * See Documentation/core-api/cachetlb.rst for more information.
37 * effects are cache-type (VIVT/VIPT/PIPT) specific.
42 * Currently only needed for cache-v6.S and cache-v7.S, see
52 * inner shareable and invalidate the I-cache.
53 * Only needed from v7 onwards, falls back to flush_cache_all()
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H A Dcputype.h1 /* SPDX-License-Identifier: GPL-2.0 */
59 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
125 : "=r" (__val) \
140 : "=r" (__val) \
265 /* StrongARM-11x0 CPUs */
312 * Marvell's PJ4 and PJ4B cores are based on V7 version,
338 feature -= 16; in cpuid_feature_extract_field()
/openbmc/qemu/tests/tcg/hexagon/
H A Dhvx_misc.c2 * Copyright(c) 2021-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
49 : : "r"(p0), "r"(p1), "r"(pout) in test_load_tmp()
81 : : "r"(pout0), "r"(pout1) in test_load_tmp2()
103 : : "r"(p0), "r"(pout) : "v2", "memory"); in test_load_cur()
125 : : "r"(p0), "r"(pout) : "v2", "memory"); in test_load_aligned()
141 : : "r"(p0), "r"(pout) : "v2", "memory"); in test_load_unaligned()
158 : : "r"(p0), "r"(pout) : "v2", "memory"); in test_store_aligned()
174 : : "r"(p0), "r"(pout) : "v2", "memory"); in test_store_unaligned()
199 : : "r"(pmask), "r"(p0), "r"(pout) in test_masked_store()
207 "if (q0) vmem(%2) = v5\n\t" /* Non-inverted test */ in test_masked_store()
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/openbmc/linux/arch/arm/mach-versatile/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
48 Include support for the ARM(R) Integrator/AP and
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
61 allows ARM(R) Ltd PrimeCells to be developed and evaluated.
62 The IM-PD1 can be found on the Integrator/PP2 platform.
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
107 bool "Integrator/CM1026EJ-S core module"
113 bool "Integrator/CM1136JF-S core module"
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/openbmc/linux/arch/powerpc/crypto/
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
15 # key = (r, s)
16 # clamp r &= 0x0FFFFFFC0FFFFFFC 0x0FFFFFFC0FFFFFFF
17 # p = 2^130 - 5
19 # a = (r + a) % p
23 # h4 = m1 * r⁴ + m2 * r³ + m3 * r² + m4 * r
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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/openbmc/linux/arch/arm/boot/dts/allwinner/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 dtb-$(CONFIG_MACH_SUN4I) += \
3 sun4i-a10-a1000.dtb \
4 sun4i-a10-ba10-tvbox.dtb \
5 sun4i-a10-chuwi-v7-cw0825.dtb \
6 sun4i-a10-cubieboard.dtb \
7 sun4i-a10-dserve-dsrv9703c.dtb \
8 sun4i-a10-gemei-g9.dtb \
9 sun4i-a10-hackberry.dtb \
10 sun4i-a10-hyundai-a7hd.dtb \
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/openbmc/qemu/target/arm/
H A Dcpu.h23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-defs.h"
29 #include "exec/page-protection.h"
30 #include "qapi/qapi-types-common.h"
79 /* ARM-specific interrupt pending bits. */
102 /* ARM-specific extra insn start words:
113 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
148 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
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/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-inventec-starscream.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include "aspeed-g6-pinctrl.dtsi"
8 #include <dt-bindings/i2c/i2c.h>
9 #include <dt-bindings/gpio/aspeed-gpio.h>
13 compatible = "inventec,starscream-bmc", "aspeed,ast2600";
20 stdout-path = &uart5;
28 reserved-memory {
29 #address-cells = <1>;
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H A Daspeed-bmc-opp-romulus.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
3 #include "aspeed-g5.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
8 compatible = "ibm,romulus-bmc", "aspeed,ast2500";
11 stdout-path = &uart5;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
25 no-map;
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/openbmc/linux/arch/sparc/math-emu/
H A Dmath_32.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sparc/math-emu/math.c
21 * of the three IEEE formats. FP_ADD_D(R,A,B) is for adding doubles,
23 * generic macros (in this case _FP_ADD(D,2,R,X,Y) where the number
27 * The generic macros are defined in op-common.h. This is where all
29 * word sizes macros in op-common.h use macros like _FP_FRAC_SLL_##wc()
31 * These are defined in the third layer of macros: op-1.h, op-2.h
32 * and op-4.h. These handle operations on floating point numbers composed
35 * constructs in op-1.h, but on sparc32 they use op-2.h definitions.]
36 * soft-fp.h is on the same level as op-common.h, and defines some
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/openbmc/linux/arch/arm/boot/compressed/
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2002 Russell King
12 #include "efi-header.S"
20 AR_CLASS( .arch armv7-a )
21 M_CLASS( .arch armv7-m )
101 kputc #'-'
105 kputc #'-'
110 kputc #'-'
146 ARM( .inst 0xf57ff06f @ v7+ isb )
154 * in little-endian form.
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/openbmc/u-boot/
H A D.travis.yml1 # SPDX-License-Identifier: GPL-2.0+
2 # Copyright Roger Meier <r.meier@siemens.com>
4 # build U-Boot on Travis CI - https://travis-ci.org/
14 - ubuntu-toolchain-r-test
15 - llvm-toolchain-trusty-7
17 - cppcheck
18 - sloccount
19 - sparse
20 - bc
21 - build-essential
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/openbmc/linux/drivers/gpu/drm/panel/
H A Dpanel-ilitek-ili9322.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * - 8-bit serial RGB interface
7 * - 24-bit parallel RGB interface
8 * - 8-bit ITU-R BT.601 interface
9 * - 8-bit ITU-R BT.656 interface
10 * - Up to 320RGBx240 dots resolution TFT LCD displays
11 * - Scaling, brightness and contrast
19 * Derived from drivers/drm/gpu/panel/panel-samsung-ld9040.c
64 /* 0 = right-to-left, 1 = left-to-right (default), horizontal flip */
66 /* 0 = down-to-up, 1 = up-to-down (default), vertical flip */
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/openbmc/qemu/disas/
H A Dsparc.c3 * include/opcode/sparc.h, opcodes/sparc-opc.c, opcodes/sparc-dis.c
30 #include "disas/dis-asm.h"
33 the opcodes library in sparc-opc.c. If you change anything here, make
36 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
43 returns non-zero.
44 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
45 Don't change this without updating sparc-opc.c. */
62 #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
68 /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
77 EG: For v7 this would be
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