Lines Matching +full:v7 +full:- +full:r
23 #include "kvm-consts.h"
24 #include "qemu/cpu-float.h"
26 #include "cpu-qom.h"
27 #include "exec/cpu-defs.h"
29 #include "exec/page-protection.h"
30 #include "qapi/qapi-types-common.h"
79 /* ARM-specific interrupt pending bits. */
102 /* ARM-specific extra insn start words:
113 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
148 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
149 * For 64-bit, this is a 2048-bit SVE register.
221 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
223 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
224 * DAIF (exception masks) are kept in env->daif
225 * BTYPE is kept in env->btype
226 * SM and ZA are kept in env->svcr
227 * all other bits are stored in their correct places in env->pstate
247 /* These hold r8-r12. */
292 uint32_t nsacr; /* Non-secure access control register. */
463 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
464 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
465 uint32_t c15_threadid; /* TI debugger thread-ID. */
483 * architecturally-correct value is being read/set.
510 * Fine-Grained Trap registers. We store these as arrays so the
531 * of the Secure and Non-Secure states. (If the CPU doesn't support
534 * and the non-active SP for the current security state in
558 uint32_t aircr; /* only holds r/w state if security extn implemented */
574 * code which raises an exception must set cs->exception_index and
576 * will then set the guest-visible registers as part of the exception
601 /* Thumb-2 EE state. */
637 * fp_status_fp16: used for half-precision calculations
639 * standard_fp_status_fp16 : used for half-precision
642 * Half-precision operations are governed by a separate
643 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
646 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
647 * round-to-nearest and is used by any operations (generally
666 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */
667 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */
673 * Contains the 'val' for the second 64-bit register of LDXP, which comes
674 * from the higher address, not the high part of a complete 128-bit value.
701 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order,
703 * array, where ZA[N] is in the least-significant bytes of env->zarray[N].
787 env->features |= 1ULL << feature; in set_feature()
792 env->features &= ~(1ULL << feature); in unset_feature()
819 * In map, each set bit is a supported vector length of (bit-number + 1) * 16
873 * pmu_op_finish() - it does not need other handling during migration
920 /* CPU has M-profile DSP extension */
935 * 0 - disabled, 1 - smc, 2 - hvc
941 /* For v8M, initial value of the Non-secure VTOR */
972 /* QOM property to indicate we should use the back-compat CNTFRQ default */
980 /* The instance init functions for implementation-specific subclasses
981 * set these fields to specify the implementation-dependent values of
982 * various constant registers and reset values of non-constant
987 * is used for reset values of non-constant registers; no reset_
993 * you need to also update the 32-bit and 64-bit versions of the
1081 * big-endian mode). This setting isn't used directly: instead it modifies
1092 /* Used to synchronize KVM and QEMU in-kernel device levels */
1193 * lower exception level. This function does that post-reset CPU setup,
1214 * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1215 * The byte at offset i from the start of the in-memory representation contains
1218 * matches QEMU's representation, which is to use an array of host-endian
1220 * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1258 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
1268 return env->aarch64; in is_a64()
1276 * they are enabled) and the guest-visible values. These two calls must
1311 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
1312 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1314 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
1315 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1318 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1319 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1321 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
1323 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
1325 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
1328 #define SCTLR_SW (1U << 10) /* v7 */
1329 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
1330 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */
1331 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
1335 #define SCTLR_RR (1U << 14) /* up to v7 */
1337 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
1339 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
1341 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */
1343 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
1347 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
1349 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
1350 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1351 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
1352 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */
1353 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
1354 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
1355 #define SCTLR_VE (1U << 24) /* up to v7 */
1358 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
1360 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1363 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1365 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1372 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1373 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1374 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1375 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
1376 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
1377 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1378 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
1445 * AArch32 mode SPSRs are basically CPSR-format.
1498 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1506 ZF = (env->ZF == 0); in pstate_read()
1507 return (env->NF & 0x80000000) | (ZF << 30) in pstate_read()
1508 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) in pstate_read()
1509 | env->pstate | env->daif | (env->btype << 10); in pstate_read()
1514 env->ZF = (~val) & PSTATE_Z; in pstate_write()
1515 env->NF = val; in pstate_write()
1516 env->CF = (val >> 29) & 1; in pstate_write()
1517 env->VF = (val << 3) & 0x80000000; in pstate_write()
1518 env->daif = val & PSTATE_DAIF; in pstate_write()
1519 env->btype = (val >> 10) & 3; in pstate_write()
1520 env->pstate = val & ~CACHED_PSTATE_BITS; in pstate_write()
1535 * Set the CPSR. Note that some bits of mask must be all-set or all-clear.
1547 ZF = (env->ZF == 0); in xpsr_read()
1548 return (env->NF & 0x80000000) | (ZF << 30) in xpsr_read()
1549 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) in xpsr_read()
1550 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) in xpsr_read()
1551 | ((env->condexec_bits & 0xfc) << 8) in xpsr_read()
1552 | (env->GE << 16) in xpsr_read()
1553 | env->v7m.exception; in xpsr_read()
1556 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
1560 env->ZF = (~val) & XPSR_Z; in xpsr_write()
1561 env->NF = val; in xpsr_write()
1562 env->CF = (val >> 29) & 1; in xpsr_write()
1563 env->VF = (val << 3) & 0x80000000; in xpsr_write()
1566 env->QF = ((val & XPSR_Q) != 0); in xpsr_write()
1569 env->GE = (val & XPSR_GE) >> 16; in xpsr_write()
1573 env->thumb = ((val & XPSR_T) != 0); in xpsr_write()
1576 env->condexec_bits &= ~3; in xpsr_write()
1577 env->condexec_bits |= (val >> 25) & 3; in xpsr_write()
1580 env->condexec_bits &= 3; in xpsr_write()
1581 env->condexec_bits |= (val >> 8) & 0xfc; in xpsr_write()
1715 #define FPCR_LEN_MASK (7 << 16) /* LEN, A-profile only */
1716 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1719 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1721 #define FPCR_AHP (1 << 26) /* Alternative half-precision */
1723 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
1809 /* These ones are M-profile only */
1816 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
1927 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1952 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
2364 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
2365 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
2366 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
2367 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
2368 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
2369 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
2389 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2392 * HWCAP bit, remember to update the feature-bit-to-hwcap
2393 * mapping in linux-user/elfload.c:get_elf_hwcap().
2408 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
2409 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
2417 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
2425 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
2446 return (env->features & (1ULL << feature)) != 0; in arm_feature()
2464 /* Return true if @space is secure, in the pre-v9 sense. */
2470 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */
2505 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { in arm_is_el3_or_mon()
2509 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { in arm_is_el3_or_mon()
2545 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); in arm_is_el2_enabled_secstate()
2614 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { in arm_el_is_aa64()
2615 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); in arm_el_is_aa64()
2623 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); in arm_el_is_aa64()
2630 * access the secure or non-secure bank of a cp register. When EL3 is
2631 * operating in AArch32 state, the NS-bit determines whether the secure
2634 * accesses are to the non-secure version.
2640 !(env->cp15.scr_el3 & SCR_NS)); in access_secure_reg()
2647 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2652 (_env)->cp15._regname##_s = (_val); \
2654 (_env)->cp15._regname##_ns = (_val); \
2690 return env->v7m.exception != 0; in arm_v7m_is_handler_mode()
2700 !(env->v7m.control[env->v7m.secure] & 1); in arm_current_el()
2704 return extract32(env->pstate, 2, 2); in arm_current_el()
2707 switch (env->uncached_cpsr & 0x1f) { in arm_current_el()
2716 /* If EL3 is 32-bit then all secure privileged modes run in in arm_current_el()
2737 * Note that we do not stop early on failure -- we will attempt
2754 * values in the list if the previous list->cpustate sync actually
2760 * Note that we do not stop early on failure -- we will attempt
2770 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
2774 * If EL3 is 64-bit:
2778 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2787 * If EL3 is 32-bit:
2796 * because they may differ in access permissions even if the VA->PA map is
2798 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2805 * which can be slow-pathed and always do a page table walk.
2817 * 7. we fold together most secure and non-secure regimes for A-profile,
2819 * process of switching between secure and non-secure is
2842 * R profile CPUs have an MPU, but can use the same set of MMU indexes
2844 * EL2 for cores like the Cortex-R52).
2859 * are not quite the same -- different CPU types (most notably M profile
2860 * vs A/R profile) would like to use MMU indexes with different semantics,
2894 * A-profile.
2916 /* TLBs with 1-1 mapping to the physical address spaces. */
2931 * M-profile.
2944 * Bit macros for the core-mmu-index values for each index,
3000 return idx - ARMMMUIdx_Phys_S; in arm_phys_to_space()
3008 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; in arm_v7m_csselr_razwi()
3014 /* We need not implement SCTLR.ITD in user-mode emulation, so in arm_sctlr_b()
3015 * let linux-user ignore the fact that it conflicts with SCTLR_B. in arm_sctlr_b()
3016 * This lets people run BE32 binaries with "-cpu any". in arm_sctlr_b()
3021 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; in arm_sctlr_b()
3032 * architecture (as word-invariant big-endianness), where loads in arm_cpu_data_is_big_endian_a32()
3037 * In user mode, however, we model BE32 as byte-invariant in arm_cpu_data_is_big_endian_a32()
3038 * big-endianness (because user-only code cannot tell the in arm_cpu_data_is_big_endian_a32()
3047 return env->uncached_cpsr & CPSR_E; in arm_cpu_data_is_big_endian_a32()
3055 /* Return true if the processor is in big-endian mode. */
3067 #include "exec/cpu-all.h"
3070 * We have more than 32-bits worth of state per TB, so we split the data
3071 * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
3078 * address size, flags2 always has 64-bits for A64, and a minimum of
3079 * 32-bits for A32 and M32.
3081 * The bits for 32-bit A-profile and M-profile partially overlap:
3084 * +-------------+----------+----------------+
3086 * | TBFLAG_AM32 | +-----+----------+
3088 * +-------------+----------------+----------+
3091 * Unless otherwise noted, these bits are cached in env->hflags.
3098 /* Target EL if we take a floating-point-disabled exception */
3107 * Bit usage when in AArch32 state, both A- and M-profile.
3113 * Bit usage when in AArch32 state, for A-profile only.
3140 * Bit usage when in AArch32 state, for M-profile only.
3144 /* Whether we should generate stack-limit checks */
3187 /* Set if FEAT_NV2 RAM accesses are big-endian */
3216 * Return the VL cached within env->hflags, in units of quadwords.
3220 return EX_TBFLAG_A64(env->hflags, VL) + 1; in sve_vq()
3227 * Return the SVL cached within env->hflags, in units of quadwords.
3231 return EX_TBFLAG_A64(env->hflags, SVL) + 1; in sme_vq()
3239 * would also end up as a mixed-endian mode with BE code, LE data. in bswap_code()
3290 * Note that if a pre-change hook is called, any registered post-change hooks
3303 * if pre-change hooks have been.
3316 * Return a pointer to the Dn register within env in 32-bit mode.
3320 return &env->vfp.zregs[regno >> 1].d[regno & 1]; in aa32_vfp_dreg()
3325 * Return a pointer to the Qn register within env in 32-bit mode.
3329 return &env->vfp.zregs[regno].d[0]; in aa32_vfp_qreg()
3334 * Return a pointer to the Qn register within env in 64-bit mode.
3338 return &env->vfp.zregs[regno].d[0]; in aa64_vfp_qreg()
3341 /* Shared between translate-sve.c and sve_helper.c. */
3345 * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
3371 * include/exec/cpu_ldst.h, and not some place linux-user specific.
3376 if (env->tagged_addr_enable) { in cpu_untagged_addr()