Lines Matching +full:v7 +full:- +full:r
3 * include/opcode/sparc.h, opcodes/sparc-opc.c, opcodes/sparc-dis.c
30 #include "disas/dis-asm.h"
33 the opcodes library in sparc-opc.c. If you change anything here, make
36 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
43 returns non-zero.
44 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
45 Don't change this without updating sparc-opc.c. */
62 #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
68 /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
77 EG: For v7 this would be
124 R frs2 floating point register (quad/multiple of 4).
156 r Single register that is both rs1 and rd.
221 fill-column: 131
222 comment-column: 0
225 /* opcodes/sparc-opc.c */
248 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
269 #define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ macro
397 'ld' pseudo-op in v9. */
838 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 },
839 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0]…
840 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 },
841 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 },
842 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 },
843 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d…
845 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 },
846 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g…
1001 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r…
1002 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i…
1004 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r…
1005 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i…
1007 … 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */
1008 … 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */
1010 … 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */
1011 … 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */
1013 … 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */
1014 … 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */
1017 { "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r…
1018 { "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i…
1019 { "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r…
1020 { "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i…
1021 { "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r…
1022 { "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i…
1024 …3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */
1025 { "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,…
1026 …3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */
1027 { "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,…
1028 …3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */
1029 { "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,…
1030 …3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */
1031 { "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,…
1032 …0, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */
1033 { "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,…
1034 … 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */
1035 { "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,…
1036 … 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */
1037 { "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,…
1038 …x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */
1039 { "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,…
1040 …0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */
1041 { "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,…
1042 … 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */
1043 { "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,…
1045 … 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */
1046 …(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */
1047 …9, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */
1048 …a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */
1049 …b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */
1051 …, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */
1052 …, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */
1053 … 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */
1054 …2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */
1055 … 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */
1057 … 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */
1058 … 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */
1059 … 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */
1060 … 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */
1061 …8, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */
1062 … 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */
1063 …, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */
1064 …RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */
1066 … F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */
1073 … F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d", 0, v9 }, /* rdhpr %hpriv,r */
1081 … F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
1082 … F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
1083 … F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */
1084 … F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */
1085 …2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */
1086 …2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */
1087 …2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */
1088 …2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */
1089 …2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */
1090 …2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */
1092 … F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */
1093 … F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */
1094 … F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */
1095 … F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */
1096 … F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */
1123 { "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs…
1124 { "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,…
1134 { "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,…
1135 { "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,…
1160 { "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, …
1161 { "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }…
1162 { "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, …
1163 { "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }…
1164 { "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, …
1165 { "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }…
1166 { "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, …
1167 { "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }…
1243 a single-line description of each condition value. John Gilmore. */
1245 /* Define branches -- one annulled, one without, etc. */
1355 { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 }
1457 #define FM_SF 1 /* v9 - values for fpsize */
1482 fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \
1487 fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \
1492 fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \
1664 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */
1666 { "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2…
1667 { "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,r…
1673 { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 },
1677 { "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 },
1689 { "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 },
1690 { "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 },
1695 { "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 },
1696 { "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1699 { "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 },
1700 { "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1707 { "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 },
1708 { "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 },
1709 { "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 },
1710 { "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 },
1713 { "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 },
1714 { "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1717 { "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 },
1718 { "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1721 { "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 },
1722 { "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1726 { "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 },
1727 { "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1730 { "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 },
1731 { "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1746 { "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_F…
1747 { "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F…
1748 { "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F…
1749 { "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F…
1750 { "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F…
1751 { "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_F…
1752 { "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F…
1753 { "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F…
1754 { "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F…
1755 { "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F…
1756 { "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_F…
1757 { "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F…
1758 { "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F…
1759 { "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F…
1760 { "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F…
1761 { "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_F…
1762 { "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F…
1763 { "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F…
1764 { "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F…
1765 { "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F…
1853 /*SLCBCC("cbn", 0), - already defined */
1861 /*SLCBCC("cba", 8), - already defined */
1881 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sr…
1883 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sr…
2026 for (p = table; p->name; ++p) in lookup_value()
2027 if (value == p->value) in lookup_value()
2028 return p->name; in lookup_value()
2226 /* opcodes/sparc-dis.c */
2250 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
2252 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
2275 /* Sign-extend a value which is N bits long. */
2277 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
2278 >> ((8 * sizeof (int)) - bits) )
2306 /* "ver" - special cased */
2321 rd and wr insns (-16). */
2336 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
2412 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) in is_delayed_branch()
2414 const sparc_opcode *opcode = op->opcode; in is_delayed_branch()
2416 if ((opcode->match & insn) == opcode->match in is_delayed_branch()
2417 && (opcode->lose & insn) == 0) in is_delayed_branch()
2418 return opcode->flags & F_DELAYED; in is_delayed_branch()
2468 unsigned long int match0 = op0->match, match1 = op1->match; in compare_opcodes()
2469 unsigned long int lose0 = op0->lose, lose1 = op1->lose; in compare_opcodes()
2477 if (op0->architecture & current_arch_mask) in compare_opcodes()
2479 if (! (op1->architecture & current_arch_mask)) in compare_opcodes()
2480 return -1; in compare_opcodes()
2484 if (op1->architecture & current_arch_mask) in compare_opcodes()
2486 else if (op0->architecture != op1->architecture) in compare_opcodes()
2487 return op0->architecture - op1->architecture; in compare_opcodes()
2496 /* xgettext:c-format */ in compare_opcodes()
2497 "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n", in compare_opcodes()
2498 op0->name, match0, lose0); in compare_opcodes()
2499 op0->lose &= ~op0->match; in compare_opcodes()
2500 lose0 = op0->lose; in compare_opcodes()
2507 /* xgettext:c-format */ in compare_opcodes()
2508 "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n", in compare_opcodes()
2509 op1->name, match1, lose1); in compare_opcodes()
2510 op1->lose &= ~op1->match; in compare_opcodes()
2511 lose1 = op1->lose; in compare_opcodes()
2523 return x1 - x0; in compare_opcodes()
2533 return x1 - x0; in compare_opcodes()
2541 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); in compare_opcodes()
2550 i = strcmp (op0->name, op1->name); in compare_opcodes()
2553 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ in compare_opcodes()
2557 /* xgettext:c-format */ in compare_opcodes()
2558 "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n", in compare_opcodes()
2559 op0->name, op1->name); in compare_opcodes()
2564 int length_diff = strlen (op0->args) - strlen (op1->args); in compare_opcodes()
2573 char *p0 = (char *) strchr (op0->args, '+'); in compare_opcodes()
2574 char *p1 = (char *) strchr (op1->args, '+'); in compare_opcodes()
2580 so the following [-1]'s are valid. */ in compare_opcodes()
2581 if (p0[-1] == 'i' && p1[1] == 'i') in compare_opcodes()
2584 if (p0[1] == 'i' && p1[-1] == 'i') in compare_opcodes()
2586 return -1; in compare_opcodes()
2592 int i0 = strncmp (op0->args, "i,1", 3) == 0; in compare_opcodes()
2593 int i1 = strncmp (op1->args, "i,1", 3) == 0; in compare_opcodes()
2596 return i0 - i1; in compare_opcodes()
2627 for (i = num_opcodes - 1; i >= 0; --i) in build_hash_table()
2629 int hash = HASH_INSN (opcode_table[i]->match); in build_hash_table()
2632 h->next = hash_table[hash]; in build_hash_table()
2633 h->opcode = opcode_table[i]; in build_hash_table()
2658 /* Print one instruction from MEMADDR on INFO->STREAM.
2669 FILE *stream = info->stream; in print_insn_sparc()
2680 || info->mach != current_mach) in print_insn_sparc()
2684 current_arch_mask = compute_arch_mask (info->mach); in print_insn_sparc()
2696 current_mach = info->mach; in print_insn_sparc()
2702 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); in print_insn_sparc()
2706 (*info->memory_error_func) (status, memaddr, info); in print_insn_sparc()
2707 return -1; in print_insn_sparc()
2712 are always big-endian even when the machine is in little-endian mode. */ in print_insn_sparc()
2713 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) in print_insn_sparc()
2720 info->insn_info_valid = 1; /* We do return this info. */ in print_insn_sparc()
2721 info->insn_type = dis_nonbranch; /* Assume non branch insn. */ in print_insn_sparc()
2722 info->branch_delay_insns = 0; /* Assume no delay. */ in print_insn_sparc()
2723 info->target = 0; /* Assume no target known. */ in print_insn_sparc()
2725 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) in print_insn_sparc()
2727 const sparc_opcode *opcode = op->opcode; in print_insn_sparc()
2730 if (! (opcode->architecture & current_arch_mask)) in print_insn_sparc()
2733 if ((opcode->match & insn) == opcode->match in print_insn_sparc()
2734 && (opcode->lose & insn) == 0) in print_insn_sparc()
2750 if (opcode->match == 0x80102000) /* or */ in print_insn_sparc()
2752 if (opcode->match == 0x80002000) /* add */ in print_insn_sparc()
2756 && strchr (opcode->args, 'r') != NULL) in print_insn_sparc()
2760 && strchr (opcode->args, 'O') != NULL) in print_insn_sparc()
2764 (*info->fprintf_func) (stream, "%s", opcode->name); in print_insn_sparc()
2769 if (opcode->args[0] != ',') in print_insn_sparc()
2770 (*info->fprintf_func) (stream, " "); in print_insn_sparc()
2772 for (s = opcode->args; *s != '\0'; ++s) in print_insn_sparc()
2776 (*info->fprintf_func) (stream, ","); in print_insn_sparc()
2781 (*info->fprintf_func) (stream, "a"); in print_insn_sparc()
2786 (*info->fprintf_func) (stream, "pn"); in print_insn_sparc()
2791 (*info->fprintf_func) (stream, "pt"); in print_insn_sparc()
2800 (*info->fprintf_func) (stream, " "); in print_insn_sparc()
2809 (*info->fprintf_func) (stream, "%c", *s); in print_insn_sparc()
2813 (*info->fprintf_func) (stream, "0"); in print_insn_sparc()
2816 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) in print_insn_sparc()
2818 case 'r': in print_insn_sparc()
2832 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) in print_insn_sparc()
2833 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) <… in print_insn_sparc()
2846 case 'R': /* Quad/multiple of 4. */ in print_insn_sparc()
2860 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) in print_insn_sparc()
2875 (*info->fprintf_func) (stream, "%%hi(%#x)", in print_insn_sparc()
2904 (*info->fprintf_func) (stream, "%d", imm); in print_insn_sparc()
2906 (*info->fprintf_func) (stream, "%#x", imm); in print_insn_sparc()
2916 (info->fprintf_func) (stream, "%d", imm); in print_insn_sparc()
2918 (info->fprintf_func) (stream, "%#x", (unsigned) imm); in print_insn_sparc()
2923 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3)); in print_insn_sparc()
2933 (info->fprintf_func) (stream, "0"); in print_insn_sparc()
2940 (info->fprintf_func) (stream, "|"); in print_insn_sparc()
2942 (info->fprintf_func) (stream, "%s", name); in print_insn_sparc()
2951 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; in print_insn_sparc()
2952 (*info->print_address_func) (info->target, info); in print_insn_sparc()
2956 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; in print_insn_sparc()
2957 (*info->print_address_func) (info->target, info); in print_insn_sparc()
2964 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); in print_insn_sparc()
2968 (*info->fprintf_func) (stream, "%%icc"); in print_insn_sparc()
2972 (*info->fprintf_func) (stream, "%%xcc"); in print_insn_sparc()
2976 (*info->fprintf_func) (stream, "%%ccr"); in print_insn_sparc()
2980 (*info->fprintf_func) (stream, "%%fprs"); in print_insn_sparc()
2984 (*info->fprintf_func) (stream, "%%asi"); in print_insn_sparc()
2988 (*info->fprintf_func) (stream, "%%tick"); in print_insn_sparc()
2992 (*info->fprintf_func) (stream, "%%pc"); in print_insn_sparc()
2997 (*info->fprintf_func) (stream, "%%ver"); in print_insn_sparc()
2999 (*info->fprintf_func) (stream, "%%%s", in print_insn_sparc()
3002 (*info->fprintf_func) (stream, "%%reserved"); in print_insn_sparc()
3007 (*info->fprintf_func) (stream, "%%%s", in print_insn_sparc()
3010 (*info->fprintf_func) (stream, "%%reserved"); in print_insn_sparc()
3015 (*info->fprintf_func) (stream, "%%%s", in print_insn_sparc()
3018 (*info->fprintf_func) (stream, "%%reserved"); in print_insn_sparc()
3023 (*info->fprintf_func) (stream, "%%%s", in print_insn_sparc()
3026 (*info->fprintf_func) (stream, "%%reserved"); in print_insn_sparc()
3031 (*info->fprintf_func) (stream, "%%reserved"); in print_insn_sparc()
3033 (*info->fprintf_func) (stream, "%%%s", in print_insn_sparc()
3034 v9a_asr_reg_names[X_RS1 (insn)-16]); in print_insn_sparc()
3039 (*info->fprintf_func) (stream, "%%reserved"); in print_insn_sparc()
3041 (*info->fprintf_func) (stream, "%%%s", in print_insn_sparc()
3042 v9a_asr_reg_names[X_RD (insn)-16]); in print_insn_sparc()
3050 (*info->fprintf_func) (stream, "%s", name); in print_insn_sparc()
3052 (*info->fprintf_func) (stream, "%ld", X_RD (insn)); in print_insn_sparc()
3057 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn)); in print_insn_sparc()
3061 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn)); in print_insn_sparc()
3065 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; in print_insn_sparc()
3066 (*info->print_address_func) (info->target, info); in print_insn_sparc()
3070 (*info->fprintf_func) in print_insn_sparc()
3075 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; in print_insn_sparc()
3076 (*info->print_address_func) (info->target, info); in print_insn_sparc()
3083 if ((info->mach == bfd_mach_sparc_v8plusa) || in print_insn_sparc()
3084 ((info->mach >= bfd_mach_sparc_v9) && in print_insn_sparc()
3085 (info->mach <= bfd_mach_sparc_v9b))) in print_insn_sparc()
3091 (*info->fprintf_func) (stream, "%s", name); in print_insn_sparc()
3093 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn)); in print_insn_sparc()
3098 (*info->fprintf_func) (stream, "%%csr"); in print_insn_sparc()
3102 (*info->fprintf_func) (stream, "%%fsr"); in print_insn_sparc()
3106 (*info->fprintf_func) (stream, "%%psr"); in print_insn_sparc()
3110 (*info->fprintf_func) (stream, "%%fq"); in print_insn_sparc()
3114 (*info->fprintf_func) (stream, "%%cq"); in print_insn_sparc()
3118 (*info->fprintf_func) (stream, "%%tbr"); in print_insn_sparc()
3122 (*info->fprintf_func) (stream, "%%wim"); in print_insn_sparc()
3126 (*info->fprintf_func) (stream, "%ld", in print_insn_sparc()
3132 (*info->fprintf_func) (stream, "%%y"); in print_insn_sparc()
3142 (*info->fprintf_func) (stream, "%s", name); in print_insn_sparc()
3144 (*info->fprintf_func) (stream, "%%cpreg(%d)", val); in print_insn_sparc()
3164 (*info->read_memory_func) in print_insn_sparc()
3165 (memaddr - 4, buffer, sizeof (buffer), info); in print_insn_sparc()
3184 errcode = (*info->read_memory_func) in print_insn_sparc()
3185 (memaddr - 8, buffer, sizeof (buffer), info); in print_insn_sparc()
3201 (*info->fprintf_func) (stream, "\t! "); in print_insn_sparc()
3202 info->target = in print_insn_sparc()
3206 info->target += X_SIMM (insn, 13); in print_insn_sparc()
3208 info->target |= X_SIMM (insn, 13); in print_insn_sparc()
3209 (*info->print_address_func) (info->target, info); in print_insn_sparc()
3210 info->insn_type = dis_dref; in print_insn_sparc()
3211 info->data_size = 4; /* FIXME!!! */ in print_insn_sparc()
3216 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) in print_insn_sparc()
3218 /* FIXME -- check is_annulled flag. */ in print_insn_sparc()
3219 if (opcode->flags & F_UNBR) in print_insn_sparc()
3220 info->insn_type = dis_branch; in print_insn_sparc()
3221 if (opcode->flags & F_CONDBR) in print_insn_sparc()
3222 info->insn_type = dis_condbranch; in print_insn_sparc()
3223 if (opcode->flags & F_JSR) in print_insn_sparc()
3224 info->insn_type = dis_jsr; in print_insn_sparc()
3225 if (opcode->flags & F_DELAYED) in print_insn_sparc()
3226 info->branch_delay_insns = 1; in print_insn_sparc()
3233 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */ in print_insn_sparc()
3234 (*info->fprintf_func) (stream, ".long %#08lx", insn); in print_insn_sparc()