Home
last modified time | relevance | path

Searched +full:v2p +full:- +full:ca15_a7 (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dvexpress-scc.txt2 -----------------------------------------------------
15 - compatible value: "arm,vexpress-scc,<model>", "arm,vexpress-scc";
18 eg. for Coretile Express A15x2 A7x3 (V2P-CA15_A7):
19 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
23 - reg: when the SCC is memory mapped, physical address and size of the
25 - interrupts: when the SCC can generate a system-level interrupt
30 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
H A Darm,vexpress-juno.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
37 further subvariants are released of the core tile, even more fine-granular
45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
49 - const: arm,vexpress,v2p-ca9
[all …]
H A Darm,cci-400.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 dtb-$(CONFIG_ARCH_INTEGRATOR) += \
4 integratorap-im-pd1.dtb \
6 dtb-$(CONFIG_ARCH_MPS2) += \
7 mps2-an385.dtb \
8 mps2-an399.dtb
9 dtb-$(CONFIG_ARCH_REALVIEW) += \
10 arm-realview-pb1176.dtb \
11 arm-realview-pb11mp.dtb \
12 arm-realview-eb.dtb \
[all …]
H A Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
/openbmc/linux/drivers/cpuidle/
H A Dcpuidle-big_little.c1 // SPDX-License-Identifier: GPL-2.0-only
41 * or in the MCPM back-ends.
47 * up and running when the CPU is powered up on cluster wake-up from shutdown.
70 .desc = "ARM little-cluster power down",
76 { .compatible = "arm,idle-state",
92 .desc = "ARM big-cluster power down",
117 * bl_enter_powerdown - Programs CPU to enter the specified state
149 return -ENOMEM; in bl_idle_driver_init()
155 drv->cpumask = cpumask; in bl_idle_driver_init()
161 { .compatible = "arm,vexpress,v2p-ca15_a7" },
[all …]
/openbmc/linux/arch/arm/mach-versatile/
H A Dtc2_pm.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright: (C) 2012-2013 Linaro Limited
17 #include <linux/irqchip/arm-gic.h>
20 #include <asm/proc-fns.h>
25 #include <linux/arm-cci.h>
50 return -EINVAL; in tc2_pm_cpu_powerup()
61 return -EINVAL; in tc2_pm_cluster_powerup()
98 * On the Cortex-A15 we need to disable in tc2_pm_cluster_cache_disable()
152 return -ETIMEDOUT; /* timeout */ in tc2_pm_wait_for_powerdown()
190 * Enable cluster-level coherency, in preparation for turning on the MMU.
[all …]