1ceca0e1cSPawel MollARM Versatile Express Serial Configuration Controller 2ceca0e1cSPawel Moll----------------------------------------------------- 3ceca0e1cSPawel Moll 4ceca0e1cSPawel MollTest chips for ARM Versatile Express platform implement SCC (Serial 5ceca0e1cSPawel MollConfiguration Controller) interface, used to set initial conditions 6ceca0e1cSPawel Mollfor the test chip. 7ceca0e1cSPawel Moll 8ceca0e1cSPawel MollIn some cases its registers are also mapped in normal address space 9ceca0e1cSPawel Molland can be used to obtain runtime information about the chip internals 10ceca0e1cSPawel Moll(like silicon temperature sensors) and as interface to other subsystems 11ceca0e1cSPawel Molllike platform configuration control and power management. 12ceca0e1cSPawel Moll 13ceca0e1cSPawel MollRequired properties: 14ceca0e1cSPawel Moll 15ceca0e1cSPawel Moll- compatible value: "arm,vexpress-scc,<model>", "arm,vexpress-scc"; 16ceca0e1cSPawel Moll where <model> is the full tile model name (as used 17ceca0e1cSPawel Moll in the tile's Technical Reference Manual), 18ceca0e1cSPawel Moll eg. for Coretile Express A15x2 A7x3 (V2P-CA15_A7): 19ceca0e1cSPawel Moll compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; 20ceca0e1cSPawel Moll 21ceca0e1cSPawel MollOptional properties: 22ceca0e1cSPawel Moll 23ceca0e1cSPawel Moll- reg: when the SCC is memory mapped, physical address and size of the 24ceca0e1cSPawel Moll registers window 25ceca0e1cSPawel Moll- interrupts: when the SCC can generate a system-level interrupt 26ceca0e1cSPawel Moll 27ceca0e1cSPawel MollExample: 28ceca0e1cSPawel Moll 29ceca0e1cSPawel Moll scc@7fff0000 { 30ceca0e1cSPawel Moll compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; 31ceca0e1cSPawel Moll reg = <0 0x7fff0000 0 0x1000>; 32ceca0e1cSPawel Moll interrupts = <0 95 4>; 33ceca0e1cSPawel Moll }; 34