| /openbmc/linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | ingenic,adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2019-2020 Artur Rojek
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Artur Rojek <contact@artur-rojek.eu>
17 ADC clients must use the format described in
18 https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml,
19 giving a phandle and IIO specifier pair ("io-channels") to the ADC controller.
24 - ingenic,jz4725b-adc
25 - ingenic,jz4740-adc
[all …]
|
| /openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | clock.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
11 /* Set of oscillator frequencies supported in the internal API. */
29 * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
53 * @param divm input divider
54 * @param divn feedback divider
55 * @param divp post divider 2^n
71 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
77 * Read low-level parameters of a PLL.
80 * @param divm returns input divider
[all …]
|
| /openbmc/linux/Documentation/hwmon/ |
| H A D | pc87360.rst | 22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
60 PC87366 11 3 3 3-4 0xE9
[all …]
|
| /openbmc/linux/drivers/hwmon/ |
| H A D | mlxreg-fan.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
27 * FAN datasheet defines the formula for RPM calculations as RPM = 15/t-high.
28 * The logic in a programmable device measures the time t-high by sampling the
29 * tachometer every t-sample (with the default value 11.32 uS) and increment
31 * RPM = 15 / (t-sample * (K + Regval)), where:
33 * - 0xff - represents tachometer fault;
34 * - 0xfe - represents tachometer minimum value , which is 4444 RPM;
35 * - 0x00 - represents tachometer maximum value , which is 300000 RPM;
39 * used: RPM = 15 / ((Regval + K) * 11.32) * 10^(-6)), which in the
42 * - for Regval 0x00, RPM will be 15000000 * 100 / (44 * 1132) = 30115;
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | nxp,sysctr-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bai Ping <ping.bai@nxp.com>
15 etc. it is intended for use in applications where the counter
21 const: nxp,sysctr-timer
32 clock-names:
35 nxp,no-divider:
36 description: if present, means there is no internal base clk divider.
[all …]
|
| /openbmc/linux/drivers/gpu/drm/pl111/ |
| H A D | pl111_drm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
8 * Copyright (c) 2006-2008 Intel Corporation
16 #include <linux/clk-provider.h>
27 * CLCD Controller Internal Register addresses
104 * struct pl111_variant_data - encodes IP differences
110 * @broken_clockdivider: the clock divider is broken and we need to
111 * use the supplied clock directly
144 /* The pixel clock (a reference to our clock divider off of CLCDCLK). */
146 /* pl111's internal clock divider. */
|
| /openbmc/linux/drivers/gpu/drm/amd/display/include/ |
| H A D | bios_parser_types.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
197 /* Input: Signal Type - to be converted to Encoder mode */
207 /* Output: If non-zero, this refDiv value should be used to calculate
210 /* Output: If non-zero, this postDiv value should be used to calculate
220 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
225 /* Calculated Reference divider of Display PLL */
227 /* Calculated Feedback divider of Display PLL */
229 /* Calculated Fractional Feedback divider of Display PLL */
[all …]
|
| /openbmc/linux/drivers/iio/imu/inv_mpu6050/ |
| H A D | inv_mpu_aux.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 TDK-InvenSense, Inc.
20 /* use 50hz frequency for xfer */ in inv_mpu_i2c_master_xfer()
29 ret = regmap_write(st->map, st->reg->sample_rate_div, d); in inv_mpu_i2c_master_xfer()
34 user_ctrl = st->chip_config.user_ctrl | INV_MPU6050_BIT_I2C_MST_EN; in inv_mpu_i2c_master_xfer()
35 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer()
39 /* wait for xfer: 1 period + half-period margin */ in inv_mpu_i2c_master_xfer()
43 user_ctrl = st->chip_config.user_ctrl; in inv_mpu_i2c_master_xfer()
44 ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); in inv_mpu_i2c_master_xfer()
49 d = st->chip_config.divider; in inv_mpu_i2c_master_xfer()
[all …]
|
| /openbmc/linux/arch/powerpc/platforms/512x/ |
| H A D | clock-commonclk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
39 /* extend the public set of clocks by adding internal slots for management */
65 /* internal, symbolic spec for the number of slots */
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
292 val &= (1 << len) - 1; in get_bit_field()
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
350 cpmf = get_bit_field(&clkregs->spmr, 16, 4); in get_cpmf_mult_x2()
[all …]
|
| /openbmc/linux/drivers/mmc/host/ |
| H A D | dw_mmc-starfive.c | 1 // SPDX-License-Identifier: GPL-2.0
18 #include "dw_mmc-pltfm.h"
36 if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) { in dw_mci_starfive_set_ios()
37 clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock; in dw_mci_starfive_set_ios()
38 ret = clk_set_rate(host->ciu_clk, clock); in dw_mci_starfive_set_ios()
40 dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock); in dw_mci_starfive_set_ios()
41 host->bus_hz = clk_get_rate(host->ciu_clk); in dw_mci_starfive_set_ios()
43 dev_dbg(host->dev, "Using the internal divider\n"); in dw_mci_starfive_set_ios()
51 struct dw_mci *host = slot->host; in dw_mci_starfive_execute_tuning()
52 struct starfive_priv *priv = host->priv; in dw_mci_starfive_execute_tuning()
[all …]
|
| /openbmc/linux/drivers/clk/sunxi/ |
| H A D | clk-a20-gmac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
28 * The external 125 MHz reference is optional, i.e. GMAC can use its
29 * internal TX clock just fine. The A31 GMAC clock module does not have
[all …]
|
| /openbmc/linux/sound/soc/fsl/ |
| H A D | fsl_asrc.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
14 #include <linux/dma/imx-dma.h>
26 dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
29 dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
32 dev_warn(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
110 * According to RM, the divider range is 1 ~ 8,
114 1, 2, 4, 8, 16, 32, 64, 128, /* divider = 1 */
115 2, 4, 8, 16, 32, 64, 128, 256, /* divider = 2 */
116 3, 6, 12, 24, 48, 96, 192, 384, /* divider = 3 */
[all …]
|
| /openbmc/u-boot/drivers/clk/aspeed/ |
| H A D | clk_ast2600.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <clk-uclass.h>
15 #include <dt-bindings/clock/ast2600-clock.h>
16 #include <dt-bindings/reset/ast2600-reset.h>
133 * Clock divider/multiplier configuration struct.
134 * For H-PLL and M-PLL the formula is
136 * M - Numerator
137 * N - Denumerator
138 * P - Post Divider
141 * D-PLL and D2-PLL have extra divider (OD + 1), which is not
[all …]
|
| /openbmc/linux/drivers/gpu/ipu-v3/ |
| H A D | ipu-di.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
14 #include <video/imx-ipu-v3.h>
15 #include "ipu-prv.h"
76 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1))
77 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1))
78 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2))
125 return readl(di->base + offset); in ipu_di_read()
130 writel(value, di->base + offset); in ipu_di_write()
166 if ((c->run_count >= 0x1000) || (c->offset_count >= 0x1000) || in ipu_di_sync_config()
[all …]
|
| /openbmc/linux/drivers/iio/adc/ |
| H A D | stm32-dfsdm-core.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
23 #include "stm32-dfsdm.h"
26 * struct stm32_dfsdm_dev_data - DFSDM compatible configuration data
96 unsigned int spi_clk_out_div; /* SPI clkout divider value */
113 ret = clk_prepare_enable(priv->clk); in stm32_dfsdm_clk_prepare_enable()
114 if (ret || !priv->aclk) in stm32_dfsdm_clk_prepare_enable()
117 ret = clk_prepare_enable(priv->aclk); in stm32_dfsdm_clk_prepare_enable()
119 clk_disable_unprepare(priv->clk); in stm32_dfsdm_clk_prepare_enable()
128 clk_disable_unprepare(priv->aclk); in stm32_dfsdm_clk_disable_unprepare()
[all …]
|
| /openbmc/linux/drivers/phy/amlogic/ |
| H A D | phy-meson-axg-mipi-dphy.c | 1 // SPDX-License-Identifier: GPL-2.0
33 * [11] mipi divider clk selection.
34 * 1: select the mipi DDRCLKHS from clock divider.
36 * [10] mipi clock divider control.
38 * [9] mipi divider output enable.
39 * [8] mipi divider counter enable.
46 * [1] write 1 to sync the txclkesc input. the internal logic have to
47 * use txclkesc to decide Txvalid and Txready.
53 * 1: from register. 0: use clk lane state machine.
188 ret = phy_init(priv->analog); in phy_meson_axg_mipi_dphy_init()
[all …]
|
| /openbmc/linux/drivers/clk/davinci/ |
| H A D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
24 #include <linux/platform_data/clk-davinci-pll.h>
80 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
87 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
91 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
97 * struct davinci_pll_clk - Main PLL clock (aka PLLOUT)
[all …]
|
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | silabs,si5341.txt | 6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
14 in turn can be directed to any of the 10 (or 4) outputs through a divider.
15 The internal structure of the clock generators can be found in [2].
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
36 "silabs,si5342" - Si5342 A/B/C/D
[all …]
|
| H A D | stericsson,u8500-clks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Linus Walleij <linus.walleij@linaro.org>
14 DB8500 digital baseband system-on-chip and its siblings such as
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
[all …]
|
| /openbmc/u-boot/arch/arm/mach-socfpga/ |
| H A D | clock_manager_arria10.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Intel Corporation
11 #include <dm/device-internal.h>
80 { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) },
81 { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) },
82 { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) },
83 { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) },
84 { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) },
85 { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) },
86 { "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) },
[all …]
|
| /openbmc/u-boot/drivers/serial/ |
| H A D | serial_pl01x.c | 1 // SPDX-License-Identifier: GPL-2.0+
11 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
37 if (readl(®s->fr) & UART_PL01x_FR_TXFF) in pl01x_putc()
38 return -EAGAIN; in pl01x_putc()
41 writel(c, ®s->dr); in pl01x_putc()
51 if (readl(®s->fr) & UART_PL01x_FR_RXFE) in pl01x_getc()
52 return -EAGAIN; in pl01x_getc()
54 data = readl(®s->dr); in pl01x_getc()
59 writel(0xFFFFFFFF, ®s->ecr); in pl01x_getc()
60 return -1; in pl01x_getc()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_display.c | 2 * Copyright 2007-8 Advanced Micro Devices, Inc.
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
52 struct drm_device *dev = crtc->dev; in avivo_crtc_load_lut()
53 struct radeon_device *rdev = dev->dev_private; in avivo_crtc_load_lut()
57 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in avivo_crtc_load_lut()
58 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
60 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
61 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
62 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
[all …]
|
| /openbmc/linux/include/linux/ |
| H A D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42 * struct clk_rate_request - Structure encoding the clk constraints that
[all …]
|
| /openbmc/linux/drivers/spi/ |
| H A D | spi-orion.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2007-2008 Marvell Ltd.
29 * It is up to the implementer to only use the chip selects
73 * have both is for managing the armada-370-spi case with old
110 return orion_spi->base + reg; in spi_reg()
144 orion_spi = spi_controller_get_devdata(spi->controller); in orion_spi_baudrate_set()
145 devdata = orion_spi->devdata; in orion_spi_baudrate_set()
147 tclk_hz = clk_get_rate(orion_spi->clk); in orion_spi_baudrate_set()
149 if (devdata->typ == ARMADA_SPI) { in orion_spi_baudrate_set()
160 /* best integer divider: */ in orion_spi_baudrate_set()
[all …]
|
| /openbmc/qemu/docs/devel/ |
| H A D | clocks.rst | 5 ----------------
28 +---------+ +----------------------+ +--------------+
30 | | | +-------+ +-------+ | | +-------+ |
31 | |>>-+-->>|Clock 2| |Clock 3|>>--->>|Clock 6| |
32 +---------+ | | | (in) | | (out) | | | | (in) | |
33 | | +-------+ +-------+ | | +-------+ |
34 | | +-------+ | +--------------+
36 | | | (out) | | +--------------+
37 | | +-------+ | | Device D |
38 | | +-------+ | | +-------+ |
[all …]
|