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/openbmc/linux/drivers/phy/allwinner/
H A Dphy-sun4i-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Allwinner sun4i USB phy driver
5 * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com>
18 #include <linux/extcon-provider.h>
28 #include <linux/phy/phy-sun4i-usb.h>
34 #include <linux/usb/of.h>
85 /* A83T specific control bits for PHY2 HSIC */
146 container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
154 iscr = readl(data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr()
157 writel(iscr, data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr()
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/openbmc/u-boot/board/freescale/ls2080aqds/
H A DREADME2 --------
3 The LS2080A Development System (QDS) is a high-performance computing,
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
15 -----------------------
16 - SERDES Connections, 16 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
19 - QSGMII
20 - SATA 3.0
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/openbmc/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-hsio-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HSIO blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the high-speed IO
15 (USB an PCIe) peripherals located in the HSIO domain of the SoC.
20 - const: fsl,imx8mp-hsio-blk-ctrl
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-openblocks-ax3-4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for OpenBlocks AX3-4 board
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include "armada-xp-mv78260.dtsi"
16 model = "PlatHome OpenBlocks AX3-4 board";
17 …compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell…
20 stdout-path = "serial0:115200n8";
[all …]
H A Darmada-385-db-ap.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * (DB-88F6820-AP)
11 /dts-v1/;
12 #include "armada-385.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
18 compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
21 stdout-path = "serial1:115200n8";
36 internal-regs {
38 pinctrl-names = "default";
39 pinctrl-0 = <&i2c0_pins>;
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H A Darmada-xp-gp.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-MV784MP-GP)
6 * Copyright (C) 2013-2014 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
22 /dts-v1/;
23 #include <dt-bindings/gpio/gpio.h>
24 #include "armada-xp-mv78460.dtsi"
27 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
[all …]
H A Darmada-xp-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * (DB-78460-BP)
6 * Copyright (C) 2012-2014 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
23 /dts-v1/;
24 #include "armada-xp-mv78460.dtsi"
28 …compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370…
31 stdout-path = "serial0:115200n8";
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/openbmc/linux/arch/arm/boot/dts/st/
H A Dstih410-b2120.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include "stihxxx-b2120.dtsi"
11 compatible = "st,stih410-b2120", "st,stih410";
14 stdout-path = &sbc_serial0;
27 usb2_picophy1: phy2 {
38 max-frequency = <200000000>;
39 sd-uhs-sdr50;
40 sd-uhs-sdr104;
41 sd-uhs-ddr50;
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H A Dstih418.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih418-clock.dtsi"
7 #include "stih407-family.dtsi"
8 #include "stih410-pinctrl.dtsi"
11 #address-cells = <1>;
12 #size-cells = <0>;
15 compatible = "arm,cortex-a9";
17 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
18 cpu-release-addr = <0x94100A4>;
22 compatible = "arm,cortex-a9";
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H A Dstih410-b2260.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "st,stih410-b2260", "st,stih410";
15 stdout-path = &uart1;
29 compatible = "gpio-leds";
30 led-user-green-1 {
33 linux,default-trigger = "heartbeat";
34 default-state = "off";
37 led-user-green-2 {
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H A Dstih410.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih410-clock.dtsi"
7 #include "stih407-family.dtsi"
8 #include "stih410-pinctrl.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
15 usb2_picophy1: phy2 {
16 compatible = "st,stih407-usb2-phy";
17 #phy-cells = <0>;
21 reset-names = "global", "port";
27 compatible = "st,stih407-usb2-phy";
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra USB PHY
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp1020utm-pc.dtsi2 * P1020 UTM-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
64 /* 512KB for u-boot Bootloader Image */
65 /* 512KB for u-boot Environment Variables */
67 label = "NOR U-Boot Image";
68 read-only;
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H A Dp1024rdb.dtsi2 * P1024 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
[all …]
H A Dp1010rdb.dtsi2 * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
64 /* 512KB for u-boot Bootloader Image */
65 /* 512KB for u-boot Environment Variables */
67 label = "NOR U-Boot Image";
68 read-only;
[all …]
H A Dp4080ds.dts4 * Copyright 2009 - 2015 Freescale Semiconductor Inc.
35 /include/ "p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
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/openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-usb.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
5 usb {
6 compatible = "simple-bus";
7 #address-cells = <2>;
8 #size-cells = <2>;
12 * Internally, USB bus to the interconnect can only address up
13 * to 40-bit
15 dma-ranges = <0 0 0 0 0x100 0x0>;
17 usbphy0: usb-phy@0 {
18 compatible = "brcm,sr-usb-combo-phy";
[all …]
/openbmc/u-boot/doc/device-tree-bindings/phy/
H A Dsun4i-usb-phy.txt1 Allwinner sun4i USB PHY
2 -----------------------
5 - compatible : should be one of
6 * allwinner,sun4i-a10-usb-phy
7 * allwinner,sun5i-a13-usb-phy
8 * allwinner,sun6i-a31-usb-phy
9 * allwinner,sun7i-a20-usb-phy
10 * allwinner,sun8i-a23-usb-phy
11 * allwinner,sun8i-a33-usb-phy
12 * allwinner,sun8i-a83t-usb-phy
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-xp-maxbcm.dts4 * Copyright (C) 2013-2014 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
51 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
58 /dts-v1/;
59 #include <dt-bindings/gpio/gpio.h>
60 #include "armada-xp-mv78460.dtsi"
64 …compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370…
67 stdout-path = "serial0:115200n8";
[all …]
H A Darmada-xp-gp.dts3 * (DB-MV784MP-GP)
5 * Copyright (C) 2013-2014 Marvell
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * This file is dual-licensed: you can use it either under the terms
52 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
59 /dts-v1/;
60 #include <dt-bindings/gpio/gpio.h>
61 #include "armada-xp-mv78460.dtsi"
64 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
[all …]
H A Darmada-8040-mcbin.dts1 // SPDX-License-Identifier: GPL-2.0
6 #include "armada-8040.dtsi" /* include SoC device tree */
9 model = "MACCHIATOBin-8040";
10 compatible = "marvell,armada8040-mcbin",
14 stdout-path = "serial0:115200n8";
31 simple-bus {
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <0>;
36 reg_usb3h0_vbus: usb3-vbus0 {
[all …]
H A Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: GPL-2.0
6 #include "armada-8040.dtsi"
9 model = "ClearFog-GT-8K";
10 compatible = "solidrun,clearfog-gt-8k",
14 stdout-path = "serial0:115200n8";
28 simple-bus {
29 compatible = "simple-bus";
31 reg_usb3h0_vbus: usb3-vbus0 {
32 compatible = "regulator-fixed";
33 pinctrl-names = "default";
[all …]
H A Dstih410-b2260.dts9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
15 compatible = "st,stih410-b2260", "st,stih410";
19 linux,stdout-path = &uart1;
20 stdout-path = &uart1;
36 compatible = "gpio-leds";
40 linux,default-trigger = "heartbeat";
41 default-state = "off";
47 default-state = "off";
53 default-state = "off";
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dehci-omap.c1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2004-2008
14 #include <usb.h>
15 #include <usb/ulpi.h>
20 #include <asm/ehci-omap.h>
33 rev = readl(&uhh->rev); in omap_uhh_reset()
36 writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc); in omap_uhh_reset()
41 while (!(readl(&uhh->syss) & 0x1)) { in omap_uhh_reset()
44 return -1; in omap_uhh_reset()
50 /* Set No-Idle, No-Standby */ in omap_uhh_reset()
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