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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dallwinner,sun9i-a80-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun9i-a80-usb-phy
25 - maxItems: 1
[all …]
H A Dqcom,usb-hsic-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hsic-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm USB HSIC PHY Controller
10 - Bjorn Andersson <andersson@kernel.org>
11 - Vinod Koul <vkoul@kernel.org>
16 - enum:
17 - qcom,usb-hsic-phy-mdm9615
18 - qcom,usb-hsic-phy-msm8974
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H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dpxa1928-usb-phy.txt1 * Marvell PXA1928 USB and HSIC PHYs
4 - compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy"
5 - reg: base address and length of the registers
6 - clocks - A single clock. From common clock binding.
7 - #phys-cells: should be 0. From common phy binding.
8 - resets: reference to the reset controller
12 usbphy: phy@7000 {
13 compatible = "marvell,pxa1928-usb-phy";
16 #phy-cells = <0>;
H A Dallwinner,sun8i-a83t-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-a83t-usb-phy
22 - description: PHY Control registers
[all …]
/openbmc/linux/drivers/phy/marvell/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Marvell platforms
6 bool "Armada 375 USB cluster PHY support" if COMPILE_TEST
12 tristate "Marvell Berlin SATA PHY driver"
17 Enable this to support the SATA PHY on Marvell Berlin SoCs.
20 tristate "Marvell Berlin USB PHY Driver"
25 Enable this to support the USB PHY on Marvell Berlin SoCs.
46 Enable this to support Marvell A3700 UTMI PHY driver.
56 used by various controllers (Ethernet, sata, usb, PCIe...).
67 lanes can be used by various controllers (Ethernet, sata, usb,
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY) += phy-armada375-usb2.o
3 obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o
4 obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o
5 obj-$(CONFIG_PHY_MMP3_USB) += phy-mmp3-usb.o
6 obj-$(CONFIG_PHY_MMP3_HSIC) += phy-mmp3-hsic.o
7 obj-$(CONFIG_PHY_MVEBU_A3700_COMPHY) += phy-mvebu-a3700-comphy.o
8 obj-$(CONFIG_PHY_MVEBU_A3700_UTMI) += phy-mvebu-a3700-utmi.o
9 obj-$(CONFIG_PHY_MVEBU_A38X_COMPHY) += phy-armada38x-comphy.o
10 obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o
[all …]
H A Dphy-mmp3-hsic.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/phy/phy.h>
17 static int mmp3_hsic_phy_init(struct phy *phy) in mmp3_hsic_phy_init() argument
19 void __iomem *base = (void __iomem *)phy_get_drvdata(phy); in mmp3_hsic_phy_init()
36 { .compatible = "marvell,mmp3-hsic-phy", },
43 struct device *dev = &pdev->dev; in mmp3_hsic_phy_probe()
46 struct phy *phy; in mmp3_hsic_phy_probe() local
52 phy = devm_phy_create(dev, NULL, &mmp3_hsic_phy_ops); in mmp3_hsic_phy_probe()
53 if (IS_ERR(phy)) { in mmp3_hsic_phy_probe()
54 dev_err(dev, "failed to create PHY\n"); in mmp3_hsic_phy_probe()
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt1 OMAP HS USB Host
5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dusb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic USB Controller
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
16 pattern: "^usb(@.*)?"
20 List of all the USB PHYs on this HCD
22 phy-names:
24 Name specifier for the USB PHY
[all …]
H A Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: USB2 ChipIdea USB controller
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
[all …]
H A Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
25 - const: nvidia,tegra132-xusb
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/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-usb-hsic.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/phy/phy.h>
10 #include <linux/pinctrl/pinctrl-state.h>
19 struct phy *phy; member
26 static int qcom_usb_hsic_phy_power_on(struct phy *phy) in qcom_usb_hsic_phy_power_on() argument
28 struct qcom_usb_hsic_phy *uphy = phy_get_drvdata(phy); in qcom_usb_hsic_phy_power_on()
29 struct ulpi *ulpi = uphy->ulpi; in qcom_usb_hsic_phy_power_on()
33 ret = clk_prepare_enable(uphy->phy_clk); in qcom_usb_hsic_phy_power_on()
37 ret = clk_prepare_enable(uphy->cal_clk); in qcom_usb_hsic_phy_power_on()
41 ret = clk_prepare_enable(uphy->cal_sleep_clk); in qcom_usb_hsic_phy_power_on()
[all …]
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm eDP PHY driver"
28 Enable this driver to support the Qualcomm eDP PHY found in various
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
3 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
4 obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o
5 obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
6 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
7 obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
8 obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
10 obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o
11 obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o
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/openbmc/linux/drivers/phy/tegra/
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/phy/phy.h>
13 #include <linux/phy/tegra/xusb.h>
24 static struct phy *tegra_xusb_pad_of_xlate(struct device *dev, in tegra_xusb_pad_of_xlate()
28 struct phy *phy = NULL; in tegra_xusb_pad_of_xlate() local
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
[all …]
/openbmc/linux/drivers/phy/samsung/
H A Dphy-exynos5250-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
11 #include <linux/phy/phy.h>
13 #include "phy-samsung-usb2.h"
15 /* Exynos USB PHY registers */
139 * can be written to the phy register.
168 return -EINVAL; in exynos5250_rate_to_clk()
176 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos5250_isol()
180 if (drv->cfg == &exynos5250_usb2_phy_config && in exynos5250_isol()
181 inst->cfg->id == EXYNOS5250_DEVICE) in exynos5250_isol()
[all …]
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun9i-a80-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
7 #include <linux/clk-provider.h>
15 #include "ccu-sun9i-a80-usb.h"
25 static SUNXI_CCU_GATE_DATA(bus_hci0_clk, "bus-hci0", clk_parent_bus, 0x0, BIT(1), 0);
26 static SUNXI_CCU_GATE_DATA(usb_ohci0_clk, "usb-ohci0", clk_parent_hosc, 0x0, BIT(2), 0);
27 static SUNXI_CCU_GATE_DATA(bus_hci1_clk, "bus-hci1", clk_parent_bus, 0x0, BIT(3), 0);
28 static SUNXI_CCU_GATE_DATA(bus_hci2_clk, "bus-hci2", clk_parent_bus, 0x0, BIT(5), 0);
29 static SUNXI_CCU_GATE_DATA(usb_ohci2_clk, "usb-ohci2", clk_parent_hosc, 0x0, BIT(6), 0);
31 static SUNXI_CCU_GATE_DATA(usb0_phy_clk, "usb0-phy", clk_parent_hosc, 0x4, BIT(1), 0);
[all …]
/openbmc/linux/drivers/phy/allwinner/
H A Dphy-sun9i-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Allwinner sun9i USB phy driver
5 * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
7 * Based on phy-sun4i-usb.c from
18 #include <linux/phy/phy.h>
19 #include <linux/usb/of.h>
29 /* usb1 HSIC specific bits */
36 struct phy *phy; member
44 static void sun9i_usb_phy_passby(struct sun9i_usb_phy *phy, int enable) in sun9i_usb_phy_passby() argument
52 if (phy->type == USBPHY_INTERFACE_MODE_HSIC) in sun9i_usb_phy_passby()
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dehci-exynos.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SAMSUNG EXYNOS USB HOST EHCI Controller
14 #include <usb.h>
36 * for the usb controller.
40 struct exynos_usb_phy *usb; member
47 const void *blob = gd->fdt_blob; in ehci_usb_ofdata_to_platdata()
54 plat->hcd_base = devfdt_get_addr(dev); in ehci_usb_ofdata_to_platdata()
55 if (plat->hcd_base == FDT_ADDR_T_NONE) { in ehci_usb_ofdata_to_platdata()
57 return -ENXIO; in ehci_usb_ofdata_to_platdata()
64 debug("XHCI: Can't get device node for usb3-phy controller\n"); in ehci_usb_ofdata_to_platdata()
[all …]
/openbmc/linux/drivers/usb/chipidea/
H A Dci_hdrc_imx.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <linux/usb/chipidea.h>
14 #include <linux/usb/of.h>
81 { .compatible = "fsl,imx23-usb", .data = &imx23_usb_data},
82 { .compatible = "fsl,imx28-usb", .data = &imx28_usb_data},
83 { .compatible = "fsl,imx27-usb", .data = &imx27_usb_data},
84 { .compatible = "fsl,imx6q-usb", .data = &imx6q_usb_data},
85 { .compatible = "fsl,imx6sl-usb", .data = &imx6sl_usb_data},
86 { .compatible = "fsl,imx6sx-usb", .data = &imx6sx_usb_data},
87 { .compatible = "fsl,imx6ul-usb", .data = &imx6ul_usb_data},
[all …]
H A Dci_hdrc_msm.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/usb/chipidea.h>
13 #include <linux/reset-controller.h>
44 bool hsic; member
52 void __iomem *addr = ci_msm->base; in ci_hdrc_msm_por_reset()
81 struct device *dev = ci->dev->parent; in ci_hdrc_msm_notify_event()
90 if (msm_ci->secondary_phy) { in ci_hdrc_msm_notify_event()
91 u32 val = readl_relaxed(msm_ci->base + HS_PHY_SEC_CTRL); in ci_hdrc_msm_notify_event()
93 writel_relaxed(val, msm_ci->base + HS_PHY_SEC_CTRL); in ci_hdrc_msm_notify_event()
96 ret = phy_init(ci->phy); in ci_hdrc_msm_notify_event()
[all …]
/openbmc/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra-xusb.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/phy/phy.h>
20 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
23 #include "../pinctrl-utils.h"
91 struct phy *phys[2];
99 writel(value, padctl->regs + offset); in padctl_writel()
105 return readl(padctl->regs + offset); in padctl_readl()
112 return padctl->soc->num_pins; in tegra_xusb_padctl_get_groups_count()
120 return padctl->soc->pins[group].name; in tegra_xusb_padctl_get_group_name()
129 * For the tegra-xusb pad controller groups are synonymous in tegra_xusb_padctl_get_group_pins()
[all …]

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