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/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
[all …]
/openbmc/linux/drivers/soc/fsl/qe/
H A Dtsa.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <dt-bindings/soc/cpm1-fsl,tsa.h>
33 /* SI mode register (32 bits) */
54 /* SI global mode register (8 bits) */
64 /* SI status register (8 bits) */
67 /* SI command register (8 bits) */
70 /* SI clock route register (32 bits) */
97 /* Serial interface RAM pointer register (32 bits) */
135 return container_of(tsa_serial, struct tsa, serials[tsa_serial->id]); in tsa_serial_get_tsa()
170 switch (tsa_serial->id) { in tsa_serial_connect()
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/openbmc/linux/drivers/spi/
H A Dspi-sh-msiof.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2014-2017 Glider bvba
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
86 #define SIMDR1_SYNCMD_MASK GENMASK(29, 28) /* SYNC Mode */
89 #define SIMDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
91 #define SIMDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
92 #define SIMDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
93 #define SIMDR1_FLD_MASK GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
98 #define SITMDR1_SYNCCH_MASK GENMASK(27, 26) /* Sync Signal Channel Select */
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/openbmc/u-boot/drivers/sound/
H A Dbroadwell_i2s.h1 /* SPDX-License-Identifier: GPL-2.0+ */
45 u32 reserved0[29]; /* 0x14 - 0x77 */
57 u32 reserved0[5]; /* 0x14 - 0x27 */
131 /* Reserved bits: 30:26, 23:19, 15:7, 4:2 */
139 /* Clock Sync Statu s*/
145 /* Receiver Time-out Interrupt */
176 /* Frame Rate Divider Control (0-7) */
188 /* Serial Clock Rate (0-4095) */
195 /* Frame Format */
229 /* DMA Tx Service Request Enable */
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/openbmc/linux/include/linux/
H A Dpxa2xx_ssp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * This driver supports the following PXA CPU/SSP ports:-
17 #include <linux/bits.h>
31 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
42 #define SSTSA (0x30) /* SSP Tx Timeslot Active */
48 /* Common PXA2xx bits first */
50 #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
51 #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */
64 #define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
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/openbmc/linux/drivers/tty/serial/
H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
71 * delay on PCI PowerMac hardware, it's dealt in HW by the MacIO chip,
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
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/openbmc/linux/sound/soc/fsl/
H A Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
18 // from 48000Hz not every frame has valid receive data, so the ratio
23 // provides us status bits when the read register is updated with *another*
25 // contains the same value) these status bits are not set. We work
26 // around this by not polling these bits but only wait a fixed delay.
35 #include <linux/delay.h>
43 #include <linux/dma/imx-dma.h>
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H A Dfsl_sai.c1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
8 #include <linux/delay.h>
23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
27 #include "imx-pcm.h"
45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
47 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's
56 int adir = (dir == TX) ? RX : TX; in fsl_sai_dir_is_synced()
58 /* current dir in async mode while opposite dir in sync mode */ in fsl_sai_dir_is_synced()
59 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
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/openbmc/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxilinx_dma.txt11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
24 - #dma-cells: Should be <1>, see "dmas" property below
25 - reg: Should contain VDMA registers location and length.
26 - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
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/openbmc/u-boot/drivers/video/
H A Dlogicore_dp_tx.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Driver for XILINX LogiCore DisplayPort v6.1 TX (Source)
31 /* The maximum pre-emphasis level is 3 */
42 * enum link_training_states - States for link training state machine
62 * struct aux_transaction - Description of an AUX channel transaction
76 * struct main_stream_attributes - Main stream attributes
87 * to the native internal 16-bit datapath
95 * @bits_per_color: Bits per color component
108 * @h_sync_width: Horizontal sync width (pixels)
110 * @h_sync_polarity: Horizontal sync polarity (0=neg|1=pos)
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H A Dmvebu_lcd.c1 // SPDX-License-Identifier: GPL-2.0+
113 for (i = 0; i < dram->num_cs; i++) { in mvebu_lcd_conf_mbus_registers()
114 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_lcd_conf_mbus_registers()
115 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | in mvebu_lcd_conf_mbus_registers()
116 (dram->mbus_dram_target_id << 4) | 1, in mvebu_lcd_conf_mbus_registers()
119 writel(cs->base & 0xffff0000, regs + MVEBU_LCD_WIN_BASE(i)); in mvebu_lcd_conf_mbus_registers()
128 int x = lcd_info->x_res; in mvebu_lcd_register_init()
129 int y = lcd_info->y_res; in mvebu_lcd_register_init()
144 * end (currently 1GB-64MB but also may be 2GB-64MB). in mvebu_lcd_register_init()
147 writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR0); in mvebu_lcd_register_init()
[all …]
/openbmc/qemu/hw/net/
H A De1000x_regs.h4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
111 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
115 * RW - register is both readable and writable
116 * RO - register is read only
117 * WO - register is write only
118 * R/clr - register is read only and is cleared when read
119 * A - register array
121 #define E1000_CTRL 0x00000 /* Device Control - RW */
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/openbmc/linux/sound/soc/bcm/
H A Dbcm2835-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
23 * Copyright 2007-2010 Freescale Semiconductor, Inc.
28 #include <linux/delay.h>
108 /* Frame length register is 10 bit, maximum length 1024 */
130 unsigned int provider = dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK; in bcm2835_i2s_start_clock()
132 if (dev->clk_prepared) in bcm2835_i2s_start_clock()
138 clk_prepare_enable(dev->clk); in bcm2835_i2s_start_clock()
139 dev->clk_prepared = true; in bcm2835_i2s_start_clock()
148 if (dev->clk_prepared) in bcm2835_i2s_stop_clock()
149 clk_disable_unprepare(dev->clk); in bcm2835_i2s_stop_clock()
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/openbmc/linux/Documentation/networking/dsa/
H A Dsja1105.rst8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath5k/
H A Dreg.h2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
42 * AR5210-Specific TXDP registers
46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
[all …]
/openbmc/linux/sound/soc/ti/
H A Ddavinci-mcasp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Multi-channel Audio Serial Port Driver
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
19 #include <linux/delay.h>
39 #include "edma-pcm.h"
40 #include "sdma-pcm.h"
41 #include "udma-pcm.h"
42 #include "davinci-mcasp.h"
136 void __iomem *reg = mcasp->base + offset; in mcasp_set_bits()
143 void __iomem *reg = mcasp->base + offset; in mcasp_clr_bits()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igc/
H A Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
88 /* Loop limit on how long we wait for auto-negotiation to complete */
161 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
162 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
170 /* 1000BASE-T Control Register */
174 /* 1000BASE-T Status Register */
180 #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */
189 /* NVM Addressing bits based on type 0=small, 1=large */
204 #define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
238 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
[all …]
/openbmc/linux/drivers/net/ethernet/cadence/
H A Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
33 #define MACB_TBQP 0x001c /* TX Q Base Address */
100 #define GEM_TXPTPUNI 0x00D8 /* PTP TX Unicast address */
101 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
102 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
103 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
104 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
112 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
113 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
[all …]
/openbmc/linux/drivers/net/ethernet/sun/
H A Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
45 * DEFAULT: 0x0, SIZE: 5 bits
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
65 * DEFAULT: 0x00000000, SIZE: 29 bits
68 #define INTR_TX_INTME 0x00000001 /* frame w/ INT ME desc bit set
[all …]
/openbmc/linux/drivers/net/wan/
H A Dfarsync.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
24 #include <linux/delay.h>
35 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
71 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
94 * file. Unfortunately various name clashes and the non-portability of the
136 volatile u8 hadr; /* High order address. Low 4 bits only, high 4
137 * bits must be zero
139 volatile u8 bits; /* Status and config */ member
[all …]
H A Dfarsync.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
23 * used with the FarSite T-Series cards (T2P & T4P) running in the high
24 * speed frame shifter mode. This is sometimes referred to as X.21 mode
30 * purpose (FarSite T-series).
33 * "hdlc" is already in use I've chosen the even less informative "sync"
37 #define FST_NDEV_NAME "sync" /* For net interface */
95 unsigned int valid; /* Bits of structure that are valid */
114 unsigned char startingSlot; /* Time slot to use for start of tx */
121 unsigned char lineBuildOut; /* 0, -7.5, -15, -22 */
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Ddefines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
65 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
74 /* mask to determine if packets should be dropped due to frame errors */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
238 /* 1000/H is not supported, nor spec-compliant. */
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
[all …]
/openbmc/linux/drivers/net/ieee802154/
H A Dadf7242.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Analog Devices ADF7242 Low-Power IEEE 802.15.4 Transceiver
5 * Copyright 2009-2017 Analog Devices Inc.
13 #include <linux/delay.h>
34 #define REG_TX_FSK_TEST 0x101 /* RW TX FSK test mode configuration */
39 #define REG_DELAYCFG0 0x109 /* RW RC_RX command to SFD or sync word delay */
40 #define REG_DELAYCFG1 0x10A /* RW RC_TX command to TX state */
41 #define REG_DELAYCFG2 0x10B /* RW Mac delay extension */
42 #define REG_SYNC_WORD0 0x10C /* RW sync word bits [7:0] of [23:0] */
43 #define REG_SYNC_WORD1 0x10D /* RW sync word bits [15:8] of [23:0] */
[all …]
/openbmc/linux/drivers/net/ethernet/dec/tulip/
H A Dtulip.h5 Written/copyright 1994-2001 by Donald Becker.
22 #include <linux/delay.h>
57 MC_HASH_ONLY = 0x00020, /* Hash-only multicast filter. */
129 /* register offset and bits for CFDD PCI config reg */
138 /* The bits in the CSR5 status registers, mostly interrupt sources. */
158 /* bit mask for CSR5 TX/RX process state */
184 /* The Tulip Rx and Tx buffer descriptors. */
211 * 'Frame Too Long', 'Runt' and 'Descriptor Error' flags generated
219 * 'Frame Too Long' flag is set if packet length including CRC exceeds
220 * 1518. However, a full sized VLAN tagged frame is 1522 bytes
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