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/openbmc/u-boot/doc/
H A DREADME.mpc85xx12 immediately on entry and keeps it set. It also uses a temporary TLB to keep a
40 TLB Entries during u-boot execution
47 1) TLB entry to overcome e500 v1/v2 debug restriction
49 TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
53 2) TLB entry for working in AS1
55 TLB Entry : 15
59 3) TLB entry for the stack during AS1
61 TLB Entry : 14
65 4) TLB entry for CCSRBAR during AS1 execution
67 TLB Entry : 13
[all …]
H A DREADME.mpc85xx-spin-table10 is more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of
20 TLB. While booting, they set up another TLB in AS=1 space and jump into
21 the new space. The new TLB covers the physical address of the spin table page,
/openbmc/qemu/target/ppc/
H A Dmmu_helper.c2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
46 /* Software driven TLB helpers */
49 ppc6xx_tlb_t *tlb; in ppc6xx_tlb_invalidate_all() local
53 tlb = &env->tlb.tlb6[nr]; in ppc6xx_tlb_invalidate_all()
54 pte_invalidate(&tlb->pte0); in ppc6xx_tlb_invalidate_all()
65 ppc6xx_tlb_t *tlb; in ppc6xx_tlb_invalidate_virt2() local
71 tlb = &env->tlb.tlb6[nr]; in ppc6xx_tlb_invalidate_virt2()
72 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { in ppc6xx_tlb_invalidate_virt2()
73 qemu_log_mask(CPU_LOG_MMU, "TLB invalidate %d/%d " in ppc6xx_tlb_invalidate_virt2()
75 pte_invalidate(&tlb->pte0); in ppc6xx_tlb_invalidate_virt2()
[all …]
H A Dmmu-booke.c2 * PowerPC BookE MMU, TLB emulation helpers for QEMU.
27 /* Generic TLB check function for embedded PowerPC implementations */
28 static bool ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb, in ppcemb_tlb_check() argument
35 if (!(tlb->prot & PAGE_VALID)) { in ppcemb_tlb_check()
38 mask = ~(tlb->size - 1); in ppcemb_tlb_check()
39 qemu_log_mask(CPU_LOG_MMU, "%s: TLB %d address " TARGET_FMT_lx in ppcemb_tlb_check()
41 __func__, i, address, pid, tlb->EPN, in ppcemb_tlb_check()
42 mask, (uint32_t)tlb->PID, tlb->prot); in ppcemb_tlb_check()
44 if (tlb->PID != 0 && tlb->PID != pid) { in ppcemb_tlb_check()
48 if ((address & mask) != tlb->EPN) { in ppcemb_tlb_check()
[all …]
H A Dmmu_common.c2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
74 /* Select TLB num in a way from address */ in ppc6xx_tlb_getnum()
76 /* Select TLB way */ in ppc6xx_tlb_getnum()
86 /* Software driven TLB helpers */
92 ppc6xx_tlb_t *tlb; in ppc6xx_tlb_check() local
100 ret = -1; /* No TLB found */ in ppc6xx_tlb_check()
103 tlb = &env->tlb.tlb6[nr]; in ppc6xx_tlb_check()
105 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) { in ppc6xx_tlb_check()
106 qemu_log_mask(CPU_LOG_MMU, "TLB %d/%d %s [" TARGET_FMT_lx in ppc6xx_tlb_check()
109 pte_is_valid(tlb->pte0) ? "valid" : "inval", in ppc6xx_tlb_check()
[all …]
/openbmc/qemu/target/mips/tcg/system/
H A Dtlb_helper.c2 * MIPS TLB (Translation lookaside buffer) helpers.
31 /* TLB management */
34 /* Discard entries from env->tlb[first] onwards. */ in r4k_mips_tlb_flush_extra()
35 while (env->tlb->tlb_in_use > first) { in r4k_mips_tlb_flush_extra()
36 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); in r4k_mips_tlb_flush_extra()
52 r4k_tlb_t *tlb; in r4k_fill_tlb() local
56 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_fill_tlb()
58 tlb->EHINV = 1; in r4k_fill_tlb()
61 tlb->EHINV = 0; in r4k_fill_tlb()
62 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); in r4k_fill_tlb()
[all …]
/openbmc/qemu/target/loongarch/tcg/
H A Dtlb_helper.c3 * QEMU LoongArch TLB helpers
43 /* No TLB match for a mapped address */ in raise_mmu_exception()
54 /* TLB match with no valid bit */ in raise_mmu_exception()
64 /* TLB match but 'D' bit is cleared */ in raise_mmu_exception()
102 LoongArchTLB *tlb = &env->tlb[index]; in invalidate_tlb_entry() local
105 uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V); in invalidate_tlb_entry()
106 uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V); in invalidate_tlb_entry()
107 uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); in invalidate_tlb_entry()
108 uint8_t tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); in invalidate_tlb_entry()
114 tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); in invalidate_tlb_entry()
[all …]
/openbmc/qemu/target/sh4/
H A Dmonitor.c30 static void print_tlb(Monitor *mon, int idx, tlb_t *tlb) in print_tlb() argument
32 monitor_printf(mon, " tlb%i:\t" in print_tlb()
37 tlb->asid, tlb->vpn, tlb->ppn, tlb->sz, tlb->size, in print_tlb()
38 tlb->v, tlb->sh, tlb->c, tlb->pr, in print_tlb()
39 tlb->d, tlb->wt); in print_tlb()
/openbmc/qemu/include/exec/
H A Dcputlb.h2 * Common CPU TLB handling
41 * @mmu_idx: mmu index of the tlb to modify
43 * @full: the details of the tlb entry
45 * Add an entry to @cpu tlb index @mmu_idx. All of the fields of
62 * @cpu: CPU to add this TLB entry for
67 * @mmu_idx: MMU index to insert TLB entry for
70 * Add an entry to this CPU's TLB (a mapping from virtual address
76 * which provoked the TLB miss.
100 * @cpu: CPU whose TLB should be flushed
103 * Flush one page from the TLB of the specified CPU, for all
[all …]
H A Dtlb-flags.h2 * TLB flags definition
23 * Flags returned for lookup of a TLB virtual address.
45 /* Set if TLB entry requires byte swap. */
47 /* Set if TLB entry contains a watchpoint. */
49 /* Set if TLB entry requires aligned accesses. */
51 /* Set if TLB entry writes ignored. */
53 /* Set if TLB entry is an IO callback. */
67 /* Zero if TLB entry is valid. */
69 /* Set if TLB entry references a clean RAM page. */
/openbmc/u-boot/board/freescale/mpc8541cds/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
28 * TLB 0: 16M Non-cacheable, guarded
37 * TLB 1: 256M Non-cacheable, guarded
45 * TLB 2: 256M Non-cacheable, guarded
53 * TLB 3: 256M Non-cacheable, guarded
61 * TLB 4: 256M Non-cacheable, guarded
69 * TLB 5: 64M Non-cacheable, guarded
79 * TLB 6: 64M Cacheable, non-guarded
87 * TLB 7: 1M Non-cacheable, guarded
/openbmc/u-boot/board/freescale/mpc8555cds/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
28 * TLB 0: 16M Non-cacheable, guarded
37 * TLB 1: 256M Non-cacheable, guarded
45 * TLB 2: 256M Non-cacheable, guarded
53 * TLB 3: 256M Non-cacheable, guarded
61 * TLB 4: 256M Non-cacheable, guarded
69 * TLB 5: 64M Non-cacheable, guarded
79 * TLB 6: 64M Cacheable, non-guarded
87 * TLB 7: 1M Non-cacheable, guarded
/openbmc/u-boot/board/sbc8548/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
31 * TLB 0: 64M Non-cacheable, guarded
44 * TLB 1: 1G Non-cacheable, guarded
53 * TLB 2: 64M Non-cacheable, guarded
64 * TLB 3: 64M Cacheable, non-guarded
72 * TLB 4: 64M Cacheable, non-guarded
82 * TLB 5: 16M Cacheable, non-guarded
94 * TLB 6: 64M Non-cacheable, guarded
102 * TLB 6: 4M Non-cacheable, guarded
110 * TLB 7: 4M Non-cacheable, guarded
/openbmc/u-boot/board/socrates/
H A Dtlb.c16 /* TLB 0 - for temp stack in cache */
32 * TLB 1: 64M Non-cacheable, guarded
41 * TLB 2: 256M Non-cacheable, guarded
49 * TLB 3: 256M Non-cacheable, guarded
58 * TLB 4: 1M Non-cacheable, guarded
67 * TLB 5: 64M Non-cacheable, guarded
78 * TLB 6: 64M Non-cacheable, guarded
88 * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
91 * Make sure the TLB count at the top of this table is correct.
/openbmc/u-boot/board/freescale/mpc8544ds/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
27 * TLB 0: 64M Non-cacheable, guarded
35 * TLB 1: 1G Non-cacheable, guarded
43 * TLB 2: 256M Non-cacheable, guarded
50 * TLB 3: 256M Non-cacheable, guarded
57 * TLB 4: 64M Non-cacheable, guarded
66 * TLB 5: 64M Non-cacheable, guarded
/openbmc/qemu/target/loongarch/
H A Dcpu-csr.h53 /* TLB related CSRs */
54 #define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */
59 #define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */
63 #define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
64 #define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */
160 /* TLB Refill CSRs */
161 #define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception address */
162 #define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */
163 #define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */
164 #define LOONGARCH_CSR_TLBRSAVE 0x8b /* KScratch for TLB refill */
[all …]
/openbmc/qemu/accel/tcg/
H A Dcputlb.c2 * Common CPU TLB handling
34 #include "exec/tlb-common.h"
40 #include "exec/tlb-flags.h"
47 #include "tlb-bounds.h"
128 /* Find the TLB index corresponding to the mmu_idx + address pair. */
132 uintptr_t size_mask = cpu->neg.tlb.f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS; in tlb_index()
137 /* Find the TLB entry corresponding to the mmu_idx + address pair. */
141 return &cpu->neg.tlb.f[mmu_idx].table[tlb_index(cpu, mmu_idx, addr)]; in tlb_entry()
167 * tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
168 * @desc: The CPUTLBDesc portion of the TLB
[all …]
/openbmc/qemu/qga/vss-win32/
H A Dmeson.build27 gen_tlb = custom_target('gen-tlb',
29 output: 'qga-vss.tlb',
30 command: [midl, '@INPUT@', '/tlb', '@OUTPUT@'])
32 gen_tlb = custom_target('gen-tlb',
34 output: 'qga-vss.tlb',
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dmmu.h136 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
137 extern void _tlbia(void); /* invalidate all TLB entries */
239 * operations when written/read. A TLB entry is created when the Mx_RPN
243 #define MI_CTR 784 /* Instruction TLB control register */
247 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
249 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
260 * about the last instruction TLB miss. When MI_RPN is written, bits in
261 * this register are used to create the TLB entry.
270 * For the instruction TLB, it contains bits that get loaded into the
271 * TLB entry when the MI_RPN is written.
[all …]
/openbmc/qemu/target/hppa/
H A Dmachine.c102 .name = "tlb entry",
112 * Zap the entire tlb, on-the-side data structures and all. in tlb_pre_load()
113 * Each tlb entry will have data re-filled by put_tlb. in tlb_pre_load()
115 memset(env->tlb, 0, sizeof(env->tlb)); in tlb_pre_load()
135 for (uint32_t i = 0; i < ARRAY_SIZE(env->tlb); ++i) { in tlb_post_load()
136 HPPATLBEntry *e = &env->tlb[i]; in tlb_post_load()
156 VMSTATE_ARRAY(tlb, CPUHPPAState,
157 ARRAY_SIZE(((CPUHPPAState *)0)->tlb),
164 .name = "env/tlb",
H A Dmem_helper.c107 is_btlb = ent < &env->tlb[HPPA_BTLB_ENTRIES(env)]; in hppa_flush_tlb_ent()
146 if (i < btlb_entries || i >= ARRAY_SIZE(env->tlb)) { in hppa_alloc_tlb_ent()
151 ent = &env->tlb[i]; in hppa_alloc_tlb_ent()
230 /* Find a valid tlb entry that matches the virtual address. */ in hppa_get_physical_address()
242 /* Map TLB access_rights field to QEMU protection. */ in hppa_get_physical_address()
297 * architectural TLB entry for the next access. in hppa_get_physical_address()
309 /* The D bit is not set -- TLB Dirty Bit Fault. */ in hppa_get_physical_address()
467 * Success! Store the translation into the QEMU TLB. in hppa_cpu_tlb_fill_align()
471 * because we record the large page here in the hppa tlb. in hppa_cpu_tlb_fill_align()
482 /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */
[all …]
/openbmc/qemu/target/mips/system/
H A Dphysaddr.c2 * MIPS TLB (Translation lookaside buffer) helpers.
28 * AdE? TLB? in is_seg_am_mapped()
49 /* Never AdE, TLB mapped if AM={1,2,3} */ in is_seg_am_mapped()
54 /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */ in is_seg_am_mapped()
59 /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */ in is_seg_am_mapped()
90 /* The segment is TLB mapped */ in get_seg_physical_address()
91 return env->tlb->map_address(env, physical, prot, real_address, in get_seg_physical_address()
148 ret = env->tlb->map_address(env, physical, prot, in get_physical_address()
157 ret = env->tlb->map_address(env, physical, prot, in get_physical_address()
198 ret = env->tlb->map_address(env, physical, prot, in get_physical_address()
/openbmc/u-boot/doc/device-tree-bindings/cpu/
H A Dnios2.txt44 altr,tlb-num-ways = <16>;
45 altr,tlb-num-entries = <128>;
46 altr,tlb-ptr-sz = <7>;
50 altr,fast-tlb-miss-addr = <0xc7fff400>;
/openbmc/qemu/target/mips/tcg/
H A Dexception.c103 [EXCP_TLBF] = "TLB refill",
115 [EXCP_LTLBL] = "TLB modify",
116 [EXCP_TLBL] = "TLB load",
117 [EXCP_TLBS] = "TLB store",
124 [EXCP_TLBXI] = "TLB execute-inhibit",
125 [EXCP_TLBRI] = "TLB read-inhibit",
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dtlb.c20 void invalidate_tlb(u8 tlb) in invalidate_tlb() argument
22 if (tlb == 0) in invalidate_tlb()
24 if (tlb == 1) in invalidate_tlb()
136 void set_tlb(u8 tlb, u32 epn, u64 rpn, in set_tlb() argument
142 if (tlb == 1) in set_tlb()
148 __func__, tsize, tlb, epn); in set_tlb()
152 _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0); in set_tlb()
161 if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) in set_tlb()
210 /* we found something, and its in the TLB we expect */ in find_tlb_idx()

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