| /openbmc/linux/include/asm-generic/ |
| H A D | tlb.h | 2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
53 * Finish in particular will issue a (final) TLB invalidate and free
88 * tlb_flush_mmu_tlbonly() - does the TLB invalidate (and resets
91 * tlb_flush_mmu() - in addition to the above TLB invalidate, also frees
108 * flush the entire TLB irrespective of the range. For instance
127 * returns the smallest TLB entry size unmapped in this range.
140 * This might be useful if your architecture has size specific TLB
[all …]
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| /openbmc/linux/mm/ |
| H A D | mmu_gather.c | 14 #include <asm/tlb.h>
18 static bool tlb_next_batch(struct mmu_gather *tlb) in tlb_next_batch() argument
23 if (tlb->delayed_rmap && tlb->active != &tlb->local) in tlb_next_batch()
26 batch = tlb->active; in tlb_next_batch()
28 tlb->active = batch->next; in tlb_next_batch()
32 if (tlb->batch_count == MAX_GATHER_BATCH_COUNT) in tlb_next_batch()
39 tlb->batch_count++; in tlb_next_batch()
44 tlb->active->next = batch; in tlb_next_batch()
45 tlb->active = batch; in tlb_next_batch()
64 * tlb_flush_rmaps - do pending rmap removals after we have flushed the TLB
[all …]
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| /openbmc/qemu/target/ppc/ |
| H A D | mmu_helper.c | 2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
45 /* Software driven TLB helpers */
48 ppc6xx_tlb_t *tlb; in ppc6xx_tlb_invalidate_all() local
52 tlb = &env->tlb.tlb6[nr]; in ppc6xx_tlb_invalidate_all()
53 pte_invalidate(&tlb->pte0); in ppc6xx_tlb_invalidate_all()
64 ppc6xx_tlb_t *tlb; in ppc6xx_tlb_invalidate_virt2() local
70 tlb = &env->tlb.tlb6[nr]; in ppc6xx_tlb_invalidate_virt2()
71 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { in ppc6xx_tlb_invalidate_virt2()
72 qemu_log_mask(CPU_LOG_MMU, "TLB invalidate %d/%d " in ppc6xx_tlb_invalidate_virt2()
74 pte_invalidate(&tlb->pte0); in ppc6xx_tlb_invalidate_virt2()
[all …]
|
| H A D | mmu-booke.c | 2 * PowerPC BookE MMU, TLB emulation helpers for QEMU.
27 /* Generic TLB check function for embedded PowerPC implementations */
28 static bool ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb, in ppcemb_tlb_check() argument
35 if (!(tlb->prot & PAGE_VALID)) { in ppcemb_tlb_check()
38 mask = ~(tlb->size - 1); in ppcemb_tlb_check()
39 qemu_log_mask(CPU_LOG_MMU, "%s: TLB %d address " TARGET_FMT_lx in ppcemb_tlb_check()
41 __func__, i, address, pid, tlb->EPN, in ppcemb_tlb_check()
42 mask, (uint32_t)tlb->PID, tlb->prot); in ppcemb_tlb_check()
44 if (tlb->PID != 0 && tlb->PID != pid) { in ppcemb_tlb_check()
48 if ((address & mask) != tlb->EPN) { in ppcemb_tlb_check()
[all …]
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| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | tlb.h | 3 * Based on arch/arm/include/asm/tlb.h
20 static void tlb_flush(struct mmu_gather *tlb);
22 #include <asm-generic/tlb.h>
29 static inline int tlb_get_level(struct mmu_gather *tlb) in tlb_get_level() argument
32 if (tlb->freed_tables) in tlb_get_level()
35 if (tlb->cleared_ptes && !(tlb->cleared_pmds || in tlb_get_level()
36 tlb->cleared_puds || in tlb_get_level()
37 tlb->cleared_p4ds)) in tlb_get_level()
40 if (tlb->cleared_pmds && !(tlb->cleared_ptes || in tlb_get_level()
41 tlb->cleared_puds || in tlb_get_level()
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | tlb.json | 4 …TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved …
8 …TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolv…
12 …TLB accesses caused by any memory load or store operation. Note that load or store instructions ca…
16 …ublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses in …
20 …ion": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch…
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …TLB driven by a memory access. Note that partial translations that also cause a table walk are cou…
32 … L2 TLB driven by a memory access. Partial translations that also cause a table walk are counted. …
36 …TLB refills caused by memory read operations. If there are multiple misses in the TLB that are res…
40 …TLB refills caused by data side memory write operations. If there are multiple misses in the TLB t…
[all …]
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| /openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | tlb.json | 4 …TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved …
8 …TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolv…
12 …TLB accesses caused by any memory load or store operation. Note that load or store instructions ca…
16 …ublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses in …
20 …ion": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch…
24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation…
28 …TLB driven by a memory access. Note that partial translations that also cause a table walk are cou…
32 … L2 TLB driven by a memory access. Partial translations that also cause a table walk are counted. …
36 …TLB refills caused by memory read operations. If there are multiple misses in the TLB that are res…
40 …TLB refills caused by data side memory write operations. If there are multiple misses in the TLB t…
[all …]
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| /openbmc/linux/arch/s390/include/asm/ |
| H A D | tlb.h | 6 * TLB flushing on s390 is complicated. The following requirement
14 * AND PURGE instruction that purges the TLB."
26 static inline void tlb_flush(struct mmu_gather *tlb);
27 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
38 #include <asm-generic/tlb.h>
42 * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page
48 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb, in __tlb_remove_page_size() argument
56 static inline void tlb_flush(struct mmu_gather *tlb) in tlb_flush() argument
58 __tlb_flush_mm_lazy(tlb->mm); in tlb_flush()
63 * page table from the tlb.
[all …]
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| /openbmc/u-boot/doc/ |
| H A D | README.mpc85xx | 12 immediately on entry and keeps it set. It also uses a temporary TLB to keep a
40 TLB Entries during u-boot execution
47 1) TLB entry to overcome e500 v1/v2 debug restriction
49 TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
53 2) TLB entry for working in AS1
55 TLB Entry : 15
59 3) TLB entry for the stack during AS1
61 TLB Entry : 14
65 4) TLB entry for CCSRBAR during AS1 execution
67 TLB Entry : 13
[all …]
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| /openbmc/qemu/target/mips/tcg/sysemu/ |
| H A D | tlb_helper.c | 2 * MIPS TLB (Translation lookaside buffer) helpers.
30 /* TLB management */
33 /* Discard entries from env->tlb[first] onwards. */ in r4k_mips_tlb_flush_extra()
34 while (env->tlb->tlb_in_use > first) { in r4k_mips_tlb_flush_extra()
35 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); in r4k_mips_tlb_flush_extra()
51 r4k_tlb_t *tlb; in r4k_fill_tlb() local
55 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_fill_tlb()
57 tlb->EHINV = 1; in r4k_fill_tlb()
60 tlb->EHINV = 0; in r4k_fill_tlb()
61 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); in r4k_fill_tlb()
[all …]
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| /openbmc/qemu/target/loongarch/tcg/ |
| H A D | tlb_helper.c | 3 * QEMU LoongArch TLB helpers
61 /* No TLB match for a mapped address */ in raise_mmu_exception()
72 /* TLB match with no valid bit */ in raise_mmu_exception()
82 /* TLB match but 'D' bit is cleared */ in raise_mmu_exception()
120 LoongArchTLB *tlb = &env->tlb[index]; in invalidate_tlb_entry() local
123 uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V); in invalidate_tlb_entry()
124 uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V); in invalidate_tlb_entry()
125 uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); in invalidate_tlb_entry()
128 tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); in invalidate_tlb_entry()
150 LoongArchTLB *tlb; in invalidate_tlb() local
[all …]
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| /openbmc/linux/arch/loongarch/include/asm/ |
| H A D | tlb.h | 13 * TLB Invalidate Flush
26 * TLB R/W operations.
49 /* Invalid all tlb */
51 /* Invalid current tlb */
53 /* Invalid all global=1 lines in current tlb */
55 /* Invalid all global=0 lines in current tlb */
57 /* Invalid global=0 and matched asid lines in current tlb */
59 /* Invalid addr with global=0 and matched asid in current tlb */
61 /* Invalid addr with global=1 or matched asid in current tlb */
63 /* Invalid matched gid in guest tlb */
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/powerpc/power8/ |
| H A D | translation.json | 5 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G",
11 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M",
17 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K",
23 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K",
29 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another …
41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data…
47 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc…
53 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d…
59 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…
[all …]
|
| /openbmc/linux/arch/riscv/include/asm/ |
| H A D | tlb.h | 11 static void tlb_flush(struct mmu_gather *tlb);
14 #include <asm-generic/tlb.h>
16 static inline void tlb_flush(struct mmu_gather *tlb) in tlb_flush() argument
19 if (tlb->fullmm || tlb->need_flush_all || tlb->freed_tables) in tlb_flush()
20 flush_tlb_mm(tlb->mm); in tlb_flush()
22 flush_tlb_mm_range(tlb->mm, tlb->start, tlb->end, in tlb_flush()
23 tlb_get_unmap_size(tlb)); in tlb_flush()
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | virtual-memory.json | 6 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
14 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
28 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
31 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
39 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
47 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
55 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
71 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
79 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
93 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | virtual-memory.json | 6 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
14 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
28 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
31 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
39 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
47 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
55 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
71 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
79 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
93 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | virtual-memory.json | 6 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
14 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
28 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
31 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
39 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
47 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
55 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
71 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal…
79 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
93 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | virtual-memory.json | 6 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
20 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
31 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
39 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
47 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
63 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
77 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
80 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can …
88 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
[all …]
|
| /openbmc/linux/arch/mips/kvm/ |
| H A D | tlb.c | 6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
92 * Sets the root GuestID to match the current guest GuestID, for TLB operation
93 * on the GPA->RPA mappings in the root TLB.
96 * possibly longer if TLB registers are modified.
121 /* Set root GuestID for root probe and write of guest TLB entry */ in kvm_vz_host_tlb_inv()
137 * We don't want to get reserved instruction exceptions for missing tlb in kvm_vz_host_tlb_inv()
153 * kvm_vz_guest_tlb_lookup() - Lookup a guest VZ TLB mapping.
155 * @gpa: Guest virtual address in a TLB mapped guest segment.
[all …]
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| /openbmc/linux/arch/x86/include/asm/ |
| H A D | tlb.h | 6 static inline void tlb_flush(struct mmu_gather *tlb);
8 #include <asm-generic/tlb.h>
10 static inline void tlb_flush(struct mmu_gather *tlb) in tlb_flush() argument
13 unsigned int stride_shift = tlb_get_unmap_shift(tlb); in tlb_flush()
15 if (!tlb->fullmm && !tlb->need_flush_all) { in tlb_flush()
16 start = tlb->start; in tlb_flush()
17 end = tlb->end; in tlb_flush()
20 flush_tlb_mm_range(tlb->mm, start, end, stride_shift, tlb->freed_tables); in tlb_flush()
24 * While x86 architecture in general requires an IPI to perform TLB
29 * below 'ifdef CONFIG_MMU_GATHER_RCU_TABLE_FREE' in include/asm-generic/tlb.h
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | virtual-memory.json | 6 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
20 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
31 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
39 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
47 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
63 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
77 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
80 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can …
88 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | virtual-memory.json | 6 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
20 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
31 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
39 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
55 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
69 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
72 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can …
80 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
88 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | virtual-memory.json | 6 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
20 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
31 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
39 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
55 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
69 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
72 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can …
80 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
88 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | virtual-memory.json | 6 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
20 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
31 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
39 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
55 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
69 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
72 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can …
80 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to …
88 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to …
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | virtual-memory.json | 6 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).…
25 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma…
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
34 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can …
43 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
52 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
61 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can …
79 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
98 …res whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma…
104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
[all …]
|