| /openbmc/linux/drivers/gpu/drm/tegra/ |
| H A D | mipi-phy.c | 16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
24 timing->clktermen = 0; in mipi_dphy_timing_get_default()
25 timing->clktrail = 80; in mipi_dphy_timing_get_default()
26 timing->clkzero = 260; in mipi_dphy_timing_get_default()
27 timing->dtermen = 0; in mipi_dphy_timing_get_default()
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| /openbmc/linux/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy.c | 28 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
35 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
46 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
47 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
50 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, in msm_dsi_dphy_timing_calc() argument
72 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true); in msm_dsi_dphy_timing_calc()
76 timing->hs_rqst = temp; in msm_dsi_dphy_timing_calc()
78 timing->hs_rqst = max_t(s32, 0, temp - 2); in msm_dsi_dphy_timing_calc()
81 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2); in msm_dsi_dphy_timing_calc()
86 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true); in msm_dsi_dphy_timing_calc()
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| H A D | dsi_phy_20nm.c | 11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
16 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_20nm_dphy_set_timing()
18 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_20nm_dphy_set_timing()
20 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
25 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_20nm_dphy_set_timing()
27 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_20nm_dphy_set_timing()
29 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_20nm_dphy_set_timing()
31 DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); in dsi_20nm_dphy_set_timing()
33 DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); in dsi_20nm_dphy_set_timing()
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| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk-tegra124-emc.c | 48 * When we change the timing to a timing with a parent that has the same
50 * timing that has a different clock source.
120 struct emc_timing *timing = NULL; in emc_determine_rate() local
136 timing = tegra->timings + i; in emc_determine_rate()
138 if (timing->rate < req->rate && i != t - 1) in emc_determine_rate()
141 if (timing->rate > req->max_rate) { in emc_determine_rate()
147 if (timing->rate < req->min_rate) in emc_determine_rate()
150 req->rate = timing->rate; in emc_determine_rate()
154 if (timing) { in emc_determine_rate()
155 req->rate = timing->rate; in emc_determine_rate()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_validation.c | 27 * This file owns timing validation against various link limitations. (ex.
38 static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing) in get_tmds_output_pixel_clock_100hz() argument
41 uint32_t pxl_clk = timing->pix_clk_100hz; in get_tmds_output_pixel_clock_100hz()
43 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in get_tmds_output_pixel_clock_100hz()
45 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in get_tmds_output_pixel_clock_100hz()
48 if (timing->display_color_depth == COLOR_DEPTH_101010) in get_tmds_output_pixel_clock_100hz()
50 else if (timing->display_color_depth == COLOR_DEPTH_121212) in get_tmds_output_pixel_clock_100hz()
57 const struct dc_crtc_timing *timing, in dp_active_dongle_validate_timing() argument
66 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) in dp_active_dongle_validate_timing()
77 switch (timing->pixel_encoding) { in dp_active_dongle_validate_timing()
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| /openbmc/u-boot/drivers/video/tegra124/ |
| H A D | display.c | 25 static int tegra_dc_calc_refresh(const struct display_timing *timing) in tegra_dc_calc_refresh() argument
28 int pclk = timing->pixelclock.typ; in tegra_dc_calc_refresh()
30 h_total = timing->hactive.typ + timing->hfront_porch.typ + in tegra_dc_calc_refresh()
31 timing->hback_porch.typ + timing->hsync_len.typ; in tegra_dc_calc_refresh()
32 v_total = timing->vactive.typ + timing->vfront_porch.typ + in tegra_dc_calc_refresh()
33 timing->vback_porch.typ + timing->vsync_len.typ; in tegra_dc_calc_refresh()
43 static void print_mode(const struct display_timing *timing) in print_mode() argument
45 int refresh = tegra_dc_calc_refresh(timing); in print_mode()
48 timing->hactive.typ, timing->vactive.typ, refresh / 1000, in print_mode()
49 refresh % 1000, timing->pixelclock.typ); in print_mode()
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| /openbmc/u-boot/drivers/video/ |
| H A D | atmel_lcdfb.c | 32 struct display_timing timing; member
114 static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix, in atmel_fb_init() argument
134 value = (timing->hactive.typ * timing->vactive.typ * in atmel_fb_init()
140 value = get_lcdc_clk_rate(0) / timing->pixelclock.typ; in atmel_fb_init()
141 if (get_lcdc_clk_rate(0) % timing->pixelclock.typ) in atmel_fb_init()
156 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)) in atmel_fb_init()
158 if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)) in atmel_fb_init()
163 /* Vertical timing */ in atmel_fb_init()
164 value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET; in atmel_fb_init()
165 value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET; in atmel_fb_init()
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| /openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_encoder_phys_vid.c | 45 struct dpu_hw_intf_timing_params *timing) in drm_mode_to_intf_timing_params() argument
47 memset(timing, 0, sizeof(*timing)); in drm_mode_to_intf_timing_params()
74 timing->width = mode->hdisplay; /* active width */ in drm_mode_to_intf_timing_params()
75 timing->height = mode->vdisplay; /* active height */ in drm_mode_to_intf_timing_params()
76 timing->xres = timing->width; in drm_mode_to_intf_timing_params()
77 timing->yres = timing->height; in drm_mode_to_intf_timing_params()
78 timing->h_back_porch = mode->htotal - mode->hsync_end; in drm_mode_to_intf_timing_params()
79 timing->h_front_porch = mode->hsync_start - mode->hdisplay; in drm_mode_to_intf_timing_params()
80 timing->v_back_porch = mode->vtotal - mode->vsync_end; in drm_mode_to_intf_timing_params()
81 timing->v_front_porch = mode->vsync_start - mode->vdisplay; in drm_mode_to_intf_timing_params()
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| H A D | timing.c | 26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_optc.c | 42 bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) in optc201_is_two_pixels_per_containter() argument
44 return optc1_is_two_pixels_per_containter(timing); in optc201_is_two_pixels_per_containter()
76 const struct dc_crtc_timing *timing) in optc201_validate_timing() argument
83 ASSERT(timing != NULL); in optc201_validate_timing()
85 v_blank = (timing->v_total - timing->v_addressable - in optc201_validate_timing()
86 timing->v_border_top - timing->v_border_bottom); in optc201_validate_timing()
88 h_blank = (timing->h_total - timing->h_addressable - in optc201_validate_timing()
89 timing->h_border_right - in optc201_validate_timing()
90 timing->h_border_left); in optc201_validate_timing()
92 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && in optc201_validate_timing()
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| /openbmc/linux/drivers/video/fbdev/ |
| H A D | gbefb.c | 37 struct gbe_timing_info timing; member
410 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) in gbefb_setup_flatpanel() argument
416 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
418 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
426 timing->pll_m = 4; in gbefb_setup_flatpanel()
427 timing->pll_n = 1; in gbefb_setup_flatpanel()
428 timing->pll_p = 0; in gbefb_setup_flatpanel()
455 struct gbe_timing_info *timing) in compute_gbe_timing() argument
466 /* Determine valid resolution and timing in compute_gbe_timing()
502 /* set video timing information */ in compute_gbe_timing()
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| /openbmc/linux/drivers/video/fbdev/via/ |
| H A D | via_modesetting.c | 18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
27 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
28 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
29 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
30 raw.ver_blank_start = timing->ver_blank_start - 1; in via_set_primary_timing()
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| /openbmc/linux/drivers/memory/tegra/ |
| H A D | tegra124-emc.c | 516 /* Timing change sequence functions */
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
577 struct emc_timing *timing = NULL; in tegra_emc_find_timing() local
582 timing = &emc->timings[i]; in tegra_emc_find_timing()
587 if (!timing) { in tegra_emc_find_timing()
588 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
592 return timing; in tegra_emc_find_timing()
598 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_prepare_timing_change() local
606 if (!timing) in tegra_emc_prepare_timing_change()
609 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) in tegra_emc_prepare_timing_change()
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| /openbmc/linux/drivers/gpu/drm/sti/ |
| H A D | sti_awg_utils.c | 122 struct awg_timing *timing) in awg_generate_line_signal() argument
127 if (timing->trailing_pixels > 0) { in awg_generate_line_signal()
129 val = timing->blanking_level; in awg_generate_line_signal()
132 val = timing->trailing_pixels - 1 + AWG_DELAY; in awg_generate_line_signal()
137 val = timing->blanking_level; in awg_generate_line_signal()
138 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, in awg_generate_line_signal()
141 if (timing->blanking_pixels > 0) { in awg_generate_line_signal()
143 val = timing->active_pixels - 1; in awg_generate_line_signal()
147 val = timing->blanking_level; in awg_generate_line_signal()
156 struct awg_timing *timing) in sti_awg_generate_code_data_enable_mode() argument
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| /openbmc/u-boot/drivers/ram/ |
| H A D | stm32_sdram.c | 21 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
23 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
25 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
27 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
33 u32 pmem; /* Common memory space timing register */
34 u32 patt; /* Attribute memory space timing registers */
40 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */
42 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */
44 u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */
46 u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dsc/ |
| H A D | dc_dsc.c | 56 const struct dc_crtc_timing *timing, const uint32_t kbps) in apply_128b_132b_stream_overhead() argument
63 if (!timing->flags.DSC) { in apply_128b_132b_stream_overhead()
68 bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10); in apply_128b_132b_stream_overhead()
73 overhead_factor = dc_fixpt_from_int(timing->h_addressable); in apply_128b_132b_stream_overhead()
88 const struct dc_crtc_timing *timing, in dc_bandwidth_in_kbps_from_timing() argument
94 if (timing->flags.DSC) in dc_bandwidth_in_kbps_from_timing()
95 return dc_dsc_stream_bandwidth_in_kbps(timing, in dc_bandwidth_in_kbps_from_timing()
96 timing->dsc_cfg.bits_per_pixel, in dc_bandwidth_in_kbps_from_timing()
97 timing->dsc_cfg.num_slices_h, in dc_bandwidth_in_kbps_from_timing()
98 timing->dsc_cfg.is_dp); in dc_bandwidth_in_kbps_from_timing()
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| /openbmc/linux/drivers/media/rc/img-ir/ |
| H A D | img-ir-hw.h | 22 /* Timing information */
53 * struct img_ir_timing_range - range of timing values
54 * @min: Minimum timing value
55 * @max: Maximum timing value (if < @min, this will be set to @min during
65 * struct img_ir_symbol_timing - timing data for a symbol
66 * @pulse: Timing range for the length of the pulse in this symbol
67 * @space: Timing range for the length of the space in this symbol
75 * struct img_ir_free_timing - timing data for free time symbol
88 * struct img_ir_timings - Timing values.
89 * @ldr: Leader symbol timing data
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_timing_generator_v.c | 45 * DCE11 Timing Generator Implementation
243 const struct dc_crtc_timing *timing) in dce110_timing_generator_v_program_blanking() argument
245 uint32_t vsync_offset = timing->v_border_bottom + in dce110_timing_generator_v_program_blanking()
246 timing->v_front_porch; in dce110_timing_generator_v_program_blanking()
247 uint32_t v_sync_start = timing->v_addressable + vsync_offset; in dce110_timing_generator_v_program_blanking()
249 uint32_t hsync_offset = timing->h_border_right + in dce110_timing_generator_v_program_blanking()
250 timing->h_front_porch; in dce110_timing_generator_v_program_blanking()
251 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_v_program_blanking()
262 timing->h_total - 1, in dce110_timing_generator_v_program_blanking()
271 timing->v_total - 1, in dce110_timing_generator_v_program_blanking()
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | ramnv50.c | 34 #include <subdev/bios/timing.h>
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
114 timing[2] = (T(CWL) - 1) << 24 | in nv50_ram_timing_calc()
118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | in nv50_ram_timing_calc()
122 timing[4] = (cur4 & 0xffff0000) | in nv50_ram_timing_calc()
125 timing[5] = T(RFC) << 24 | in nv50_ram_timing_calc()
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| /openbmc/u-boot/board/xilinx/zynqmp/ |
| H A D | tap_delays.c | 84 static void arasan_zynqmp_tap_sdr104(u8 deviceid, u8 timing, u8 bank) in arasan_zynqmp_tap_sdr104() argument
105 static void arasan_zynqmp_tap_hs(u8 deviceid, u8 timing, u8 bank) in arasan_zynqmp_tap_hs() argument
117 if (timing == MMC_TIMING_MMC_HS) in arasan_zynqmp_tap_hs()
133 if (timing == MMC_TIMING_MMC_HS) in arasan_zynqmp_tap_hs()
142 static void arasan_zynqmp_tap_ddr50(u8 deviceid, u8 timing, u8 bank) in arasan_zynqmp_tap_ddr50() argument
150 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
158 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
170 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
178 if (timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_tap_ddr50()
187 static void arasan_zynqmp_tap_sdr50(u8 deviceid, u8 timing, u8 bank) in arasan_zynqmp_tap_sdr50() argument
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| /openbmc/u-boot/common/ |
| H A D | edid.c | 68 /* Set all parts of a timing entry to the same value */
77 * decode_timing() - Decoding an 18-byte detailed timing record
79 * @buf: Pointer to EDID detailed timing record
80 * @timing: Place to put timing
82 static void decode_timing(u8 *buf, struct display_timing *timing) in decode_timing() argument
90 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); in decode_timing()
104 set_entry(&timing->hactive, ha); in decode_timing()
105 set_entry(&timing->hfront_porch, hso); in decode_timing()
106 set_entry(&timing->hback_porch, hbl - hso - hspw); in decode_timing()
107 set_entry(&timing->hsync_len, hspw); in decode_timing()
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| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr_regs.h | 22 u32 pwrtmg; /* 0x34 Low Power Timing*/
30 u32 rfshtmg; /* 0x64 Refresh Timing*/
46 u32 dramtmg0; /* 0x100 SDRAM Timing 0*/
47 u32 dramtmg1; /* 0x104 SDRAM Timing 1*/
48 u32 dramtmg2; /* 0x108 SDRAM Timing 2*/
49 u32 dramtmg3; /* 0x10c SDRAM Timing 3*/
50 u32 dramtmg4; /* 0x110 SDRAM Timing 4*/
51 u32 dramtmg5; /* 0x114 SDRAM Timing 5*/
52 u32 dramtmg6; /* 0x118 SDRAM Timing 6*/
53 u32 dramtmg7; /* 0x11c SDRAM Timing 7*/
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| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | sdhci-am654.yaml | 62 description: Output tap delay for SD/MMC legacy timing
68 description: Output tap delay for MMC high speed timing
74 description: Output tap delay for SD high speed timing
80 description: Output tap delay for SD UHS SDR12 timing
86 description: Output tap delay for SD UHS SDR25 timing
92 description: Output tap delay for SD UHS SDR50 timing
98 description: Output tap delay for SD UHS SDR104 timing
104 description: Output tap delay for SD UHS DDR50 timing
110 description: Output tap delay for eMMC DDR52 timing
116 description: Output tap delay for eMMC HS200 timing
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| /openbmc/linux/drivers/ata/ |
| H A D | pata_triflex.c | 62 * triflex_load_timing - timing configuration
76 u32 timing = 0; in triflex_load_timing() local
88 timing = 0x0103;break; in triflex_load_timing()
90 timing = 0x0203;break; in triflex_load_timing()
92 timing = 0x0808;break; in triflex_load_timing()
96 timing = 0x0F0F;break; in triflex_load_timing()
98 timing = 0x0202;break; in triflex_load_timing()
100 timing = 0x0204;break; in triflex_load_timing()
102 timing = 0x0404;break; in triflex_load_timing()
104 timing = 0x0508;break; in triflex_load_timing()
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | xenon_sdhci.c | 123 u8 timing; member
141 if ((priv->timing == MMC_TIMING_UHS_SDR50) || in xenon_mmc_phy_init()
142 (priv->timing == MMC_TIMING_UHS_SDR25) || in xenon_mmc_phy_init()
143 (priv->timing == MMC_TIMING_UHS_SDR12) || in xenon_mmc_phy_init()
144 (priv->timing == MMC_TIMING_SD_HS) || in xenon_mmc_phy_init()
145 (priv->timing == MMC_TIMING_LEGACY)) in xenon_mmc_phy_init()
227 * If timing belongs to high speed, set bit[17] of in xenon_mmc_phy_set()
230 if ((priv->timing == MMC_TIMING_MMC_HS400) || in xenon_mmc_phy_set()
231 (priv->timing == MMC_TIMING_MMC_HS200) || in xenon_mmc_phy_set()
232 (priv->timing == MMC_TIMING_UHS_SDR50) || in xenon_mmc_phy_set()
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