| /openbmc/linux/drivers/clocksource/ |
| H A D | timer-zevio.c | 51 void __iomem *timer1, *timer2; member
67 writel(delta, timer->timer1 + IO_CURRENT_VAL); in zevio_timer_set_event()
69 timer->timer1 + IO_CONTROL); in zevio_timer_set_event()
83 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); in zevio_timer_shutdown()
108 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); in zevio_timer_interrupt()
131 timer->timer1 = timer->base + IO_TIMER1; in zevio_timer_add()
164 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); in zevio_timer_add()
165 writel(0, timer->timer1 + IO_DIVIDER); in zevio_timer_add()
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| H A D | timer-orion.c | 139 /* we are only interested in timer1 irq */ in orion_timer_init()
142 pr_err("%pOFn: unable to parse timer1 irq\n", np); in orion_timer_init()
166 /* setup timer1 as clockevent timer */ in orion_timer_init()
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| H A D | timer-npcm7xx.c | 184 "npcm7xx-timer1", timer_of_rate(&npcm7xx_to), in npcm7xx_clocksource_init()
203 /* Enable the clock for timer1, if it exists */ in npcm7xx_timer_init()
209 pr_warn("%pOF: Failed to get clock for timer1: %pe", np, clk); in npcm7xx_timer_init()
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| H A D | arc_timer.c | 7 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
9 * We've designated TIMER0 for clockevents and TIMER1 for clocksource
193 * 32bit TIMER1 to keep counting monotonically and wraparound
207 .name = "ARC Timer1",
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| H A D | timer-ixp4xx.c | 159 * We use OS timer1 on the CPU for the timer tick and the timestamp
199 tmr->clkevt.name = "ixp4xx timer1"; in ixp4xx_timer_register()
210 IRQF_TIMER, "IXP4XX-TIMER1", tmr); in ixp4xx_timer_register()
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| H A D | timer-fttmr010.c | 386 IRQF_TIMER, "FTTMR010-TIMER1", in fttmr010_common_init()
391 IRQF_TIMER, "FTTMR010-TIMER1", in fttmr010_common_init()
395 pr_err("FTTMR010-TIMER1 no IRQ\n"); in fttmr010_common_init()
399 fttmr010->clkevt.name = "FTTMR010-TIMER1"; in fttmr010_common_init()
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| H A D | timer-owl.c | 131 timer1_irq = of_irq_get_byname(node, "timer1"); in owl_timer_init()
133 pr_err("Can't parse timer1 IRQ\n"); in owl_timer_init()
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| H A D | Kconfig | 180 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
181 where TIMER0 serves as clockevent and TIMER1 serves as clocksource.
289 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
291 TIMER0 serves as clockevent while TIMER1 provides clocksource.
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/ |
| H A D | timer.c | 13 static struct timer_regs *timer1 = (struct timer_regs *)TIMER1_BASE; variable
63 lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000); in __udelay()
64 lpc32xx_timer_count(timer1, 1); in __udelay()
66 while (readl(&timer1->tc) < usec) in __udelay()
69 lpc32xx_timer_count(timer1, 0); in __udelay()
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| /openbmc/linux/sound/isa/gus/ |
| H A D | gus_timer.c | 91 struct snd_timer *timer = gus->gf1.timer1; in snd_gf1_interrupt_timer1()
132 gus->gf1.timer1 = NULL; in snd_gf1_timer1_free()
146 if (gus->gf1.timer1 != NULL || gus->gf1.timer2 != NULL) in snd_gf1_timers_init()
164 gus->gf1.timer1 = timer; in snd_gf1_timers_init()
180 if (gus->gf1.timer1) { in snd_gf1_timers_done()
181 snd_device_free(gus->card, gus->gf1.timer1); in snd_gf1_timers_done()
182 gus->gf1.timer1 = NULL; in snd_gf1_timers_done()
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| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | ezchip,nps400-timer1.txt | 5 - compatible : should be "ezchip,nps400-timer1"
7 Clocks required for compatible = "ezchip,nps400-timer1":
13 compatible = "ezchip,nps400-timer1";
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| H A D | snps,arc-timer.txt | 4 - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically
6 TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
24 timer1 {
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| H A D | cirrus,clps711x-timer.txt | 13 timer0 = &timer1;
14 timer1 = &timer2;
17 timer1: timer@80000300 {
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| H A D | actions,owl-timer.txt | 10 "timer0", "timer1", "timer2", "timer3"
20 interrupt-names = "timer0", "timer1";
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| H A D | arm,sp804.yaml | 56 be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1
96 clock-names = "timer1", "timer2", "apb_pclk";
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| /openbmc/linux/arch/arc/boot/dts/ |
| H A D | skeleton.dtsi | 38 /* TIMER1 for free running clocksource */
39 timer1 {
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| H A D | skeleton_hs.dtsi | 39 /* TIMER1 for free running clocksource: Fallback if rtc not found */
40 timer1 {
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| /openbmc/linux/arch/arm64/boot/dts/broadcom/stingray/ |
| H A D | stingray.dtsi | 347 clock-names = "timer1", "timer2", "apb_pclk";
351 timer1: timer@40000 { label
358 clock-names = "timer1", "timer2", "apb_pclk";
368 clock-names = "timer1", "timer2", "apb_pclk";
379 clock-names = "timer1", "timer2", "apb_pclk";
390 clock-names = "timer1", "timer2", "apb_pclk";
401 clock-names = "timer1", "timer2", "apb_pclk";
412 clock-names = "timer1", "timer2", "apb_pclk";
423 clock-names = "timer1", "timer2", "apb_pclk";
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| /openbmc/linux/arch/arm/boot/dts/cirrus/ |
| H A D | ep7209.dtsi | 23 timer0 = &timer1;
24 timer1 = &timer2;
117 timer1: timer@80000300 { label
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| /openbmc/linux/arch/arm64/boot/dts/altera/ |
| H A D | socfpga_stratix10_swvp.dts | 17 timer1 = &timer1;
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| /openbmc/u-boot/arch/arm/mach-omap2/am33xx/ |
| H A D | clock_ti816x.c | 310 /* Enable timer1 */ in peripheral_enable()
312 /* Select timer1 clock to be CLKIN (27MHz) */ in peripheral_enable()
315 /* Wait for timer1 to be ON-ACTIVE */ in peripheral_enable()
319 /* Wait for timer1 to be enabled */ in peripheral_enable()
326 /* Start timer1 */ in peripheral_enable()
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| /openbmc/linux/sound/drivers/opl3/ |
| H A D | opl3_lib.c | 98 /* Set timer1 to 0xff */ in snd_opl3_detect()
252 opl3->timer1 = timer; in snd_opl3_timer1_init()
299 timer = opl3->timer1; in snd_opl3_interrupt()
468 snd_device_free(opl3->card, opl3->timer1); in snd_opl3_timer_new()
469 opl3->timer1 = NULL; in snd_opl3_timer_new()
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| /openbmc/linux/arch/m68k/bvme6000/ |
| H A D | config.c | 185 * So, when reading the elapsed time, you should read timer1,
249 rtc->t1cr_omr |= 0x40; /* Latch timer1 */ in bvme6000_read_clk()
250 msb = rtc->t1msb; /* Read timer1 */ in bvme6000_read_clk()
251 v = (msb << 8) | rtc->t1lsb; /* Read timer1 */ in bvme6000_read_clk()
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| /openbmc/linux/drivers/pci/hotplug/ |
| H A D | cpcihp_zt5550.c | 113 * Disable timer0, timer1 and ENUM interrupts in zt5550_hc_config()
115 dbg("disabling timer0, timer1 and ENUM interrupts"); in zt5550_hc_config()
117 dbg("disabled timer0, timer1 and ENUM interrupts"); in zt5550_hc_config()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | k3-am654-r5-base-board.dts | 24 tick-timer = &timer1;
58 timer1: timer@40400000 { label
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