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/openbmc/linux/drivers/pwm/
H A Dpwm-omap-dmtimer.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Also based on pwm-samsung.c
13 * PWM driver / controller, using the OMAP's dual-mode timers
14 * with a timer counter that goes up. When it overflows it gets
15 * reloaded with the load value and the pwm output goes up.
20 * - When PWM is stopped, timer counter gets stopped immediately. This
21 * doesn't allow the current PWM period to complete and stops abruptly.
22 * - When PWM is running and changing both duty cycle and period,
25 * is updated while the pwm pin is high, current pwm period/duty_cycle
26 * can get updated as below based on the current timer counter:
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menuconfig PWM config
3 bool "Pulse-Width Modulation (PWM) Support"
5 Generic Pulse-Width Modulation (PWM) support.
7 In Pulse-Width Modulation, a variation of the width of pulses
14 This framework provides a generic interface to PWM devices
16 to register and unregister a PWM chip, an abstraction of a PWM
17 controller, that supports one or more PWM devices. Client
18 drivers can request PWM devices and use the generic framework
21 This generic framework replaces the legacy PWM framework which
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H A Dpwm-renesas-tpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Mobile TPU PWM driver
18 #include <linux/pwm.h>
24 #define TPU_TSTR 0x00 /* Timer start register (shared) */
26 #define TPU_TCRn 0x00 /* Timer control register */
35 #define TPU_TMDRn 0x04 /* Timer mode register */
41 #define TPU_TIORn 0x08 /* Timer I/O control register */
50 #define TPU_TIERn 0x0c /* Timer interrupt enable register */
51 #define TPU_TSRn 0x10 /* Timer status register */
52 #define TPU_TCNTn 0x14 /* Timer counter */
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H A Dpwm-dwc.c1 // SPDX-License-Identifier: GPL-2.0
3 * DesignWare PWM Controller driver
5 * Copyright (C) 2018-2020 Intel Corporation
12 * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and low
22 #include <linux/pwm.h>
39 /* Timer Control Register */
62 return readl(dwc->base + offset); in dwc_pwm_readl()
67 writel(value, dwc->base + offset); in dwc_pwm_writel()
70 static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) in __dwc_pwm_set_enable() argument
74 reg = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm)); in __dwc_pwm_set_enable()
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H A Dpwm-stm32-lp.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Low-Power Timer PWM driver
9 * Inspired by Gerald Baeza's pwm-stm32 driver
13 #include <linux/mfd/stm32-lptimer.h>
18 #include <linux/pwm.h>
31 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
34 static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, in stm32_pwm_lp_apply() argument
44 pwm_get_state(pwm, &cstate); in stm32_pwm_lp_apply()
47 if (!state->enabled) { in stm32_pwm_lp_apply()
49 /* Disable LP timer */ in stm32_pwm_lp_apply()
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/openbmc/linux/Documentation/devicetree/bindings/soc/microchip/
H A Datmel,at91rm9200-tcb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel Timer Counter Block
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
14 timer has three channels with two counters each.
19 - enum:
20 - atmel,at91rm9200-tcb
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/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp157c.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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H A Dstm32f429.dtsi2 * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
5 * This file is dual-licensed: you can use it either under the terms
45 #include "armv7-m.dtsi"
46 #include <dt-bindings/clock/stm32fx-clock.h>
47 #include <dt-bindings/mfd/stm32f4-rcc.h>
51 clk_hse: clk-hse {
52 #clock-cells = <0>;
53 compatible = "fixed-clock";
54 clock-frequency = <0>;
57 clk_lse: clk-lse {
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dst,stm32-timers.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This hardware block provides 3 types of timer along with PWM functionality:
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
12 by a programmable prescaler, break input feature, PWM outputs and
13 complementary PWM outputs channels.
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
15 driven by a programmable prescaler and PWM outputs.
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H A Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
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/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-samsung.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC PWM timers
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
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H A Dpwm-omap-dmtimer.txt1 * OMAP PWM for dual-mode timers
4 - compatible: Shall contain "ti,omap-dmtimer-pwm".
5 - ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer-dm.yaml for info
7 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
11 - ti,prescaler: Should be a value between 0 and 7, see the timers datasheet
12 - ti,clock-source: Set dmtimer parent clock, values between 0 and 2:
13 - 0x00 - high-frequency system clock (timer_sys_ck)
14 - 0x01 - 32-kHz always-on clock (timer_32k_ck)
15 - 0x02 - external clock (timer_ext_ck, OMAP2 only)
18 pwm9: dmtimer-pwm@9 {
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H A Dsnps,dw-apb-timers-pwm2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/snps,dw-apb-timers-pwm2.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Synopsys DW-APB timers PWM controller
11 - Ben Dooks <ben.dooks@sifive.com>
14 This describes the DesignWare APB timers module when used in the PWM
24 - $ref: pwm.yaml#
28 const: snps,dw-apb-timers-pwm2
33 "#pwm-cells":
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/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
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H A Dstm32mp131.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp13-clks.h>
8 #include <dt-bindings/reset/stm32mp13-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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H A Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
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H A Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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/openbmc/linux/drivers/media/rc/
H A Dir-rx51.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/pwm.h>
15 #include <media/rc-core.h>
21 struct pwm_device *pwm; member
23 struct hrtimer timer; member
36 ir_rx51->state.enabled = true; in ir_rx51_on()
37 pwm_apply_might_sleep(ir_rx51->pwm, &ir_rx51->state); in ir_rx51_on()
42 ir_rx51->state.enabled = false; in ir_rx51_off()
43 pwm_apply_might_sleep(ir_rx51->pwm, &ir_rx51->state); in ir_rx51_off()
48 ir_rx51->state.period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, ir_rx51->freq); in init_timing_params()
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/openbmc/qemu/hw/timer/
H A Dexynos4210_pwm.c2 * Samsung exynos4210 Pulse Width Modulation Timer
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
27 #include "qemu/timer.h"
39 do { fprintf(stdout, "PWM: [%24s:%5d] " fmt, __func__, __LINE__, \
88 /* timer struct */
90 uint32_t id; /* timer id */
91 qemu_irq irq; /* local timer irq */
92 uint32_t freq; /* timer frequency */
94 /* use ptimer.c to represent count down timer */
95 ptimer_state *ptimer; /* timer */
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dingenic,tcu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ingenic,tcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Timer/Counter Unit (TCU)
11 Documentation/arch/mips/ingenic-tcu.rst.
14 - Paul Cercueil <paul@crapouillou.net>
21 - ingenic,jz4740-tcu
22 - ingenic,jz4725b-tcu
23 - ingenic,jz4760-tcu
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H A Drenesas,rz-mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This hardware block consists of eight 16-bit timer channels and one
14 32- bit timer channel. It supports the following specifications:
15 - Pulse input/output: 28 lines max.
16 - Pulse input 3 lines
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H A Dti,timer-dm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
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/openbmc/u-boot/doc/device-tree-bindings/timer/
H A Datcpit100_timer.txt1 Andestech ATCPIT100 timer
2 ------------------------------------------------------------------
6 This timer is a set of compact multi-function timers, which can be
7 used as pulse width modulators (PWM) as well as simple timers.
10 multi-function timer and provide the following usage scenarios:
11 One 32-bit timer
12 Two 16-bit timers
13 Four 8-bit timers
14 One 16-bit PWM
15 One 16-bit timer and one 8-bit PWM
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/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-kizbox.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-kizbox.dts - Device Tree file for Overkiz Kizbox board
5 * Copyright (C) 2012-2014 Boris BREZILLON <b.brezillon@overkiz.com>
6 * 2014-2015 Gaël PORTAY <g.portay@overkiz.com>
8 /dts-v1/;
10 #include <dt-bindings/pwm/pwm.h>
18 stdout-path = &dbgu;
27 clock-frequency = <18432000>;
31 gpio-keys {
32 compatible = "gpio-keys";
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/openbmc/u-boot/arch/arm/cpu/armv7/s5p-common/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/pwm.h>
15 /* Use the old PWM interface for now */
17 #include <pwm.h>
24 /* macro to read the 16 bit timer */
31 * Read the countdown timer.
36 * @return current value of timer
40 struct s5p_timer *const timer = s5p_get_base_timer(); in timer_get_us_down() local
42 return readl(&timer->tcnto4); in timer_get_us_down()
47 /* PWM Timer 4 */ in timer_init()
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