Searched +full:tegra210 +full:- +full:xusb +full:- +full:padctl (Results 1 – 24 of 24) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra XUSB device mode controller (XUDC)14 - Nagarjuna Kristam <nkristam@nvidia.com>15 - JC Kuo <jckuo@nvidia.com>16 - Thierry Reding <treding@nvidia.com>21 - enum:22 - nvidia,tegra210-xudc # For Tegra210[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra210 xHCI controller10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>14 exposed by the Tegra XUSB pad controller.18 const: nvidia,tegra210-xusb22 - description: base and length of the xHCI host registers[all …]
1 Device tree binding for NVIDIA Tegra XUSB pad controller4 NOTE: It turns out that this binding isn't an accurate description of the XUSB7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.10 The Tegra XUSB pad controller manages a set of lanes, each of which can be14 This document defines the device-specific binding for the XUSB pad controller.16 Refer to pinctrl-bindings.txt in this directory for generic information about17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on21 --------------------22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",[all …]
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra210 XUSB pad controller10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or22 super-speed USB. Other lanes are for various types of low-speed, full-speed[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.6 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt13 #include "../xusb-padctl-common.h"17 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>34 "xusb",36 "pcie-x1",37 "pcie-x4",74 TEGRA210_LANE("otg-0", 0x004, 0, 0x3, 0, otg),75 TEGRA210_LANE("otg-1", 0x004, 2, 0x3, 0, otg),[all …]
1 /dts-v1/;3 #include "tegra210.dtsi"6 model = "NVIDIA P2371-2180";7 compatible = "nvidia,p2371-2180", "nvidia,tegra210";10 stdout-path = &uarta;24 pcie-controller@01003000 {36 padctl@7009f000 {37 pinctrl-0 = <&padctl_default>;38 pinctrl-names = "default";41 xusb {[all …]
1 #include <dt-bindings/clock/tegra210-car.h>2 #include <dt-bindings/gpio/tegra-gpio.h>3 #include <dt-bindings/memory/tegra210-mc.h>4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>5 #include <dt-bindings/interrupt-controller/arm-gic.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>9 compatible = "nvidia,tegra210";10 interrupt-parent = <&lic>;11 #address-cells = <2>;12 #size-cells = <2>;[all …]
1 # SPDX-License-Identifier: GPL-2.0+3 # (C) Copyright 2010-2015 Nvidia Corporation.5 # (C) Copyright 2000-200810 obj-y += spl.o11 obj-y += cpu.o13 obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o16 obj-y += ap.o17 obj-y += board.o board2.o18 obj-y += cache.o19 obj-y += clock.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.13 #include <linux/phy/tegra/xusb.h>22 #include "xusb.h"31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.11 #include <linux/dma-mapping.h>20 #include <linux/phy/tegra/xusb.h>275 struct tegra_xusb_padctl *padctl; member321 return readl(tegra->fpci_base + offset); in fpci_readl()327 writel(value, tegra->fpci_base + offset); in fpci_writel()332 return readl(tegra->ipfs_base + offset); in ipfs_readl()338 writel(value, tegra->ipfs_base + offset); in ipfs_writel()343 return readl(tegra->bar2_base + offset); in bar2_readl()[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra210-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra210-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>7 #include <dt-bindings/reset/tegra210-car.h>8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/thermal/tegra124-soctherm.h>10 #include <dt-bindings/soc/tegra-pmc.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra186-clock.h>3 #include <dt-bindings/gpio/tegra186-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/memory/tegra186-mc.h>7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>8 #include <dt-bindings/power/tegra186-powergate.h>9 #include <dt-bindings/reset/tegra186-reset.h>10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra194-clock.h>3 #include <dt-bindings/gpio/tegra194-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>8 #include <dt-bindings/power/tegra194-powergate.h>9 #include <dt-bindings/reset/tegra194-reset.h>10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/input/gpio-keys.h>5 #include <dt-bindings/input/linux-event-codes.h>6 #include <dt-bindings/mfd/max77620.h>8 #include "tegra210.dtsi"12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";22 stdout-path = "serial0:115200n8";33 hvddio-pex-supply = <&vdd_1v8>;34 dvddio-pex-supply = <&vdd_pex_1v05>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 #include <dt-bindings/clock/tegra234-clock.h>4 #include <dt-bindings/gpio/tegra234-gpio.h>5 #include <dt-bindings/interrupt-controller/arm-gic.h>6 #include <dt-bindings/mailbox/tegra186-hsp.h>7 #include <dt-bindings/memory/tegra234-mc.h>8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>9 #include <dt-bindings/power/tegra234-powergate.h>10 #include <dt-bindings/reset/tegra234-reset.h>11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>[all …]
1 // SPDX-License-Identifier: GPL-2.03 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/input/input.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>8 model = "NVIDIA Tegra210 P2597 I/O board";9 compatible = "nvidia,p2597", "nvidia,tegra210";23 avdd-dsi-csi-supply = <&vdd_dsi_csi>;33 avdd-io-hdmi-dp-supply = <&avdd_1v05>;34 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;35 hdmi-supply = <&vdd_hdmi>;[all …]
1 // SPDX-License-Identifier: GPL-2.02 /dts-v1/;4 #include <dt-bindings/input/input.h>5 #include <dt-bindings/mfd/max77620.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>8 #include "tegra210.dtsi"12 compatible = "google,smaug-rev8", "google,smaug-rev7",13 "google,smaug-rev6", "google,smaug-rev5",14 "google,smaug-rev4", "google,smaug-rev3",15 "google,smaug-rev2", "google,smaug-rev1",[all …]
1 // SPDX-License-Identifier: GPL-2.07 * Copyright (c) 2008-2009, NVIDIA Corporation.9 * Copyright (c) 2013-2014, NVIDIA Corporation.12 #define pr_fmt(fmt) "tegra-pcie: " fmt21 #include <power-domain.h>33 #include <asm/arch-tegra/xusb-padctl.h>34 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>41 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be163 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit243 writel(value, pcie->afi.start + offset); in afi_writel()[all …]
1 // SPDX-License-Identifier: GPL-2.0+30 * good reason why driver-model conversion is infeasible. Examples include36 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),37 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),38 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),39 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),40 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),42 COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),43 COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),44 COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * NVIDIA Tegra XUSB device mode controller5 * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.12 #include <linux/dma-mapping.h>20 #include <linux/phy/tegra/xusb.h>246 return (le32_to_cpu(ctx->member) >> (shift)) & (mask); \253 tmp = le32_to_cpu(ctx->member) & ~((mask) << (shift)); \255 ctx->member = cpu_to_le32(tmp); \338 return (le32_to_cpu(trb->member) >> (shift)) & (mask); \345 tmp = le32_to_cpu(trb->member) & ~((mask) << (shift)); \[all …]
... --------------------- ...
5 ---------------------------------------------------21 W: *Web-page* with status/info23 B: URI for where to file *bugs*. A web-page with detailed bug28 patches to the given subsystem. This is either an in-tree file,29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst46 N: [^a-z]tegra all files whose path contains tegra64 ----------------83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)85 L: linux-scsi@vger.kernel.org88 F: drivers/scsi/3w-*[all …]
1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa[all...]
1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'3 2024-12-2[all...]