1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
6 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
13 #include "../xusb-padctl-common.h"
17 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
34 	"xusb",
36 	"pcie-x1",
37 	"pcie-x4",
74 	TEGRA210_LANE("otg-0",     0x004,  0, 0x3, 0, otg),
75 	TEGRA210_LANE("otg-1",     0x004,  2, 0x3, 0, otg),
76 	TEGRA210_LANE("otg-2",     0x004,  4, 0x3, 0, otg),
77 	TEGRA210_LANE("otg-3",     0x004,  6, 0x3, 0, otg),
78 	TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg),
79 	TEGRA210_LANE("hsic-0",    0x004, 14, 0x1, 0, usb),
80 	TEGRA210_LANE("hsic-1",    0x004, 15, 0x1, 0, usb),
81 	TEGRA210_LANE("pcie-0",    0x028, 12, 0x3, 1, pci),
82 	TEGRA210_LANE("pcie-1",    0x028, 14, 0x3, 2, pci),
83 	TEGRA210_LANE("pcie-2",    0x028, 16, 0x3, 3, pci),
84 	TEGRA210_LANE("pcie-3",    0x028, 18, 0x3, 4, pci),
85 	TEGRA210_LANE("pcie-4",    0x028, 20, 0x3, 5, pci),
86 	TEGRA210_LANE("pcie-5",    0x028, 22, 0x3, 6, pci),
87 	TEGRA210_LANE("pcie-6",    0x028, 24, 0x3, 7, pci),
88 	TEGRA210_LANE("sata-0",    0x028, 30, 0x3, 8, pci),
96 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)  in tegra_xusb_padctl_enable()  argument
100 	if (padctl->enable++ > 0)  in tegra_xusb_padctl_enable()
103 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_enable()
105 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_enable()
109 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_enable()
111 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_enable()
115 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_enable()
117 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_enable()
122 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)  in tegra_xusb_padctl_disable()  argument
126 	if (padctl->enable == 0) {  in tegra_xusb_padctl_disable()
131 	if (--padctl->enable > 0)  in tegra_xusb_padctl_disable()
134 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_disable()
136 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_disable()
140 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_disable()
142 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_disable()
146 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_disable()
148 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_disable()
157 	err = tegra_xusb_padctl_enable(phy->padctl);  in phy_prepare()
170 	return tegra_xusb_padctl_disable(phy->padctl);  in phy_unprepare()
217 	struct tegra_xusb_padctl *padctl = phy->padctl;  in pcie_phy_enable()  local
223 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
226 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
228 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);  in pcie_phy_enable()
231 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);  in pcie_phy_enable()
233 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
235 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
237 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
239 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
241 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
243 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
245 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);  in pcie_phy_enable()
250 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);  in pcie_phy_enable()
252 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
256 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
258 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
260 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
262 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
264 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
268 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);  in pcie_phy_enable()
270 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);  in pcie_phy_enable()
272 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
274 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
281 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
287 		return -ETIMEDOUT;  in pcie_phy_enable()
291 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
293 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
300 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
306 		return -ETIMEDOUT;  in pcie_phy_enable()
310 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
312 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
318 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
324 		return -ETIMEDOUT;  in pcie_phy_enable()
328 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
331 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
337 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
343 		return -ETIMEDOUT;  in pcie_phy_enable()
347 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
349 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
355 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
361 		return -ETIMEDOUT;  in pcie_phy_enable()
365 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
367 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
376 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
378 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
380 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
382 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
384 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
386 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
414 		.padctl = &padctl,
436 						"nvidia,tegra210-xusb-padctl");  in tegra_xusb_padctl_init()
447 		count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",  in tegra_xusb_padctl_init()