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/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-host1x.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra host1x controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The host1x top-level node defines a number of children, each
14 representing one of the host1x client modules defined in this binding.
19 - enum:
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/openbmc/linux/Documentation/devicetree/bindings/gpu/host1x/
H A Dnvidia,tegra210-nvenc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 NVENC is the hardware video encoder present on NVIDIA Tegra210
11 and newer chips. It is located on the Host1x bus and typically
12 programmed through Host1x channels.
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
[all …]
H A Dnvidia,tegra210-nvdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 NVDEC is the hardware video decoder present on NVIDIA Tegra210
11 and newer chips. It is located on the Host1x bus and typically
12 programmed through Host1x channels.
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
[all …]
H A Dnvidia,tegra210-nvjpg.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210
11 and newer chips. It is located on the Host1x bus and typically programmed
12 through Host1x channels.
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvjpg@[0-9a-f]*$"
[all …]
H A Dnvidia,tegra234-nvdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 NVDEC is the hardware video decoder present on NVIDIA Tegra210
11 and newer chips. It is located on the Host1x bus and typically
12 programmed through Host1x channels.
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
[all …]
/openbmc/linux/drivers/gpu/host1x/hw/
H A Dhost1x05.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Host1x init for Tegra210 SoCs
11 struct host1x;
13 int host1x05_init(struct host1x *host);
H A Dhost1x05.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Host1x init for Tegra210 SoCs
23 int host1x05_init(struct host1x *host) in host1x05_init()
25 host->channel_op = &host1x_channel_ops; in host1x05_init()
26 host->cdma_op = &host1x_cdma_ops; in host1x05_init()
27 host->cdma_pb_op = &host1x_pushbuffer_ops; in host1x05_init()
28 host->syncpt_op = &host1x_syncpt_ops; in host1x05_init()
29 host->intr_op = &host1x_intr_ops; in host1x05_init()
30 host->debug_op = &host1x_debug_ops; in host1x05_init()
H A Dhost1x05_hardware.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Tegra host1x Register Offsets for Tegra210
/openbmc/linux/Documentation/gpu/
H A Dtegra.rst6 the host1x controller. host1x supplies command streams, gathered from a push
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
25 GPU and video engines via host1x.
30 The various host1x clients need to be bound together into a logical device in
32 this is implemented in the host1x driver. When a driver is registered with the
37 to the logical host1x device.
40 device using a driver-provided function which will set up the bits specific to
[all …]
/openbmc/linux/drivers/staging/media/tegra-video/
H A Dvi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/host1x.h>
16 #include <media/media-entity.h>
17 #include <media/v4l2-async.h>
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-dev.h>
21 #include <media/v4l2-subdev.h>
22 #include <media/videobuf2-v4l2.h>
44 * struct tegra_vi_ops - Tegra VI operations
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H A Dvideo.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/host1x.h>
10 #include <media/v4l2-event.h>
21 tegra_channels_cleanup(vid->vi); in tegra_v4l2_dev_release()
24 media_device_unregister(&vid->media_dev); in tegra_v4l2_dev_release()
25 media_device_cleanup(&vid->media_dev); in tegra_v4l2_dev_release()
39 v4l2_event_queue(&chan->video, arg); in tegra_v4l2_dev_notify()
40 if (ev->type == V4L2_EVENT_SOURCE_CHANGE && vb2_is_streaming(&chan->queue)) in tegra_v4l2_dev_notify()
41 vb2_queue_error(&chan->queue); in tegra_v4l2_dev_notify()
51 return -ENOMEM; in host1x_video_probe()
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H A Dtegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * This source file contains Tegra210 supported video formats,
14 #include <linux/host1x.h>
29 /* Tegra210 VI registers */
40 /* Tegra210 VI CSI registers */
64 /* Tegra210 CSI Pixel Parser registers: Starts from 0x838, offset 0x0 */
92 /* Tegra210 CSI PHY registers */
146 /* Tegra210 VI registers accessors */
150 writel_relaxed(val, chan->vi->iomem + addr); in tegra_vi_write()
155 return readl_relaxed(chan->vi->iomem + addr); in tegra_vi_read()
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H A Dcsi.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/host1x.h>
16 #include <media/v4l2-fwnode.h>
70 return -ENOIOCTLCMD; in csi_enum_bus_code()
72 if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts)) in csi_enum_bus_code()
73 return -EINVAL; in csi_enum_bus_code()
75 code->code = tegra_csi_tpg_fmts[code->index].code; in csi_enum_bus_code()
87 return -ENOIOCTLCMD; in csi_get_format()
89 fmt->format = csi_chan->format; in csi_get_format()
100 frmrate = csi->soc->tpg_frmrate_table; in csi_get_frmrate_table_index()
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/openbmc/u-boot/arch/arm/dts/
H A Dtegra210.dtsi1 #include <dt-bindings/clock/tegra210-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra210-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
9 compatible = "nvidia,tegra210";
10 interrupt-parent = <&lic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
[all …]
/openbmc/linux/drivers/gpu/drm/tegra/
H A Ddrm.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/host1x.h>
27 #include <asm/dma-iommu.h>
76 struct drm_device *drm = old_state->dev; in tegra_atomic_commit_tail()
77 struct tegra_drm *tegra = drm->dev_private; in tegra_atomic_commit_tail()
79 if (tegra->hub) { in tegra_atomic_commit_tail()
108 return -ENOMEM; in tegra_drm_open()
110 idr_init_base(&fpriv->legacy_contexts, 1); in tegra_drm_open()
111 xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1); in tegra_drm_open()
[all …]
H A Dnvdec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2022, NVIDIA Corporation.
8 #include <linux/dma-mapping.h>
9 #include <linux/host1x.h>
50 /* RISC-V specific data */
63 writel(value, nvdec->regs + offset); in nvdec_writel()
71 if (nvdec->config->supports_sid && tegra_dev_iommu_get_stream_id(nvdec->dev, &stream_id)) { in nvdec_boot_falcon()
81 err = falcon_boot(&nvdec->falcon); in nvdec_boot_falcon()
85 err = falcon_wait_idle(&nvdec->falcon); in nvdec_boot_falcon()
87 dev_err(nvdec->dev, "falcon boot timed out\n"); in nvdec_boot_falcon()
[all …]
H A Dvic.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
9 #include <linux/host1x.h>
52 writel(value, vic->regs + offset); in vic_writel()
61 if (vic->config->supports_sid && tegra_dev_iommu_get_stream_id(vic->dev, &stream_id)) { in vic_boot()
88 err = falcon_boot(&vic->falcon); in vic_boot()
92 hdr = vic->falcon.firmware.virt; in vic_boot()
97 hdr = vic->falcon.firmware.virt + in vic_boot()
101 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE, in vic_boot()
104 &vic->falcon, VIC_SET_FCE_UCODE_OFFSET, in vic_boot()
[all …]
/openbmc/linux/drivers/gpu/host1x/
H A Ddev.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Tegra host1x driver
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
10 #include <linux/dma-mapping.h>
23 #include <trace/events/host1x.h>
27 #include <asm/dma-iommu.h>
45 void host1x_common_writel(struct host1x *host1x, u32 v, u32 r) in host1x_common_writel() argument
47 writel(v, host1x->common_regs + r); in host1x_common_writel()
50 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r) in host1x_hypervisor_writel() argument
52 writel(v, host1x->hv_regs + r); in host1x_hypervisor_writel()
[all …]
H A Dmipi.c24 #include <linux/host1x.h>
139 return readl(mipi->regs + (offset << 2)); in tegra_mipi_readl()
145 writel(value, mipi->regs + (offset << 2)); in tegra_mipi_writel()
153 err = clk_enable(mipi->clk); in tegra_mipi_power_up()
160 if (mipi->soc->needs_vclamp_ref) in tegra_mipi_power_up()
169 clk_disable(mipi->clk); in tegra_mipi_power_up()
179 err = clk_enable(mipi->clk); in tegra_mipi_power_down()
194 * control a regulator that supplies current to the pre-driver logic. in tegra_mipi_power_down()
200 if (mipi->soc->needs_vclamp_ref) in tegra_mipi_power_down()
216 err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate", in tegra_mipi_request()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
[all …]
H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
[all …]
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]
H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]
H A Dtegra210-p2371-2180.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra210-p2180.dtsi"
5 #include "tegra210-p2597.dtsi"
9 compatible = "nvidia,p2371-2180", "nvidia,tegra210";
14 hvddio-pex-supply = <&vdd_1v8>;
15 dvddio-pex-supply = <&vdd_pex_1v05>;
16 vddio-pex-ctl-supply = <&vdd_1v8>;
19 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
20 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
[all …]

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