19952f691SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2a134789aSThierry Reding /*
3a134789aSThierry Reding  * Tegra host1x Register Offsets for Tegra210
4a134789aSThierry Reding  *
5a134789aSThierry Reding  * Copyright (c) 2015 NVIDIA Corporation.
6a134789aSThierry Reding  */
7a134789aSThierry Reding 
8a134789aSThierry Reding #ifndef __HOST1X_HOST1X05_HARDWARE_H
9a134789aSThierry Reding #define __HOST1X_HOST1X05_HARDWARE_H
10a134789aSThierry Reding 
11a134789aSThierry Reding #include <linux/types.h>
12a134789aSThierry Reding #include <linux/bitops.h>
13a134789aSThierry Reding 
14a134789aSThierry Reding #include "hw_host1x05_channel.h"
15a134789aSThierry Reding #include "hw_host1x05_sync.h"
16a134789aSThierry Reding #include "hw_host1x05_uclass.h"
17a134789aSThierry Reding 
18*3000c4acSMikko Perttunen #include "opcodes.h"
19a134789aSThierry Reding 
20a134789aSThierry Reding #endif
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