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Searched full:tclk (Results 1 – 25 of 104) sorted by relevance

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/openbmc/linux/drivers/clk/sunxi/
H A Dclk-sun4i-tcon-ch1.c36 struct tcon_ch1_clk *tclk = hw_to_tclk(hw); in tcon_ch1_disable() local
40 spin_lock_irqsave(&tclk->lock, flags); in tcon_ch1_disable()
41 reg = readl(tclk->reg); in tcon_ch1_disable()
43 writel(reg, tclk->reg); in tcon_ch1_disable()
44 spin_unlock_irqrestore(&tclk->lock, flags); in tcon_ch1_disable()
49 struct tcon_ch1_clk *tclk = hw_to_tclk(hw); in tcon_ch1_enable() local
53 spin_lock_irqsave(&tclk->lock, flags); in tcon_ch1_enable()
54 reg = readl(tclk->reg); in tcon_ch1_enable()
56 writel(reg, tclk->reg); in tcon_ch1_enable()
57 spin_unlock_irqrestore(&tclk->lock, flags); in tcon_ch1_enable()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmvebu-core-clock.txt8 0 = tclk (Internal Bus clock)
15 0 = tclk (Internal Bus clock)
21 0 = tclk (Internal Bus clock)
27 0 = tclk (Internal Bus clock)
35 0 = tclk (Internal Bus clock)
41 0 = tclk (Internal Bus clock)
47 0 = tclk (Internal Bus clock)
72 output names ("tclk", "cpuclk", "l2clk", "ddrclk")
85 /* get tclk from core clock provider */
H A Dqcom,sdx75-gcc.yaml28 - description: EMAC0 sgmiiphy mac tclk source
30 - description: EMAC0 sgmiiphy tclk source
32 - description: EMAC1 sgmiiphy mac tclk source
34 - description: EMAC1 sgmiiphy tclk source
H A Dmvebu-gated-clock.txt189 - clocks : default parent clock phandle (e.g. tclk)
196 /* default parent clock is tclk */
/openbmc/linux/arch/arm/mach-dove/
H A Dcommon.c71 static struct clk *tclk; variable
87 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk); in dove_clk_init()
89 usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); in dove_clk_init()
90 usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); in dove_clk_init()
91 sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA); in dove_clk_init()
92 pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0); in dove_clk_init()
93 pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1); in dove_clk_init()
94 sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0); in dove_clk_init()
95 sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1); in dove_clk_init()
96 nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND); in dove_clk_init()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_topology.c16 unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk) in mv_ddr_cl_calc() argument
18 unsigned int cl = ceil_div(taa_min, tclk); in mv_ddr_cl_calc()
24 unsigned int mv_ddr_cwl_calc(unsigned int tclk) in mv_ddr_cwl_calc() argument
28 if (tclk >= 1250) in mv_ddr_cwl_calc()
30 else if (tclk >= 1071) in mv_ddr_cwl_calc()
32 else if (tclk >= 938) in mv_ddr_cwl_calc()
34 else if (tclk >= 833) in mv_ddr_cwl_calc()
36 else if (tclk >= 750) in mv_ddr_cwl_calc()
38 else if (tclk >= 625) in mv_ddr_cwl_calc()
53 unsigned int tclk; in mv_ddr_topology_map_update() local
[all …]
H A Dmv_ddr_common.c25 unsigned int time_to_nclk(unsigned int t, unsigned int tclk) in time_to_nclk() argument
27 /* t & tclk parameters are in ps */ in time_to_nclk()
28 return ((unsigned long)t * 1000 / tclk + 974) / 1000; in time_to_nclk()
/openbmc/linux/arch/arm/plat-orion/
H A Dtime.c62 * at least 7.5ns (133MHz TCLK).
197 unsigned int irq, unsigned int tclk) in orion_time_init() argument
207 ticks_per_jiffy = (tclk + HZ/2) / HZ; in orion_time_init()
209 orion_delay_timer.freq = tclk; in orion_time_init()
215 sched_clock_register(orion_read_sched_clock, 32, tclk); in orion_time_init()
228 tclk, 300, 32, clocksource_mmio_readl_down); in orion_time_init()
237 clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe); in orion_time_init()
H A Dcommon.c36 clkdev entries to the tclk. */
37 void __init orion_clkdev_init(struct clk *tclk) in orion_clkdev_init() argument
39 orion_clkdev_add(NULL, "orion_spi.0", tclk); in orion_clkdev_init()
40 orion_clkdev_add(NULL, "orion_spi.1", tclk); in orion_clkdev_init()
41 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", tclk); in orion_clkdev_init()
42 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", tclk); in orion_clkdev_init()
43 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".2", tclk); in orion_clkdev_init()
44 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".3", tclk); in orion_clkdev_init()
45 orion_clkdev_add(NULL, "orion_wdt", tclk); in orion_clkdev_init()
46 orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", tclk); in orion_clkdev_init()
/openbmc/linux/drivers/power/reset/
H A Dqnap-poweroff.c50 static unsigned long tclk; variable
55 const unsigned divisor = ((tclk + (8 * cfg->baud)) / (16 * cfg->baud)); in qnap_power_off()
94 /* We need to know tclk in order to calculate the UART divisor */ in qnap_power_off_probe()
101 tclk = clk_get_rate(clk); in qnap_power_off_probe()
/openbmc/linux/drivers/clk/
H A Dclk-vt8500.c353 unsigned long tclk; in vt8500_find_pll_bits() local
369 tclk = (parent_rate / *prediv) * *multiplier; in vt8500_find_pll_bits()
371 if (tclk != rate) in vt8500_find_pll_bits()
373 rate, tclk); in vt8500_find_pll_bits()
457 unsigned long tclk, rate_err, best_err; in wm8750_find_pll_bits() local
465 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); in wm8750_find_pll_bits()
466 if (tclk > rate) in wm8750_find_pll_bits()
469 rate_err = rate - tclk; in wm8750_find_pll_bits()
505 unsigned long tclk, rate_err, best_err; in wm8850_find_pll_bits() local
513 tclk = parent_rate * ((mul + 1) * 2) / in wm8850_find_pll_bits()
[all …]
/openbmc/linux/arch/arm/mach-mv78xx0/
H A Dcommon.c108 * TCLK tick rate is configured by DEV_A[2:0] strap pins. in get_tclk()
118 panic("unknown TCLK PLL setting: %.8x\n", in get_tclk()
165 static struct clk *tclk; variable
169 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, get_tclk()); in clk_init()
171 orion_clkdev_init(tclk); in clk_init()
291 IRQ_MV78XX0_UART_0, tclk); in mv78xx0_uart0_init()
301 IRQ_MV78XX0_UART_1, tclk); in mv78xx0_uart1_init()
311 IRQ_MV78XX0_UART_2, tclk); in mv78xx0_uart2_init()
320 IRQ_MV78XX0_UART_3, tclk); in mv78xx0_uart3_init()
421 printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); in mv78xx0_init()
/openbmc/linux/arch/arm/mach-orion5x/
H A Dcommon.c62 static struct clk *tclk; variable
66 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, orion5x_tclk); in clk_init()
68 orion_clkdev_init(tclk); in clk_init()
136 IRQ_ORION5X_UART0, tclk); in orion5x_uart0_init()
145 IRQ_ORION5X_UART1, tclk); in orion5x_uart1_init()
319 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); in orion5x_init()
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml52 - const: tclk
99 clock-names = "tclk";
/openbmc/linux/Documentation/devicetree/bindings/ptp/
H A Dptp-qoriq.txt16 - fsl,tclk-period Timer reference clock period in nanoseconds.
81 fsl,tclk-period = <10>;
/openbmc/linux/drivers/i2c/busses/
H A Di2c-mv64xxx.c826 const int tclk, const int n, const int m) in mv64xxx_calc_freq() argument
829 return tclk / (10 * (m + 1) * (1 << n)); in mv64xxx_calc_freq()
831 return tclk / (10 * (m + 1) * (2 << n)); in mv64xxx_calc_freq()
836 const u32 req_freq, const u32 tclk) in mv64xxx_find_baud_factors() argument
843 freq = mv64xxx_calc_freq(drv_data, tclk, n, m); in mv64xxx_find_baud_factors()
864 u32 bus_freq, tclk; in mv64xxx_of_config() local
868 * need to know tclk in order to calculate bus clock in mv64xxx_of_config()
875 tclk = clk_get_rate(drv_data->clk); in mv64xxx_of_config()
884 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) { in mv64xxx_of_config()
/openbmc/linux/drivers/clk/mvebu/
H A Dcommon.c110 const char *tclk_name = "tclk"; in mvebu_coreclk_setup()
120 /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ in mvebu_coreclk_setup()
134 /* Register TCLK */ in mvebu_coreclk_setup()
/openbmc/linux/arch/arm/plat-orion/include/plat/
H A Dtime.h17 unsigned int irq, unsigned int tclk);
/openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dkw88f6192.h17 /* TCLK Core Clock defination */
H A Dkw88f6281.h17 /* TCLK Core Clock definition */
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dmarvell,orion-timer.txt7 - clocks: phandle of timer reference clock (tclk)
/openbmc/linux/Documentation/devicetree/bindings/power/reset/
H A Dqnap-poweroff.txt15 - clocks: tclk clock
/openbmc/u-boot/arch/arm/mach-orion5x/include/mach/
H A Dmv88f5182.h20 /* TCLK Core Clock defination */
/openbmc/u-boot/board/Synology/ds109/
H A Dds109.h34 u32 tclk; member
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-370-pinctrl.txt52 mpp31 31 gpio, tclk, ge0(txerr)
94 mpp63 63 gpio, spi0(sck), tclk

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