16 unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk)  in mv_ddr_cl_calc()  argument
18 	unsigned int cl = ceil_div(taa_min, tclk);  in mv_ddr_cl_calc()
24 unsigned int mv_ddr_cwl_calc(unsigned int tclk)  in mv_ddr_cwl_calc()  argument
28 	if (tclk >= 1250)  in mv_ddr_cwl_calc()
30 	else if (tclk >= 1071)  in mv_ddr_cwl_calc()
32 	else if (tclk >= 938)  in mv_ddr_cwl_calc()
34 	else if (tclk >= 833)  in mv_ddr_cwl_calc()
36 	else if (tclk >= 750)  in mv_ddr_cwl_calc()
38 	else if (tclk >= 625)  in mv_ddr_cwl_calc()
53 	unsigned int tclk;  in mv_ddr_topology_map_update()  local
108 		tclk = 1000000 / mv_ddr_freq_get(iface_params->memory_freq);  in mv_ddr_topology_map_update()
110 		val = mv_ddr_cwl_calc(tclk);  in mv_ddr_topology_map_update()
119 		val = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk);  in mv_ddr_topology_map_update()