Home
last modified time | relevance | path

Searched +full:trtp +full:- +full:min +full:- +full:tck (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/memory/
H A Dof_memory.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 * of_get_min_tck() - extract min timing values for ddr
21 * @dev: device requesting for min timing values
26 * default min timings provided by JEDEC.
32 struct lpddr2_min_tck *min; in of_get_min_tck() local
34 min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL); in of_get_min_tck()
35 if (!min) in of_get_min_tck()
38 ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); in of_get_min_tck()
39 ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); in of_get_min_tck()
40 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_get_min_tck()
[all …]
H A Djedec_ddr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
64 /* Refresh rate in nano-seconds */
157 u32 tRTP; member
169 * Min value for some parameters in terms of number of tCK cycles(nCK)
181 u32 tRTP; member
207 * -ENOENT if info unavailable.
237 u32 tRTP; member
252 * Min value for some parameters in terms of number of tCK cycles(nCK)
266 u32 tRTP; member
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Delpida_ecb240abacn.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4";
10 io-width = <32>;
12 tRPab-min-tck = <3>;
13 tRCD-min-tck = <3>;
14 tWR-min-tck = <3>;
15 tRASmin-min-tck = <3>;
16 tRRD-min-tck = <2>;
17 tWTR-min-tck = <2>;
18 tXP-min-tck = <2>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
[all …]
H A Djedec,lpddr3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Demif.c1 // SPDX-License-Identifier: GPL-2.0+
17 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
23 /* Base AC Timing values specified by JESD209-2 for 532MHz operation */
48 * Min tCK values specified by JESD209-2
49 * Min tCK specifies the minimum duration of some AC timing parameters in terms
51 * absolute time value is less than the min tCK value, min tCK value should
63 .tRTP = 2,
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Demif.c1 // SPDX-License-Identifier: GPL-2.0+
22 /* Base AC Timing values specified by JESD209-2 for 400MHz operation */
46 /* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
71 * Min tCK values specified by JESD209-2
72 * Min tCK specifies the minimum duration of some AC timing parameters in terms
74 * absolute time value is less than the min tCK value, min tCK value should
86 .tRTP = 2,
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
27 stdout-path = "serial2:115200n8";
31 compatible = "samsung,secure-firmware";
35 fixed-rate-clocks {
[all …]
/openbmc/u-boot/drivers/ddr/fsl/
H A Dlc_common_dimm_params.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
39 if (mclk_ps < outpdimm->tckmin_x_ps) { in compute_cas_latency()
42 mclk_ps, outpdimm->tckmin_x_ps); in compute_cas_latency()
45 if (mclk_ps > outpdimm->tckmax_ps) { in compute_cas_latency()
47 mclk_ps, outpdimm->tckmax_ps); in compute_cas_latency()
51 caslat_actual = (outpdimm->taamin_ps + mclk_ps - 1) / mclk_ps; in compute_cas_latency()
55 retry--; in compute_cas_latency()
66 outpdimm->lowest_common_spd_caslat = caslat_actual; in compute_cas_latency()
[all …]
H A Dctrl_regs.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
29 * Rtt(nominal) - DDR2:
34 * Rtt(nominal) - DDR3:
49 * if (popts->dimmslot[i].num_valid_cs
50 * && (popts->cs_local_opts[2*i].odt_rd_cfg
51 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
108 * CWL = 5 if tCK >= 2.5ns
109 * 6 if 2.5ns > tCK >= 1.875ns
[all …]
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2015
10 * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
26 * Allwinner as part of the open-source bootloader release (refer to
27 * https://github.com/allwinner-zh/bootloader.git) and augments the upstream
36 * Note that the Zynq-documentation provides a very close match for the DDR
42 * (i.e. the rules for MEMC_FREQ_RATIO=2 from the Zynq-documentation apply).
48 * 1) Only DDR3 support is implemented, as our test platform (the A80-Q7
50 * 2) Only 2T-mode has been implemented and tested.
62 * The driver should be driven from a device-tree based configuration that
[all …]
/openbmc/u-boot/arch/arm/include/asm/
H A Demif.h4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
815 * calculations. So, as a trade-off keep denominator(and consequently
816 * numerator) within a limit sacrificing some accuracy - but not much
885 /* Interleaving policies at EMIF level- between banks and Chip Selects */
909 /* To be used when voltage is changed for DPS/DVFS - 1us */
913 * 50us - or maximum value will do
921 * due to smart-reflex.
934 /* Enable ZQ Calibration on exiting Self-refresh */
937 * ZQ Calibration simultaneously on both chip-selects:
1005 * nWR : 3(default). EMIF does not do pre-charge.
[all …]
/openbmc/u-boot/drivers/ram/rockchip/
H A Ddmc-rk3368.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/memory/rk3368-dmc.h>
10 #include <dt-structs.h>
123 ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
125 ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
133 (((n - 5) & 0x7) << 3)
141 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
143 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
149 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
151 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
[all …]