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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Delpida_ecb240abacn.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4";
10 io-width = <32>;
12 tRPab-min-tck = <3>;
13 tRCD-min-tck = <3>;
14 tWR-min-tck = <3>;
15 tRASmin-min-tck = <3>;
16 tRRD-min-tck = <2>;
17 tWTR-min-tck = <2>;
18 tXP-min-tck = <2>;
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr2-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
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H A Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
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H A Djedec,lpddr3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
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H A Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
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/openbmc/linux/drivers/memory/
H A Dof_memory.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 * of_get_min_tck() - extract min timing values for ddr
21 * @dev: device requesting for min timing values
26 * default min timings provided by JEDEC.
32 struct lpddr2_min_tck *min; in of_get_min_tck() local
34 min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL); in of_get_min_tck()
35 if (!min) in of_get_min_tck()
38 ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab); in of_get_min_tck()
39 ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD); in of_get_min_tck()
40 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_get_min_tck()
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H A Djedec_ddr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
64 /* Refresh rate in nano-seconds */
169 * Min value for some parameters in terms of number of tCK cycles(nCK)
207 * -ENOENT if info unavailable.
234 u32 tRAS; member
252 * Min value for some parameters in terms of number of tCK cycles(nCK)
263 u32 tRAS; member
/openbmc/u-boot/include/
H A Dddr_spd.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
10 * Format from "JEDEC Standard No. 21-C,
37 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
39 Clk @ CL=X-0.5 (tAC) */
40 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */
41 unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
42 unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/
43 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */
44 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */
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H A Dspd.h1 /* SPDX-License-Identifier: GPL-2.0+ */
38 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time at CL=X-1 */
39 unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */
40 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time at CL=X-2 */
41 unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */
42 unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/
43 unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */
44 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */
45 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ member
56 unsigned char trc; /* 41 Min Active to Auto refresh time tRC */
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/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dmx6-ddr.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 #include "mx6q-ddr.h"
13 #include "mx6dl-ddr.h"
16 #include "mx6sx-ddr.h"
19 #include "mx6ul-ddr.h"
22 #include "mx6sl-ddr.h"
249 * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
366 u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
370 u8 rowaddr; /* row address bits (11-16)*/
371 u8 coladdr; /* col address bits (9-12) */
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/openbmc/u-boot/drivers/ddr/fsl/
H A Dinteractive.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2010-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
140 pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]); in fsl_ddr_spd_edit()
145 sizeof((common_timing_params_t *)0)->x, 0}
152 common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num]; in lowest_common_dimm_parameters_edit()
210 sizeof((dimm_params_t *)0)->x, 0}
212 sizeof((dimm_params_t *)0)->x, 1}
220 dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]); in fsl_ddr_dimm_parameters_edit()
410 if (pdimm->n_ranks == 0) { in print_dimm_parameters()
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H A Dctrl_regs.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
29 * Rtt(nominal) - DDR2:
34 * Rtt(nominal) - DDR3:
49 * if (popts->dimmslot[i].num_valid_cs
50 * && (popts->cs_local_opts[2*i].odt_rd_cfg
51 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
155 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ in set_csn_config()
174 if (!popts->memctl_interleaving) in set_csn_config()
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/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
27 stdout-path = "serial2:115200n8";
31 compatible = "samsung,secure-firmware";
35 fixed-rate-clocks {
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/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2015
10 * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
26 * Allwinner as part of the open-source bootloader release (refer to
27 * https://github.com/allwinner-zh/bootloader.git) and augments the upstream
36 * Note that the Zynq-documentation provides a very close match for the DDR
42 * (i.e. the rules for MEMC_FREQ_RATIO=2 from the Zynq-documentation apply).
48 * 1) Only DDR3 support is implemented, as our test platform (the A80-Q7
50 * 2) Only 2T-mode has been implemented and tested.
62 * The driver should be driven from a device-tree based configuration that
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_spd.c1 // SPDX-License-Identifier: GPL-2.0
196 * Name: ddr3_get_dimm_num - Find number of dimms and their addresses
198 * Args: dimm_addr - array of dimm addresses
211 dimm_cur_addr--) { in ddr3_get_dimm_num()
214 /* Far-End DIMM must be connected */ in ddr3_get_dimm_num()
232 * Name: dimmSpdInit - Get the SPD parameters.
234 * Args: dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator.
235 * info - DIMM information structure.
261 info->err_check_type = 0; in ddr3_spd_init()
265 info->err_check_type = 1; in ddr3_spd_init()
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_bw.c1 // SPDX-License-Identifier: MIT
47 val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC); in dg1_mchbar_read_qgv_point_info()
53 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000); in dg1_mchbar_read_qgv_point_info()
55 val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); in dg1_mchbar_read_qgv_point_info()
57 sp->dclk *= 2; in dg1_mchbar_read_qgv_point_info()
59 if (sp->dclk == 0) in dg1_mchbar_read_qgv_point_info()
60 return -EINVAL; in dg1_mchbar_read_qgv_point_info()
62 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR); in dg1_mchbar_read_qgv_point_info()
63 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); in dg1_mchbar_read_qgv_point_info()
64 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val); in dg1_mchbar_read_qgv_point_info()
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/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dplatform.S9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * EC1. Modify DQIDLY and DQSI-MCLK2X calibration algorithm
28 * EC6. Remove AST2300-A0 PCI-e workaround
31 * EC9. Add DRAM size auto-detection
36 * EC1. Add solution of LPC lock issue due to watchdog reset. (AP note A2300-11)
63 * EC1. Default assign X-DMA engine to VGA memory domain, MCR08[16] = 1.
67 * CONFIG_DRAM_336 // 336MHz (DDR-667)
68 * CONFIG_DRAM_408 // 408MHz (DDR-800) (default)
141 cmp r2, r3 @ record min
155 cmp r2, r3 @ record min
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/openbmc/u-boot/drivers/ram/rockchip/
H A Ddmc-rk3368.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/memory/rk3368-dmc.h>
10 #include <dt-structs.h>
123 ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
125 ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
133 (((n - 5) & 0x7) << 3)
141 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
143 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
149 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
151 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
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/openbmc/linux/sound/pci/asihpi/
H A Dhpi6205.c1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 1997-2014 AudioScience Inc. <support@audioscience.com>
17 (C) Copyright AudioScience Inc. 1998-2010
61 /* Host-to-DSP Control Register (HDCR) bitfields */
70 * BAR1 maps to non-prefetchable 8 Mbyte memory block
114 /* a non-NULL handle means there is an HPI allocated buffer */
117 /* non-zero size means a buffer exists, may be external */
224 switch (phm->function) { in subsys_message()
229 phr->error = HPI_ERROR_INVALID_FUNC; in subsys_message()
238 struct hpi_hw_obj *phw = pao->priv; in control_message()
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/openbmc/linux/Documentation/translations/sp_SP/process/
H A Dcoding-style.rst1 .. include:: ../disclaimer-sp.rst
3 :Original: :ref:`Documentation/process/coding-style.rst <submittingpatches>`
24 -----------
49 sangría`` (``double-indenting``) en etiquetas ``case``. Por ejemplo:
51 .. code-block:: c
73 .. code-block:: c
80 .. code-block:: c
87 .. code-block:: c
106 ------------------------------------
129 ----------------------------------
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/openbmc/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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/openbmc/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
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