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/openbmc/u-boot/board/work-microwave/work_92105/
H A Dwork_92105_spl.c31 .tmrd = 1,
51 .tmrd = 1,
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr3.yaml68 tMRD-min-tck:
202 tMRD-min-tck = <5>;
227 tMRD = <7000>;
H A Djedec,lpddr3-timings.yaml49 tMRD:
141 tMRD = <7000>;
/openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/
H A Dddr2_v3s.c25 u8 tmrd = 2; in mctl_set_timing_params() local
62 writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), in mctl_set_timing_params()
H A Dlpddr3_stock.c25 u8 tmrd = 5; in mctl_set_timing_params() local
61 writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), in mctl_set_timing_params()
H A Dddr3_1333.c25 u8 tmrd = 4; in mctl_set_timing_params() local
65 writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), in mctl_set_timing_params()
/openbmc/linux/drivers/memory/
H A Dof_memory.c195 ret |= of_property_read_u32(np, "tMRD-min-tck", &min->tMRD); in of_lpddr3_get_min_tck()
238 ret |= of_property_read_u32(np, "tMRD", &tim->tMRD); in of_lpddr3_do_get_timings()
H A Djedec_ddr.h248 u32 tMRD; member
277 u32 tMRD; member
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rk3036.h46 u32 tmrd; member
243 u32 tmrd; member
H A Dsdram.h49 u32 tmrd; member
H A Dddr_rk3368.h50 u32 tmrd; member
H A Dsdram_rk322x.h82 u32 tmrd; member
208 u32 tmrd; member
/openbmc/u-boot/drivers/ram/
H A Dstm32_sdram.c120 u8 tmrd; member
202 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, in stm32_sdram_init()
212 | timing->tmrd << FMC_SDTR_TMRD_SHIFT, in stm32_sdram_init()
/openbmc/u-boot/arch/arm/include/asm/arch-vf610/
H A Dddrmc-vf610.h27 u8 tmrd; member
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32-fmc.txt19 tmrd
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dddr.c1000 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr; in mx6_lpddr2_cfg() local
1055 * tMRD should be set to max(tMRR, tMRW) in mx6_lpddr2_cfg()
1057 tmrd = 5; in mx6_lpddr2_cfg()
1090 debug("tmrd=%d\n", tmrd); in mx6_lpddr2_cfg()
1142 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl; in mx6_lpddr2_cfg()
1231 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; in mx6_ddr3_cfg() local
1333 tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1; in mx6_ddr3_cfg()
1366 debug("tmrd=%d\n", tmrd); in mx6_ddr3_cfg()
1436 (twr << 9) | (tmrd << 5) | tcwl; in mx6_ddr3_cfg()
/openbmc/u-boot/board/timll/devkit3250/
H A Ddevkit3250_spl.c38 .tmrd = 1,
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-lmcx-defs.h1829 uint64_t tmrd:3; member
1841 uint64_t tmrd:3;
1853 uint64_t tmrd:3; member
1865 uint64_t tmrd:3;
2602 uint64_t tmrd:4; member
2612 uint64_t tmrd:4;
2631 uint64_t tmrd:4; member
2641 uint64_t tmrd:4;
2659 uint64_t tmrd:4; member
2669 uint64_t tmrd:4;
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a83t.c109 u8 tmrd = 4; in auto_set_timing_para() local
157 tmrd = 5; in auto_set_timing_para()
176 reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); in auto_set_timing_para()
H A Ddram_sun9i.c124 u32 tMRD; /* in nCK */ member
387 const u32 tMRD = para->tMRD; in mctl_channel_init() local
546 writel((MCTL_DIV2(tMRD) << 12) | (MCTL_DIV2(tMOD) << 0), in mctl_channel_init()
644 writel((tMRD << 0) | ((tMOD - 12) << 2) | (tFAW << 5) | in mctl_channel_init()
897 .tMRD = 4, in sunxi_dram_init()
H A Ddram_sun8i_a33.c109 u8 tmrd = 4; in auto_set_timing_para() local
144 reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); in auto_set_timing_para()
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Demc.h92 u32 tmrd; member
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c49 writel(dram->tmrd, &emc->t_mrd); in ddr_init()
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dlpddr2.h40 … 0x00180E63 /* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */
/openbmc/u-boot/board/tbs/tbs2910/
H A Dtbs2910.cfg81 /* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */

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