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/openbmc/linux/drivers/phy/hisilicon/
H A Dphy-histb-combphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
14 #include <linux/mfd/syscon.h>
17 #include <linux/phy/phy.h>
21 #include <dt-bindings/phy/phy.h>
46 struct regmap *syscon; member
49 struct phy *phy; member
50 struct histb_combphy_mode mode; member
56 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
74 static int is_mode_fixed(struct histb_combphy_mode *mode) in is_mode_fixed() argument
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H A Dphy-hi3660-usb3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Phy provider for USB 3.0 controller on HiSilicon 3660 platform
5 * Copyright (C) 2017-2018 Hilisicon Electronics Co., Ltd.
12 #include <linux/mfd/syscon.h>
15 #include <linux/phy/phy.h>
55 /* This value config the default txtune parameter of the usb 2.0 phy */
66 static int hi3660_phy_init(struct phy *phy) in hi3660_phy_init() argument
68 struct hi3660_priv *priv = phy_get_drvdata(phy); in hi3660_phy_init()
73 ret = regmap_write(priv->peri_crg, PERI_CRG_ISODIS, USB_REFCLK_ISO_EN); in hi3660_phy_init()
79 ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, val); in hi3660_phy_init()
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dhisilicon-hns-dsaf.txt4 - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
5 "hisilicon,hns-dsaf-v1" is for hip05.
6 "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
7 - mode: dsa fabric mode string. only support one of dsaf modes like these:
8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
12 - interrupts: should contain the DSA Fabric and rcb interrupt.
13 - reg: specifies base physical address(es) and size of the device registers.
[all …]
H A Dsocionext,uniphier-ave4.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/socionext,uniphier-ave4.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro4-ave4
20 - socionext,uniphier-pxs2-ave4
21 - socionext,uniphier-ld11-ave4
22 - socionext,uniphier-ld20-ave4
23 - socionext,uniphier-pxs3-ave4
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H A Dallwinner,sun8i-a83t-emac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun8i-a83t-emac
17 - const: allwinner,sun8i-h3-emac
18 - const: allwinner,sun8i-r40-gmac
19 - const: allwinner,sun8i-v3s-emac
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H A Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7110-dwmac
21 - compatible
26 - enum:
27 - starfive,jh7110-dwmac
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H A Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
26 - compatible
29 - $ref: snps,dwmac.yaml#
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H A Dhisilicon-hip04-net.txt6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
10 phandle, specifies a reference to the syscon ppe node
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
28 - compatible: "hisilicon,hip04-ppe", "syscon".
29 - reg: address and length of the register set for the device.
36 - compatible: should be "hisilicon,mdio".
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H A Dcpsw.txt2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
16 - bd_ram_size : Specifies internal descriptor RAM size
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H A Dcortina,gemini-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
19 const: cortina,gemini-ethernet
23 description: must contain the global registers and the V-bit and A-bit
26 "#address-cells":
29 "#size-cells":
38 "^ethernet-port@[0-9]+$":
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/openbmc/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dexynos-pmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
12 # Custom select to avoid matching all nodes with 'syscon'
18 - samsung,exynos3250-pmu
19 - samsung,exynos4210-pmu
20 - samsung,exynos4212-pmu
21 - samsung,exynos4412-pmu
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/openbmc/linux/drivers/phy/ti/
H A Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/phy/phy.h>
19 #include <linux/phy/omap_control_phy.h>
21 #include <linux/mfd/syscon.h>
177 unsigned int dpll_reset_reg; /* reg. index within syscon */
178 unsigned int power_reg; /* power reg. index within syscon */
179 unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */
181 enum pipe3_mode mode; member
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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../snps,dw-pcie.yaml
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H A Daxis,artpec6-pcie.txt1 * Axis ARTPEC-6 PCIe interface
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
12 the PHY controller, and configuration address space.
13 - reg-names: Must include the following entries:
14 - "dbi"
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/openbmc/linux/drivers/phy/marvell/
H A Dphy-mvebu-cp110-utmi.c1 // SPDX-License-Identifier: GPL-2.0
8 * Marvell CP110 UTMI PHY driver
13 #include <linux/mfd/syscon.h>
16 #include <linux/phy/phy.h>
79 #define PORT_REGS(p) ((p)->priv->regs + (p)->id * 0x1000)
82 * struct mvebu_cp110_utmi - PHY driver data
84 * @regs: PHY registers
85 * @syscon: Regmap with system controller registers
87 * @ops: phy ops
91 struct regmap *syscon; member
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dstarfive,jh7110-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PCIe 2.0 PHY
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-pcie-phy
19 "#phy-cells":
22 starfive,sys-syscon:
23 $ref: /schemas/types.yaml#/definitions/phandle-array
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H A Dmixel,mipi-dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mixel DSI PHY for i.MX8
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
17 The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
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H A Drockchip-pcie-phy.txt1 Rockchip PCIE PHY
2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
13 Required properties for legacy PHY mode (deprecated):
14 - #phy-cells: must be 0
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/openbmc/linux/drivers/phy/starfive/
H A Dphy-jh7110-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 PCIe 2.0 PHY driver
14 #include <linux/mfd/syscon.h>
15 #include <linux/phy/phy.h>
37 struct phy *phy; member
44 enum phy_mode mode; member
49 if (!data->stg_syscon || !data->sys_syscon) { in phy_usb3_mode_set()
50 dev_err(&data->phy->dev, "doesn't support usb3 mode\n"); in phy_usb3_mode_set()
51 return -EINVAL; in phy_usb3_mode_set()
54 regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, in phy_usb3_mode_set()
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/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
27 - mediatek,mt8186-mtu3
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H A Dmediatek,mtk-xhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
[all …]
/openbmc/linux/drivers/phy/samsung/
H A Dphy-samsung-ufs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * UFS PHY driver for Samsung SoC
16 #include <linux/mfd/syscon.h>
18 #include <linux/phy/phy.h>
22 #include "phy-samsung-ufs.h"
24 #define for_each_phy_lane(phy, i) \ argument
25 for (i = 0; i < (phy)->lane_cnt; i++)
27 for (; (cfg)->id; (cfg)++)
31 static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy, in samsung_ufs_phy_config() argument
39 writel(cfg->val, (phy)->reg_pma + cfg->off_0); in samsung_ufs_phy_config()
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/openbmc/linux/drivers/media/platform/ti/omap3isp/
H A Dispcsiphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - CSI PHY module
23 static void csiphy_routing_cfg_3630(struct isp_csiphy *phy, in csiphy_routing_cfg_3630() argument
28 u32 shift, mode; in csiphy_routing_cfg_3630() local
30 regmap_read(phy->isp->syscon, phy->isp->syscon_offset, &reg); in csiphy_routing_cfg_3630()
42 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
50 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
54 /* Select data/clock or data/strobe mode for CCP2 */ in csiphy_routing_cfg_3630()
58 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE; in csiphy_routing_cfg_3630()
60 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK; in csiphy_routing_cfg_3630()
[all …]
/openbmc/linux/drivers/pci/controller/dwc/
H A Dpci-keystone.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 * Implementation based on pci-exynos.c and pcie-designware.c
19 #include <linux/mfd/syscon.h>
24 #include <linux/phy/phy.h>
31 #include "pcie-designware.h"
59 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1)))
60 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1)))
84 #define ERR_NONFATAL BIT(2) /* Non-fatal error */
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/openbmc/linux/drivers/usb/dwc3/
H A Ddwc3-am62.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-am62.c - TI specific Glue layer for AM62 DWC3 USB Controller
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
12 #include <linux/mfd/syscon.h>
45 /* PHY CONFIG register bits */
54 /* MODE CONTROL register bits */
100 /* Mask for PHY PLL REFCLK */
110 struct regmap *syscon; member
134 return readl((am62->usbss) + offset); in dwc3_ti_readl()
139 writel(value, (am62->usbss) + offset); in dwc3_ti_writel()
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