1208b65f7SCorentin Labbe# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2208b65f7SCorentin Labbe%YAML 1.2 3208b65f7SCorentin Labbe--- 4208b65f7SCorentin Labbe$id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml# 5208b65f7SCorentin Labbe$schema: http://devicetree.org/meta-schemas/core.yaml# 6208b65f7SCorentin Labbe 7208b65f7SCorentin Labbetitle: Cortina Systems Gemini Ethernet Controller 8208b65f7SCorentin Labbe 9208b65f7SCorentin Labbemaintainers: 10208b65f7SCorentin Labbe - Linus Walleij <linus.walleij@linaro.org> 11208b65f7SCorentin Labbe 12208b65f7SCorentin Labbedescription: | 13208b65f7SCorentin Labbe This ethernet controller is found in the Gemini SoC family: 14208b65f7SCorentin Labbe StorLink SL3512 and SL3516, also known as Cortina Systems 15208b65f7SCorentin Labbe CS3512 and CS3516. 16208b65f7SCorentin Labbe 17208b65f7SCorentin Labbeproperties: 18208b65f7SCorentin Labbe compatible: 19208b65f7SCorentin Labbe const: cortina,gemini-ethernet 20208b65f7SCorentin Labbe 21208b65f7SCorentin Labbe reg: 22208b65f7SCorentin Labbe minItems: 3 23208b65f7SCorentin Labbe description: must contain the global registers and the V-bit and A-bit 24208b65f7SCorentin Labbe memory areas, in total three register sets. 25208b65f7SCorentin Labbe 26208b65f7SCorentin Labbe "#address-cells": 27208b65f7SCorentin Labbe const: 1 28208b65f7SCorentin Labbe 29208b65f7SCorentin Labbe "#size-cells": 30208b65f7SCorentin Labbe const: 1 31208b65f7SCorentin Labbe 32208b65f7SCorentin Labbe ranges: true 33208b65f7SCorentin Labbe 34208b65f7SCorentin Labbe# The subnodes represents the two ethernet ports in this device. 35208b65f7SCorentin Labbe# They are not independent of each other since they share resources 36208b65f7SCorentin Labbe# in the parent node, and are thus children. 37208b65f7SCorentin LabbepatternProperties: 38208b65f7SCorentin Labbe "^ethernet-port@[0-9]+$": 39208b65f7SCorentin Labbe type: object 40*057062adSRob Herring unevaluatedProperties: false 41208b65f7SCorentin Labbe description: contains the resources for ethernet port 42208b65f7SCorentin Labbe allOf: 43208b65f7SCorentin Labbe - $ref: ethernet-controller.yaml# 44208b65f7SCorentin Labbe properties: 45208b65f7SCorentin Labbe compatible: 46208b65f7SCorentin Labbe const: cortina,gemini-ethernet-port 47208b65f7SCorentin Labbe 48208b65f7SCorentin Labbe reg: 49208b65f7SCorentin Labbe items: 50208b65f7SCorentin Labbe - description: DMA/TOE memory 51208b65f7SCorentin Labbe - description: GMAC memory area of the port 52208b65f7SCorentin Labbe 53208b65f7SCorentin Labbe interrupts: 54208b65f7SCorentin Labbe maxItems: 1 55208b65f7SCorentin Labbe description: should contain the interrupt line of the port. 56208b65f7SCorentin Labbe this is nominally a level interrupt active high. 57208b65f7SCorentin Labbe 58208b65f7SCorentin Labbe resets: 59208b65f7SCorentin Labbe maxItems: 1 60208b65f7SCorentin Labbe description: this must provide an SoC-integrated reset line for the port. 61208b65f7SCorentin Labbe 62208b65f7SCorentin Labbe clocks: 63208b65f7SCorentin Labbe maxItems: 1 64208b65f7SCorentin Labbe description: this should contain a handle to the PCLK clock for 65208b65f7SCorentin Labbe clocking the silicon in this port 66208b65f7SCorentin Labbe 67208b65f7SCorentin Labbe clock-names: 68208b65f7SCorentin Labbe const: PCLK 69208b65f7SCorentin Labbe 70208b65f7SCorentin Labbe required: 71208b65f7SCorentin Labbe - reg 72208b65f7SCorentin Labbe - compatible 73208b65f7SCorentin Labbe - interrupts 74208b65f7SCorentin Labbe - resets 75208b65f7SCorentin Labbe - clocks 76208b65f7SCorentin Labbe - clock-names 77208b65f7SCorentin Labbe 78208b65f7SCorentin Labberequired: 79208b65f7SCorentin Labbe - compatible 80208b65f7SCorentin Labbe - reg 81208b65f7SCorentin Labbe - ranges 82208b65f7SCorentin Labbe 83208b65f7SCorentin LabbeadditionalProperties: false 84208b65f7SCorentin Labbe 85208b65f7SCorentin Labbeexamples: 86208b65f7SCorentin Labbe - | 87208b65f7SCorentin Labbe #include <dt-bindings/interrupt-controller/irq.h> 88208b65f7SCorentin Labbe #include <dt-bindings/clock/cortina,gemini-clock.h> 89208b65f7SCorentin Labbe #include <dt-bindings/reset/cortina,gemini-reset.h> 90208b65f7SCorentin Labbe mdio0: mdio { 91208b65f7SCorentin Labbe #address-cells = <1>; 92208b65f7SCorentin Labbe #size-cells = <0>; 93208b65f7SCorentin Labbe phy0: ethernet-phy@1 { 94208b65f7SCorentin Labbe reg = <1>; 95208b65f7SCorentin Labbe device_type = "ethernet-phy"; 96208b65f7SCorentin Labbe }; 97208b65f7SCorentin Labbe phy1: ethernet-phy@3 { 98208b65f7SCorentin Labbe reg = <3>; 99208b65f7SCorentin Labbe device_type = "ethernet-phy"; 100208b65f7SCorentin Labbe }; 101208b65f7SCorentin Labbe }; 102208b65f7SCorentin Labbe 103208b65f7SCorentin Labbe 104208b65f7SCorentin Labbe ethernet@60000000 { 105208b65f7SCorentin Labbe compatible = "cortina,gemini-ethernet"; 106208b65f7SCorentin Labbe reg = <0x60000000 0x4000>, /* Global registers, queue */ 107208b65f7SCorentin Labbe <0x60004000 0x2000>, /* V-bit */ 108208b65f7SCorentin Labbe <0x60006000 0x2000>; /* A-bit */ 109208b65f7SCorentin Labbe #address-cells = <1>; 110208b65f7SCorentin Labbe #size-cells = <1>; 111208b65f7SCorentin Labbe ranges; 112208b65f7SCorentin Labbe 113208b65f7SCorentin Labbe gmac0: ethernet-port@0 { 114208b65f7SCorentin Labbe compatible = "cortina,gemini-ethernet-port"; 115208b65f7SCorentin Labbe reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ 116208b65f7SCorentin Labbe <0x6000a000 0x2000>; /* Port 0 GMAC */ 117208b65f7SCorentin Labbe interrupt-parent = <&intcon>; 118208b65f7SCorentin Labbe interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 119208b65f7SCorentin Labbe resets = <&syscon GEMINI_RESET_GMAC0>; 120208b65f7SCorentin Labbe clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; 121208b65f7SCorentin Labbe clock-names = "PCLK"; 122208b65f7SCorentin Labbe phy-mode = "rgmii"; 123208b65f7SCorentin Labbe phy-handle = <&phy0>; 124208b65f7SCorentin Labbe }; 125208b65f7SCorentin Labbe 126208b65f7SCorentin Labbe gmac1: ethernet-port@1 { 127208b65f7SCorentin Labbe compatible = "cortina,gemini-ethernet-port"; 128208b65f7SCorentin Labbe reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ 129208b65f7SCorentin Labbe <0x6000e000 0x2000>; /* Port 1 GMAC */ 130208b65f7SCorentin Labbe interrupt-parent = <&intcon>; 131208b65f7SCorentin Labbe interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 132208b65f7SCorentin Labbe resets = <&syscon GEMINI_RESET_GMAC1>; 133208b65f7SCorentin Labbe clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; 134208b65f7SCorentin Labbe clock-names = "PCLK"; 135208b65f7SCorentin Labbe phy-mode = "rgmii"; 136208b65f7SCorentin Labbe phy-handle = <&phy1>; 137208b65f7SCorentin Labbe }; 138208b65f7SCorentin Labbe }; 139