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/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-irq.c15 static void xpu_ack(struct cx18 *cx, u32 sw2) in xpu_ack() argument
17 if (sw2 & IRQ_CPU_TO_EPU_ACK) in xpu_ack()
19 if (sw2 & IRQ_APU_TO_EPU_ACK) in xpu_ack()
34 u32 sw1, sw2, hw2; in cx18_irq_handler() local
37 sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & cx->sw2_irq_mask; in cx18_irq_handler()
42 if (sw2) in cx18_irq_handler()
43 cx18_write_reg_expect(cx, sw2, SW2_INT_STATUS, ~sw2, sw2); in cx18_irq_handler()
47 if (sw1 || sw2 || hw2) in cx18_irq_handler()
48 CX18_DEBUG_HI_IRQ("received interrupts SW1: %x SW2: %x HW2: %x\n", in cx18_irq_handler()
49 sw1, sw2, hw2); in cx18_irq_handler()
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/openbmc/linux/tools/testing/selftests/net/
H A Dtest_bridge_backup_port.sh35 # | sw1 | | sw2 |
154 setup_ns sw1 sw2
155 for ns in $sw1 $sw2; do
161 ip link set dev veth1 netns $sw2 name veth0
213 local ns=$sw2
239 cleanup_ns $sw1 $sw2
363 run_cmd "ip -n $sw2 address replace 192.0.2.36/32 dev lo"
368 run_cmd "tc -n $sw2 qdisc replace dev vx0 clsact"
369 …run_cmd "tc -n $sw2 filter replace dev vx0 ingress pref 1 handle 101 proto ip flower src_mac $smac…
370 …run_cmd "tc -n $sw2 filter replace dev vx0 ingress pref 1 handle 102 proto ip flower src_mac $smac…
[all …]
/openbmc/u-boot/board/freescale/ls1088a/
H A DREADME17 SW2 x100 0000
24 SW2 0100 0000
31 SW2 1100 0000
73 SW2 x110 1111
77 SW2 0110 1111
81 SW2 0110 1111
85 SW2 1110 1111
89 SW2 1110 1111
/openbmc/u-boot/doc/
H A DREADME.mpc85xxcds88 SW2[2] on the carrier card before resetting the board in order to set the
101 The first two bits of SW2 control how flash is used on the board:
105 SW2=00XXXXXX FLASH: Boot bank 1, bank 2 available.
114 connected.. By convention, the user-specific bits of SW2 are used to
119 SW2=xxxxxx00 PCI SLOT INFORM: The CDS carrier is in slot0 of the Arcadia
133 SW2=0x1111yy x=Flash bank, yy=PCI slot
158 SW2=01000111
172 SW2=10011111
H A DREADME.b4860qds123 SW2 ON ON ON ON ON ON OFF OFF
135 SW2 [1.1] = 1
139 SW2 [1.1] = 0
148 SW2 ON OFF ON OFF ON ON OFF OFF
160 SW2 [1.1] = 1
164 SW2 [1.1] = 0
/openbmc/u-boot/board/sbc8548/
H A DREADME36 card. [The above discussion assumes that the SW2[1-4] has not been changed
194 alternate setting, you also need to switch SW2.8 to ON.
207 SW2.1 CFG_SYS_PLL0 1 0*
208 SW2.2 CFG_SYS_PLL1 1* 0
209 SW2.3 CFG_SYS_PLL2 1* 0
210 SW2.4 CFG_SYS_PLL3 1 0*
211 SW2.5 CFG_CORE_PLL0 1* 0
212 SW2.6 CFG_CORE_PLL1 1 0*
213 SW2.7 CFG_CORE_PLL2 1* 0
214 SW2.8 CFG_ROM_LOC1 1 0*
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dltc3676.txt8 - regulators: Contains eight regulator child nodes sw1, sw2, sw3, sw4,
13 nodes for sw1, sw2, sw3, sw4, ldo1, ldo2 and ldo4 additionally need to specify
20 Regulators sw1, sw2, sw3, sw4 can regulate the feedback reference from:
45 sw2_reg: sw2 {
H A Dpfuze100.yaml15 sw1ab,sw1c,sw2,sw3a,sw3b,sw4,swbst,vsnvs,vrefddr,vgen1~vgen6
17 sw1ab,sw2,sw3a,sw3b,swbst,vsnvs,vrefddr,vgen1~vgen6,coin
19 sw1a,sw1b,sw2,sw3,swbst,vsnvs,vrefddr,vldo1,vldo2,vccsd,v33,vldo3,vldo4
21 sw1,sw2,sw3,vsnvs,vldo1,vldo2,vccsd,v33,vldo3,vldo4
122 sw2_reg: sw2 {
H A Dltc3589.txt8 - regulators: Contains eight regulator child nodes sw1, sw2, sw3, bb-out,
13 nodes for sw1, sw2, sw3, bb-out, ldo1, and ldo2 additionally need to specify
20 Regulators sw1, sw2, sw3, and ldo2 can regulate the feedback reference from
45 sw2_reg: sw2 {
H A Dpv88060.txt11 BUCK1, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, SW1, SW2, SW3, SW4,
90 SW2 {
91 regulator-name = "sw2";
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME287 SW2: 10111011
292 SW2: 00111011
297 SW2: 10111011
302 SW2: 00111011
309 SW2: 10111001
314 SW2: 00111001
319 SW2: 10111001
324 SW2: 00111001
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dsh73a0-kzm9g.dts113 label = "SW2-R";
119 label = "SW2-L";
125 label = "SW2-P";
131 label = "SW2-U";
137 label = "SW2-D";
H A Dr8a7792-blanche.dts120 label = "SW2-1";
127 label = "SW2-2";
134 label = "SW2-3";
141 label = "SW2-4";
H A Dr8a7794-alt.dts106 label = "SW2-1";
113 label = "SW2-2";
120 label = "SW2-3";
127 label = "SW2-4";
/openbmc/u-boot/arch/arm/dts/
H A Dr8a7792-blanche.dts117 label = "SW2-1";
124 label = "SW2-2";
131 label = "SW2-3";
138 label = "SW2-4";
/openbmc/u-boot/board/freescale/corenet_ds/
H A Deth_hydra.c285 * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
290 u8 sw2 = in_8(&PIXIS_SW(2)); in initialize_lane_to_slot() local
292 lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; in initialize_lane_to_slot()
295 lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; in initialize_lane_to_slot()
298 switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { in initialize_lane_to_slot()
311 lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; in initialize_lane_to_slot()
313 lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; in initialize_lane_to_slot()
H A Deth_superhydra.c247 * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
252 u8 sw2 = in_8(&PIXIS_SW(2)); in initialize_lane_to_slot() local
256 lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; in initialize_lane_to_slot()
259 lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; in initialize_lane_to_slot()
262 switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { in initialize_lane_to_slot()
275 lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; in initialize_lane_to_slot()
278 lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; in initialize_lane_to_slot()
/openbmc/u-boot/board/freescale/mx35pdk/
H A DREADME14 switch the boot device with the switches SW1-SW2 on the Personality board,
77 (SW1-SW2) and on the DEBUG board (SW4-SW10).
105 SW2 all off
/openbmc/linux/drivers/staging/media/atomisp/pci/
H A Dsh_css_hrt.c69 * Wait till SP is idle or till there is a SW2 interrupt in sh_css_hrt_sp_wait()
70 * The SW2 interrupt will be used when frameloop runs on SP in sh_css_hrt_sp_wait()
/openbmc/linux/drivers/regulator/
H A Dpfuze100-regulator.c373 PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
391 PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
409 PFUZE3000_SW_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
424 PFUZE3000_SW_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
439 { .name = "sw2", },
459 { .name = "sw2", },
479 { .name = "sw2", },
496 { .name = "sw2", },
783 /* SW2~SW4 high bit check and modify the voltage value table */ in pfuze100_regulator_probe()
/openbmc/u-boot/board/freescale/t208xrdb/
H A DREADME142 SW2[1:8] = '10111111'
154 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
173 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
184 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
193 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
/openbmc/u-boot/board/freescale/mpc837xemds/
H A DREADME18 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
19 SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME194 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
196 set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
223 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
237 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
248 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53-qsrb.dts50 sw2_reg: sw2 {
51 regulator-name = "SW2";
/openbmc/u-boot/board/freescale/mpc8536ds/
H A DREADME36 SW2[5-8] = 1011
70 SW2[5-8] = 0111
123 SW2[5-8] = 0110

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