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/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dnuvoton,npcm750-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton NPCM Reset controller
10 - Tomer Maimon <tmaimon77@gmail.com>
15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
16 - nuvoton,npcm845-reset # Arbel NPCM8XX SoC
21 '#reset-cells':
24 '#clock-cells':
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_ctl.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
26 * struct dpu_hw_stage_cfg - blending stage cfg
42 * @stream_sel: Stream selection for multi-stream interfaces
56 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions
61 * kickoff hw operation for Sw controlled interfaces
62 * DSI cmd mode and WB interface are SW controlled
75 * kickoff prepare is in progress hw operation for sw
77 * are SW controlled
156 * @dspp_sub_blk : DSPP sub-block index
[all …]
/openbmc/linux/drivers/thunderbolt/
H A Dlc.c1 // SPDX-License-Identifier: GPL-2.0
14 * tb_lc_read_uuid() - Read switch UUID from link controller common register
15 * @sw: Switch whose UUID is read
18 int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid) in tb_lc_read_uuid() argument
20 if (!sw->cap_lc) in tb_lc_read_uuid()
21 return -EINVAL; in tb_lc_read_uuid()
22 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4); in tb_lc_read_uuid()
25 static int read_lc_desc(struct tb_switch *sw, u32 *desc) in read_lc_desc() argument
27 if (!sw->cap_lc) in read_lc_desc()
28 return -EINVAL; in read_lc_desc()
[all …]
H A Dtb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt driver - bus logic (NHI independent)
12 #include <linux/nvmem-provider.h>
30 * struct tb_nvm - Structure holding NVM information
32 * @major: Major version number of the active NVM portion
33 * @minor: Minor version number of the active NVM portion
37 * @non_active: Non-active portion NVMem device
42 * @buf_data_size: Number of bytes actually consumed by the new NVM
78 * enum tb_switch_tmu_mode - TMU mode
80 * @TB_SWITCH_TMU_MODE_LOWRES: Uni-directional, normal mode
[all …]
H A Ddma_port.c1 // SPDX-License-Identifier: GPL-2.0
48 * struct tb_dma_port - DMA control port
49 * @sw: Switch the DMA port belongs to
50 * @port: Switch port number where DMA capability is found
55 struct tb_switch *sw; member
68 u64 route = tb_cfg_get_route(pkg->buffer) & ~BIT_ULL(63); in dma_port_match()
70 if (pkg->frame.eof == TB_CFG_PKG_ERROR) in dma_port_match()
72 if (pkg->frame.eof != req->response_type) in dma_port_match()
74 if (route != tb_cfg_get_route(req->request)) in dma_port_match()
76 if (pkg->frame.size != req->response_size) in dma_port_match()
[all …]
H A Dswitch.c1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt driver - switch/port utility functions
12 #include <linux/nvmem-provider.h>
37 static struct nvm_auth_status *__nvm_get_auth_status(const struct tb_switch *sw) in __nvm_get_auth_status() argument
42 if (uuid_equal(&st->uuid, sw->uuid)) in __nvm_get_auth_status()
49 static void nvm_get_auth_status(const struct tb_switch *sw, u32 *status) in nvm_get_auth_status() argument
54 st = __nvm_get_auth_status(sw); in nvm_get_auth_status()
57 *status = st ? st->status : 0; in nvm_get_auth_status()
60 static void nvm_set_auth_status(const struct tb_switch *sw, u32 status) in nvm_set_auth_status() argument
64 if (WARN_ON(!sw->uuid)) in nvm_set_auth_status()
[all …]
H A Dicm.c1 // SPDX-License-Identifier: GPL-2.0
4 * the Thunderbolt host controller performing most of the low-level
53 * struct usb4_switch_nvm_auth - Holds USB4 NVM_AUTH status
65 * struct icm - Internal connection manager private data
74 * @max_boot_acl: Maximum number of preboot ACL entries (%0 if not supported)
81 * @cio_reset: Trigger CIO reset
158 if (!ep->len) in parse_intel_vss()
160 if (ep_name + ep->len > end) in parse_intel_vss()
163 if (ep->type == EP_NAME_INTEL_VSS) in parse_intel_vss()
164 return (const struct intel_vss *)ep->data; in parse_intel_vss()
[all …]
/openbmc/u-boot/board/freescale/common/
H A Dngpixis.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2010-2011 Freescale Semiconductor
6 * This file provides support for the ngPIXIS, a board-specific FPGA used on
10 * eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that
17 * PIXIS_BASE - The virtual address of the base of the PIXIS register map
19 * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
24 * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
26 * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
28 * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
56 * Reset the board. This ignores the ENx registers.
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_x540.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
31 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X540()
32 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X540()
35 phy->ops.set_phy_power = ixgbe_set_copper_phy_power; in ixgbe_get_invariants_X540()
37 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; in ixgbe_get_invariants_X540()
38 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; in ixgbe_get_invariants_X540()
39 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; in ixgbe_get_invariants_X540()
40 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; in ixgbe_get_invariants_X540()
41 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; in ixgbe_get_invariants_X540()
[all …]
/openbmc/linux/include/linux/mfd/
H A Daltera-a10sr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
27 * the number of GPIO in each register. We then need to multiply
39 #define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */
41 #define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */
45 #define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */
46 #define ALTR_A10SR_PBDSW_IRQ_REG 0x06 /* PB & DIP SW Flag Clear */
55 #define ALTR_A10SR_HPS_RST_REG 0x10 /* HPS Reset */
56 #define ALTR_A10SR_USB_QSPI_REG 0x12 /* USB, BQSPI, FILE Reset */
60 #define ALTR_A10SR_WARM_RST_REG 0x1A /* HPS Warm Reset */
[all …]
/openbmc/linux/include/linux/soc/ti/
H A Dk3-ringacc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
16 * enum k3_ring_mode - &struct k3_ring_cfg mode
20 * @K3_RINGACC_RING_MODE_RING: Exposed Ring mode for SW direct access
24 * controls the entire state of the queue, and SW has no directly control,
26 * This is particularly useful when more than one SW or HW entity can be
41 * enum k3_ring_size - &struct k3_ring_cfg elm_size
60 * enum k3_ring_cfg - RA ring configuration structure
62 * @size: Ring size, number of elements
86 #define K3_RINGACC_RING_ID_ANY (-1)
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
[all …]
/openbmc/u-boot/board/micronas/vct/
H A Dscc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
17 #define DMA_START 0 /* DMA command - start DMA */
18 #define DMA_STOP 1 /* DMA command - stop DMA */
19 #define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */
20 #define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */
29 #define SCC_DBG_SYNC_RES 0x0001 /* synchronuous reset */
61 u32 p_scc_id; /* instance number of SCC unit */
65 u32 p_dma_channels_rd; /* Number of Read DMA channels */
66 u32 p_dma_channels_wr; /* Number of Write DMA channels */
68 u32 p_dma_packet_desc; /* Number of packet descriptors */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dnvidia,tegra124-soctherm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 polled or interrupt-based thermal monitoring, CPU and GPU throttling based
21 - nvidia,tegra124-soctherm
22 - nvidia,tegra132-soctherm
23 - nvidia,tegra210-soctherm
[all …]
/openbmc/linux/drivers/net/ethernet/sun/
H A Dsunhme.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GREG_SWRESET 0x000UL /* Software Reset */
21 /* Global reset register. */
38 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
39 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
40 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
42 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
46 #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
47 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
48 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
[all …]
/openbmc/linux/arch/alpha/kernel/
H A Dsignal.c1 // SPDX-License-Identifier: GPL-2.0
7 * 1997-11-02 Modified for POSIX.1b signals by Richard Henderson
69 __get_user(new_ka.sa.sa_handler, &act->sa_handler) || in SYSCALL_DEFINE3()
70 __get_user(new_ka.sa.sa_flags, &act->sa_flags) || in SYSCALL_DEFINE3()
71 __get_user(mask, &act->sa_mask)) in SYSCALL_DEFINE3()
72 return -EFAULT; in SYSCALL_DEFINE3()
81 __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || in SYSCALL_DEFINE3()
82 __put_user(old_ka.sa.sa_flags, &oact->sa_flags) || in SYSCALL_DEFINE3()
83 __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask)) in SYSCALL_DEFINE3()
84 return -EFAULT; in SYSCALL_DEFINE3()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c1 // SPDX-License-Identifier: GPL-2.0
91 u32 pbs_rep_time = 0; /* counts number of loop in case of fail */ in ddr3_pbs_tx()
92 /* bit array for unlock pups - used to repeat on the RX operation */ in ddr3_pbs_tx()
102 DEBUG_PBS_S("DDR3 - PBS TX - Starting PBS TX procedure\n"); in ddr3_pbs_tx()
104 pups = dram_info->num_of_total_pups; in ddr3_pbs_tx()
105 max_pup = dram_info->num_of_total_pups; in ddr3_pbs_tx()
107 /* Enable SW override */ in ddr3_pbs_tx()
110 /* [0] = 1 - Enable SW override */ in ddr3_pbs_tx()
111 /* 0x15B8 - Training SW 2 Register */ in ddr3_pbs_tx()
113 DEBUG_PBS_S("DDR3 - PBS RX - SW Override Enabled\n"); in ddr3_pbs_tx()
[all …]
H A Dddr3_write_leveling.c1 // SPDX-License-Identifier: GPL-2.0
59 * Args: freq - current sequence frequency
60 * dram_info - main struct
70 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
71 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
84 /* Config the retest number */ in ddr3_write_leveling_hw()
86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
103 * Read results to arrays - Results are required for WL in ddr3_write_leveling_hw()
107 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
[all …]
/openbmc/u-boot/board/CZ.NIC/turris_mox/
H A Dturris_mox.c1 // SPDX-License-Identifier: GPL-2.0+
46 gd->ram_base = 0; in dram_init()
47 gd->ram_size = (phys_size_t)get_ram_size(0, 0x40000000); in dram_init()
54 gd->bd->bi_dram[0].start = (phys_addr_t)0; in dram_init_banksize()
55 gd->bd->bi_dram[0].size = gd->ram_size; in dram_init_banksize()
69 * if pcie should be enabled in U-Boot's device tree. Therefore we have in board_fix_fdt()
107 printf("Cannot find PCIe node in U-Boot's device tree!\n"); in board_fix_fdt()
113 printf("Cannot %s PCIe in U-Boot's device tree!\n", in board_fix_fdt()
135 /* Do not reset the watchdog too often */ in watchdog_reset()
146 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dxhci.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Based on xHCI host controller driver in linux-kernel
29 /* Max number of USB devices for any host controller - limit in section 6.1 */
31 /* Section 5.3.3 - MaxPorts */
42 * connect status, over-current status, port speed, and device removable.
43 * connect status and port speed are also sticky - meaning they're in
44 * the AUX well and they aren't changed by a hot, warm, or cold reset.
55 * bit 4 (port reset)
63 * warm port reset changed (reserved zero for USB 2.0 ports),
64 * over-current, reset, link state, and L1 change
[all …]
/openbmc/linux/arch/openrisc/kernel/
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
26 #include <asm/asm-offsets.h>
30 l.movhi rd,hi(-KERNELBASE) ;\
73 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
76 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
79 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
82 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
85 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
88 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
[all …]
/openbmc/linux/drivers/usb/host/
H A Dxhci-caps.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 /* bits 7:0 - how long is the Capabilities register */
9 /* HCSPARAMS1 - hcs_params1 - bitmasks */
15 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
18 /* HCSPARAMS2 - hcs_params2 - bitmasks */
19 /* bits 0:3, frames or uframes that SW needs to queue transactions
22 /* bits 4:7, max number of Event Ring segments */
24 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
25 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
26 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Ddefines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
36 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
182 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2023, Intel Corporation. */
88 * ice_dump_phy_type - helper function to dump phy_type
115 * ice_set_mac_type - Sets MAC type
123 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) in ice_set_mac_type()
124 return -ENODEV; in ice_set_mac_type()
126 switch (hw->device_id) { in ice_set_mac_type()
133 hw->mac_type = ICE_MAC_E810; in ice_set_mac_type()
154 hw->mac_type = ICE_MAC_GENERIC; in ice_set_mac_type()
160 hw->mac_type = ICE_MAC_E830; in ice_set_mac_type()
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dgdsc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
17 * struct gdsc - Globally Distributed Switch Controller
21 * @collapse_ctrl: APCS collapse-vote register
22 * @collapse_mask: APCS collapse-vote mask
25 * @cxc_count: number of @cxcs
31 * @reset_count: number of @resets
32 * @rcdev: reset controller
52 * There is no SW control to transition a GDSC into
94 return -ENOSYS; in gdsc_register()

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