17ec59eeaSAnirudh Venkataramanan // SPDX-License-Identifier: GPL-2.0
27ec59eeaSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */
37ec59eeaSAnirudh Venkataramanan
47ec59eeaSAnirudh Venkataramanan #include "ice_common.h"
59c20346bSAnirudh Venkataramanan #include "ice_sched.h"
67ec59eeaSAnirudh Venkataramanan #include "ice_adminq_cmd.h"
7c90ed40cSTony Nguyen #include "ice_flow.h"
8272ad794SKarol Kolacinski #include "ice_ptp_hw.h"
97ec59eeaSAnirudh Venkataramanan
1071245072SJacob Keller #define ICE_PF_RESET_WAIT_COUNT 300
11f31e4b6fSAnirudh Venkataramanan
12f8c74ca6SAnirudh Venkataramanan static const char * const ice_link_mode_str_low[] = {
13f8c74ca6SAnirudh Venkataramanan [0] = "100BASE_TX",
14f8c74ca6SAnirudh Venkataramanan [1] = "100M_SGMII",
15f8c74ca6SAnirudh Venkataramanan [2] = "1000BASE_T",
16f8c74ca6SAnirudh Venkataramanan [3] = "1000BASE_SX",
17f8c74ca6SAnirudh Venkataramanan [4] = "1000BASE_LX",
18f8c74ca6SAnirudh Venkataramanan [5] = "1000BASE_KX",
19f8c74ca6SAnirudh Venkataramanan [6] = "1G_SGMII",
20f8c74ca6SAnirudh Venkataramanan [7] = "2500BASE_T",
21f8c74ca6SAnirudh Venkataramanan [8] = "2500BASE_X",
22f8c74ca6SAnirudh Venkataramanan [9] = "2500BASE_KX",
23f8c74ca6SAnirudh Venkataramanan [10] = "5GBASE_T",
24f8c74ca6SAnirudh Venkataramanan [11] = "5GBASE_KR",
25f8c74ca6SAnirudh Venkataramanan [12] = "10GBASE_T",
26f8c74ca6SAnirudh Venkataramanan [13] = "10G_SFI_DA",
27f8c74ca6SAnirudh Venkataramanan [14] = "10GBASE_SR",
28f8c74ca6SAnirudh Venkataramanan [15] = "10GBASE_LR",
29f8c74ca6SAnirudh Venkataramanan [16] = "10GBASE_KR_CR1",
30f8c74ca6SAnirudh Venkataramanan [17] = "10G_SFI_AOC_ACC",
31f8c74ca6SAnirudh Venkataramanan [18] = "10G_SFI_C2C",
32f8c74ca6SAnirudh Venkataramanan [19] = "25GBASE_T",
33f8c74ca6SAnirudh Venkataramanan [20] = "25GBASE_CR",
34f8c74ca6SAnirudh Venkataramanan [21] = "25GBASE_CR_S",
35f8c74ca6SAnirudh Venkataramanan [22] = "25GBASE_CR1",
36f8c74ca6SAnirudh Venkataramanan [23] = "25GBASE_SR",
37f8c74ca6SAnirudh Venkataramanan [24] = "25GBASE_LR",
38f8c74ca6SAnirudh Venkataramanan [25] = "25GBASE_KR",
39f8c74ca6SAnirudh Venkataramanan [26] = "25GBASE_KR_S",
40f8c74ca6SAnirudh Venkataramanan [27] = "25GBASE_KR1",
41f8c74ca6SAnirudh Venkataramanan [28] = "25G_AUI_AOC_ACC",
42f8c74ca6SAnirudh Venkataramanan [29] = "25G_AUI_C2C",
43f8c74ca6SAnirudh Venkataramanan [30] = "40GBASE_CR4",
44f8c74ca6SAnirudh Venkataramanan [31] = "40GBASE_SR4",
45f8c74ca6SAnirudh Venkataramanan [32] = "40GBASE_LR4",
46f8c74ca6SAnirudh Venkataramanan [33] = "40GBASE_KR4",
47f8c74ca6SAnirudh Venkataramanan [34] = "40G_XLAUI_AOC_ACC",
48f8c74ca6SAnirudh Venkataramanan [35] = "40G_XLAUI",
49f8c74ca6SAnirudh Venkataramanan [36] = "50GBASE_CR2",
50f8c74ca6SAnirudh Venkataramanan [37] = "50GBASE_SR2",
51f8c74ca6SAnirudh Venkataramanan [38] = "50GBASE_LR2",
52f8c74ca6SAnirudh Venkataramanan [39] = "50GBASE_KR2",
53f8c74ca6SAnirudh Venkataramanan [40] = "50G_LAUI2_AOC_ACC",
54f8c74ca6SAnirudh Venkataramanan [41] = "50G_LAUI2",
55f8c74ca6SAnirudh Venkataramanan [42] = "50G_AUI2_AOC_ACC",
56f8c74ca6SAnirudh Venkataramanan [43] = "50G_AUI2",
57f8c74ca6SAnirudh Venkataramanan [44] = "50GBASE_CP",
58f8c74ca6SAnirudh Venkataramanan [45] = "50GBASE_SR",
59f8c74ca6SAnirudh Venkataramanan [46] = "50GBASE_FR",
60f8c74ca6SAnirudh Venkataramanan [47] = "50GBASE_LR",
61f8c74ca6SAnirudh Venkataramanan [48] = "50GBASE_KR_PAM4",
62f8c74ca6SAnirudh Venkataramanan [49] = "50G_AUI1_AOC_ACC",
63f8c74ca6SAnirudh Venkataramanan [50] = "50G_AUI1",
64f8c74ca6SAnirudh Venkataramanan [51] = "100GBASE_CR4",
65f8c74ca6SAnirudh Venkataramanan [52] = "100GBASE_SR4",
66f8c74ca6SAnirudh Venkataramanan [53] = "100GBASE_LR4",
67f8c74ca6SAnirudh Venkataramanan [54] = "100GBASE_KR4",
68f8c74ca6SAnirudh Venkataramanan [55] = "100G_CAUI4_AOC_ACC",
69f8c74ca6SAnirudh Venkataramanan [56] = "100G_CAUI4",
70f8c74ca6SAnirudh Venkataramanan [57] = "100G_AUI4_AOC_ACC",
71f8c74ca6SAnirudh Venkataramanan [58] = "100G_AUI4",
72f8c74ca6SAnirudh Venkataramanan [59] = "100GBASE_CR_PAM4",
73f8c74ca6SAnirudh Venkataramanan [60] = "100GBASE_KR_PAM4",
74f8c74ca6SAnirudh Venkataramanan [61] = "100GBASE_CP2",
75f8c74ca6SAnirudh Venkataramanan [62] = "100GBASE_SR2",
76f8c74ca6SAnirudh Venkataramanan [63] = "100GBASE_DR",
77f8c74ca6SAnirudh Venkataramanan };
78f8c74ca6SAnirudh Venkataramanan
79f8c74ca6SAnirudh Venkataramanan static const char * const ice_link_mode_str_high[] = {
80f8c74ca6SAnirudh Venkataramanan [0] = "100GBASE_KR2_PAM4",
81f8c74ca6SAnirudh Venkataramanan [1] = "100G_CAUI2_AOC_ACC",
82f8c74ca6SAnirudh Venkataramanan [2] = "100G_CAUI2",
83f8c74ca6SAnirudh Venkataramanan [3] = "100G_AUI2_AOC_ACC",
84f8c74ca6SAnirudh Venkataramanan [4] = "100G_AUI2",
85f8c74ca6SAnirudh Venkataramanan };
86f8c74ca6SAnirudh Venkataramanan
87f8c74ca6SAnirudh Venkataramanan /**
88f8c74ca6SAnirudh Venkataramanan * ice_dump_phy_type - helper function to dump phy_type
89f8c74ca6SAnirudh Venkataramanan * @hw: pointer to the HW structure
90f8c74ca6SAnirudh Venkataramanan * @low: 64 bit value for phy_type_low
91f8c74ca6SAnirudh Venkataramanan * @high: 64 bit value for phy_type_high
92f8c74ca6SAnirudh Venkataramanan * @prefix: prefix string to differentiate multiple dumps
93f8c74ca6SAnirudh Venkataramanan */
94f8c74ca6SAnirudh Venkataramanan static void
ice_dump_phy_type(struct ice_hw * hw,u64 low,u64 high,const char * prefix)95f8c74ca6SAnirudh Venkataramanan ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix)
96f8c74ca6SAnirudh Venkataramanan {
97f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low);
98f8c74ca6SAnirudh Venkataramanan
99f8c74ca6SAnirudh Venkataramanan for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) {
100f8c74ca6SAnirudh Venkataramanan if (low & BIT_ULL(i))
101f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
102f8c74ca6SAnirudh Venkataramanan prefix, i, ice_link_mode_str_low[i]);
103f8c74ca6SAnirudh Venkataramanan }
104f8c74ca6SAnirudh Venkataramanan
105f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high);
106f8c74ca6SAnirudh Venkataramanan
107f8c74ca6SAnirudh Venkataramanan for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) {
108f8c74ca6SAnirudh Venkataramanan if (high & BIT_ULL(i))
109f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
110f8c74ca6SAnirudh Venkataramanan prefix, i, ice_link_mode_str_high[i]);
111f8c74ca6SAnirudh Venkataramanan }
112f8c74ca6SAnirudh Venkataramanan }
113f8c74ca6SAnirudh Venkataramanan
114f31e4b6fSAnirudh Venkataramanan /**
115f31e4b6fSAnirudh Venkataramanan * ice_set_mac_type - Sets MAC type
116f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the HW structure
117f31e4b6fSAnirudh Venkataramanan *
118f31e4b6fSAnirudh Venkataramanan * This function sets the MAC type of the adapter based on the
119f9867df6SAnirudh Venkataramanan * vendor ID and device ID stored in the HW structure.
120f31e4b6fSAnirudh Venkataramanan */
ice_set_mac_type(struct ice_hw * hw)1215e24d598STony Nguyen static int ice_set_mac_type(struct ice_hw *hw)
122f31e4b6fSAnirudh Venkataramanan {
123f31e4b6fSAnirudh Venkataramanan if (hw->vendor_id != PCI_VENDOR_ID_INTEL)
124d54699e2STony Nguyen return -ENODEV;
125f31e4b6fSAnirudh Venkataramanan
126ea78ce4dSPaul Greenwalt switch (hw->device_id) {
127ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E810C_BACKPLANE:
128ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E810C_QSFP:
129ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E810C_SFP:
1307dcf78b8STony Nguyen case ICE_DEV_ID_E810_XXV_BACKPLANE:
1317dcf78b8STony Nguyen case ICE_DEV_ID_E810_XXV_QSFP:
132ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E810_XXV_SFP:
133ea78ce4dSPaul Greenwalt hw->mac_type = ICE_MAC_E810;
134ea78ce4dSPaul Greenwalt break;
135ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_10G_BASE_T:
136ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_BACKPLANE:
137ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_QSFP:
138ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_SFP:
139ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_SGMII:
140ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_10G_BASE_T:
141ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_BACKPLANE:
142ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_QSFP:
143ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_SFP:
144ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_SGMII:
145ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822L_10G_BASE_T:
146ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822L_BACKPLANE:
147ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822L_SFP:
148ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822L_SGMII:
149ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_10G_BASE_T:
150ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_1GBE:
151ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_BACKPLANE:
152ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_QSFP:
153ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_SFP:
154f31e4b6fSAnirudh Venkataramanan hw->mac_type = ICE_MAC_GENERIC;
155ea78ce4dSPaul Greenwalt break;
156ea78ce4dSPaul Greenwalt default:
157ea78ce4dSPaul Greenwalt hw->mac_type = ICE_MAC_UNKNOWN;
158ea78ce4dSPaul Greenwalt break;
159ea78ce4dSPaul Greenwalt }
160ea78ce4dSPaul Greenwalt
161ea78ce4dSPaul Greenwalt ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
162f31e4b6fSAnirudh Venkataramanan return 0;
163f31e4b6fSAnirudh Venkataramanan }
164f31e4b6fSAnirudh Venkataramanan
165f31e4b6fSAnirudh Venkataramanan /**
16606c16d89SJacob Keller * ice_is_e810
16706c16d89SJacob Keller * @hw: pointer to the hardware structure
16806c16d89SJacob Keller *
16906c16d89SJacob Keller * returns true if the device is E810 based, false if not.
17006c16d89SJacob Keller */
ice_is_e810(struct ice_hw * hw)17106c16d89SJacob Keller bool ice_is_e810(struct ice_hw *hw)
17206c16d89SJacob Keller {
17306c16d89SJacob Keller return hw->mac_type == ICE_MAC_E810;
17406c16d89SJacob Keller }
17506c16d89SJacob Keller
17606c16d89SJacob Keller /**
177885fe693SMaciej Machnikowski * ice_is_e810t
178885fe693SMaciej Machnikowski * @hw: pointer to the hardware structure
179885fe693SMaciej Machnikowski *
180885fe693SMaciej Machnikowski * returns true if the device is E810T based, false if not.
181885fe693SMaciej Machnikowski */
ice_is_e810t(struct ice_hw * hw)182885fe693SMaciej Machnikowski bool ice_is_e810t(struct ice_hw *hw)
183885fe693SMaciej Machnikowski {
184885fe693SMaciej Machnikowski switch (hw->device_id) {
185885fe693SMaciej Machnikowski case ICE_DEV_ID_E810C_SFP:
186793189a2SArkadiusz Kubalewski switch (hw->subsystem_device_id) {
187793189a2SArkadiusz Kubalewski case ICE_SUBDEV_ID_E810T:
188793189a2SArkadiusz Kubalewski case ICE_SUBDEV_ID_E810T2:
189793189a2SArkadiusz Kubalewski case ICE_SUBDEV_ID_E810T3:
190793189a2SArkadiusz Kubalewski case ICE_SUBDEV_ID_E810T4:
191793189a2SArkadiusz Kubalewski case ICE_SUBDEV_ID_E810T6:
192793189a2SArkadiusz Kubalewski case ICE_SUBDEV_ID_E810T7:
193885fe693SMaciej Machnikowski return true;
194793189a2SArkadiusz Kubalewski }
195793189a2SArkadiusz Kubalewski break;
196793189a2SArkadiusz Kubalewski case ICE_DEV_ID_E810C_QSFP:
197793189a2SArkadiusz Kubalewski switch (hw->subsystem_device_id) {
198793189a2SArkadiusz Kubalewski case ICE_SUBDEV_ID_E810T2:
199793189a2SArkadiusz Kubalewski case ICE_SUBDEV_ID_E810T3:
200793189a2SArkadiusz Kubalewski case ICE_SUBDEV_ID_E810T5:
201793189a2SArkadiusz Kubalewski return true;
202793189a2SArkadiusz Kubalewski }
203885fe693SMaciej Machnikowski break;
204885fe693SMaciej Machnikowski default:
205885fe693SMaciej Machnikowski break;
206885fe693SMaciej Machnikowski }
207885fe693SMaciej Machnikowski
208885fe693SMaciej Machnikowski return false;
209885fe693SMaciej Machnikowski }
210885fe693SMaciej Machnikowski
211885fe693SMaciej Machnikowski /**
212634d841dSKarol Kolacinski * ice_is_e823
213634d841dSKarol Kolacinski * @hw: pointer to the hardware structure
214634d841dSKarol Kolacinski *
215634d841dSKarol Kolacinski * returns true if the device is E823-L or E823-C based, false if not.
216634d841dSKarol Kolacinski */
ice_is_e823(struct ice_hw * hw)217634d841dSKarol Kolacinski bool ice_is_e823(struct ice_hw *hw)
218634d841dSKarol Kolacinski {
219634d841dSKarol Kolacinski switch (hw->device_id) {
220634d841dSKarol Kolacinski case ICE_DEV_ID_E823L_BACKPLANE:
221634d841dSKarol Kolacinski case ICE_DEV_ID_E823L_SFP:
222634d841dSKarol Kolacinski case ICE_DEV_ID_E823L_10G_BASE_T:
223634d841dSKarol Kolacinski case ICE_DEV_ID_E823L_1GBE:
224634d841dSKarol Kolacinski case ICE_DEV_ID_E823L_QSFP:
225634d841dSKarol Kolacinski case ICE_DEV_ID_E823C_BACKPLANE:
226634d841dSKarol Kolacinski case ICE_DEV_ID_E823C_QSFP:
227634d841dSKarol Kolacinski case ICE_DEV_ID_E823C_SFP:
228634d841dSKarol Kolacinski case ICE_DEV_ID_E823C_10G_BASE_T:
229634d841dSKarol Kolacinski case ICE_DEV_ID_E823C_SGMII:
230634d841dSKarol Kolacinski return true;
231634d841dSKarol Kolacinski default:
232634d841dSKarol Kolacinski return false;
233634d841dSKarol Kolacinski }
234634d841dSKarol Kolacinski }
235634d841dSKarol Kolacinski
236634d841dSKarol Kolacinski /**
237f31e4b6fSAnirudh Venkataramanan * ice_clear_pf_cfg - Clear PF configuration
238f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure
2393968540bSAnirudh Venkataramanan *
2403968540bSAnirudh Venkataramanan * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
2413968540bSAnirudh Venkataramanan * configuration, flow director filters, etc.).
242f31e4b6fSAnirudh Venkataramanan */
ice_clear_pf_cfg(struct ice_hw * hw)2435e24d598STony Nguyen int ice_clear_pf_cfg(struct ice_hw *hw)
244f31e4b6fSAnirudh Venkataramanan {
245f31e4b6fSAnirudh Venkataramanan struct ice_aq_desc desc;
246f31e4b6fSAnirudh Venkataramanan
247f31e4b6fSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
248f31e4b6fSAnirudh Venkataramanan
249f31e4b6fSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
250f31e4b6fSAnirudh Venkataramanan }
251f31e4b6fSAnirudh Venkataramanan
252f31e4b6fSAnirudh Venkataramanan /**
253dc49c772SAnirudh Venkataramanan * ice_aq_manage_mac_read - manage MAC address read command
254f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
255dc49c772SAnirudh Venkataramanan * @buf: a virtual buffer to hold the manage MAC read response
256dc49c772SAnirudh Venkataramanan * @buf_size: Size of the virtual buffer
257dc49c772SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
258dc49c772SAnirudh Venkataramanan *
259dc49c772SAnirudh Venkataramanan * This function is used to return per PF station MAC address (0x0107).
260dc49c772SAnirudh Venkataramanan * NOTE: Upon successful completion of this command, MAC address information
261dc49c772SAnirudh Venkataramanan * is returned in user specified buffer. Please interpret user specified
262dc49c772SAnirudh Venkataramanan * buffer as "manage_mac_read" response.
263dc49c772SAnirudh Venkataramanan * Response such as various MAC addresses are stored in HW struct (port.mac)
26481aed647SJacob Keller * ice_discover_dev_caps is expected to be called before this function is
26581aed647SJacob Keller * called.
266dc49c772SAnirudh Venkataramanan */
2675e24d598STony Nguyen static int
ice_aq_manage_mac_read(struct ice_hw * hw,void * buf,u16 buf_size,struct ice_sq_cd * cd)268dc49c772SAnirudh Venkataramanan ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
269dc49c772SAnirudh Venkataramanan struct ice_sq_cd *cd)
270dc49c772SAnirudh Venkataramanan {
271dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read_resp *resp;
272dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read *cmd;
273dc49c772SAnirudh Venkataramanan struct ice_aq_desc desc;
2745e24d598STony Nguyen int status;
275dc49c772SAnirudh Venkataramanan u16 flags;
276d6fef10cSMd Fahad Iqbal Polash u8 i;
277dc49c772SAnirudh Venkataramanan
278dc49c772SAnirudh Venkataramanan cmd = &desc.params.mac_read;
279dc49c772SAnirudh Venkataramanan
280dc49c772SAnirudh Venkataramanan if (buf_size < sizeof(*resp))
281d54699e2STony Nguyen return -EINVAL;
282dc49c772SAnirudh Venkataramanan
283dc49c772SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
284dc49c772SAnirudh Venkataramanan
285dc49c772SAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
286dc49c772SAnirudh Venkataramanan if (status)
287dc49c772SAnirudh Venkataramanan return status;
288dc49c772SAnirudh Venkataramanan
2897a63dae0SBruce Allan resp = buf;
290dc49c772SAnirudh Venkataramanan flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
291dc49c772SAnirudh Venkataramanan
292dc49c772SAnirudh Venkataramanan if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
293dc49c772SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
294d54699e2STony Nguyen return -EIO;
295dc49c772SAnirudh Venkataramanan }
296dc49c772SAnirudh Venkataramanan
297d6fef10cSMd Fahad Iqbal Polash /* A single port can report up to two (LAN and WoL) addresses */
298d6fef10cSMd Fahad Iqbal Polash for (i = 0; i < cmd->num_addr; i++)
299d6fef10cSMd Fahad Iqbal Polash if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
300d6fef10cSMd Fahad Iqbal Polash ether_addr_copy(hw->port_info->mac.lan_addr,
301d6fef10cSMd Fahad Iqbal Polash resp[i].mac_addr);
302d6fef10cSMd Fahad Iqbal Polash ether_addr_copy(hw->port_info->mac.perm_addr,
303d6fef10cSMd Fahad Iqbal Polash resp[i].mac_addr);
304d6fef10cSMd Fahad Iqbal Polash break;
305d6fef10cSMd Fahad Iqbal Polash }
306d6fef10cSMd Fahad Iqbal Polash
307dc49c772SAnirudh Venkataramanan return 0;
308dc49c772SAnirudh Venkataramanan }
309dc49c772SAnirudh Venkataramanan
310dc49c772SAnirudh Venkataramanan /**
311dc49c772SAnirudh Venkataramanan * ice_aq_get_phy_caps - returns PHY capabilities
312dc49c772SAnirudh Venkataramanan * @pi: port information structure
313dc49c772SAnirudh Venkataramanan * @qual_mods: report qualified modules
314dc49c772SAnirudh Venkataramanan * @report_mode: report mode capabilities
315dc49c772SAnirudh Venkataramanan * @pcaps: structure for PHY capabilities to be filled
316dc49c772SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
317dc49c772SAnirudh Venkataramanan *
318dc49c772SAnirudh Venkataramanan * Returns the various PHY capabilities supported on the Port (0x0600)
319dc49c772SAnirudh Venkataramanan */
3205e24d598STony Nguyen int
ice_aq_get_phy_caps(struct ice_port_info * pi,bool qual_mods,u8 report_mode,struct ice_aqc_get_phy_caps_data * pcaps,struct ice_sq_cd * cd)321dc49c772SAnirudh Venkataramanan ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
322dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps_data *pcaps,
323dc49c772SAnirudh Venkataramanan struct ice_sq_cd *cd)
324dc49c772SAnirudh Venkataramanan {
325dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps *cmd;
326dc49c772SAnirudh Venkataramanan u16 pcaps_size = sizeof(*pcaps);
327dc49c772SAnirudh Venkataramanan struct ice_aq_desc desc;
328f8c74ca6SAnirudh Venkataramanan const char *prefix;
32955df52a0SPaul Greenwalt struct ice_hw *hw;
3305518ac2aSTony Nguyen int status;
331dc49c772SAnirudh Venkataramanan
332dc49c772SAnirudh Venkataramanan cmd = &desc.params.get_phy;
333dc49c772SAnirudh Venkataramanan
334dc49c772SAnirudh Venkataramanan if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
335d54699e2STony Nguyen return -EINVAL;
33655df52a0SPaul Greenwalt hw = pi->hw;
337dc49c772SAnirudh Venkataramanan
3380a02944fSAnirudh Venkataramanan if (report_mode == ICE_AQC_REPORT_DFLT_CFG &&
3390a02944fSAnirudh Venkataramanan !ice_fw_supports_report_dflt_cfg(hw))
340d54699e2STony Nguyen return -EINVAL;
3410a02944fSAnirudh Venkataramanan
342dc49c772SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
343dc49c772SAnirudh Venkataramanan
344dc49c772SAnirudh Venkataramanan if (qual_mods)
345dc49c772SAnirudh Venkataramanan cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM);
346dc49c772SAnirudh Venkataramanan
347dc49c772SAnirudh Venkataramanan cmd->param0 |= cpu_to_le16(report_mode);
34855df52a0SPaul Greenwalt status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
34955df52a0SPaul Greenwalt
350f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n");
351f8c74ca6SAnirudh Venkataramanan
352f8c74ca6SAnirudh Venkataramanan switch (report_mode) {
353f8c74ca6SAnirudh Venkataramanan case ICE_AQC_REPORT_TOPO_CAP_MEDIA:
354f8c74ca6SAnirudh Venkataramanan prefix = "phy_caps_media";
355f8c74ca6SAnirudh Venkataramanan break;
356f8c74ca6SAnirudh Venkataramanan case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA:
357f8c74ca6SAnirudh Venkataramanan prefix = "phy_caps_no_media";
358f8c74ca6SAnirudh Venkataramanan break;
359f8c74ca6SAnirudh Venkataramanan case ICE_AQC_REPORT_ACTIVE_CFG:
360f8c74ca6SAnirudh Venkataramanan prefix = "phy_caps_active";
361f8c74ca6SAnirudh Venkataramanan break;
362f8c74ca6SAnirudh Venkataramanan case ICE_AQC_REPORT_DFLT_CFG:
363f8c74ca6SAnirudh Venkataramanan prefix = "phy_caps_default";
364f8c74ca6SAnirudh Venkataramanan break;
365f8c74ca6SAnirudh Venkataramanan default:
366f8c74ca6SAnirudh Venkataramanan prefix = "phy_caps_invalid";
367f8c74ca6SAnirudh Venkataramanan }
368f8c74ca6SAnirudh Venkataramanan
369f8c74ca6SAnirudh Venkataramanan ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low),
370f8c74ca6SAnirudh Venkataramanan le64_to_cpu(pcaps->phy_type_high), prefix);
371f8c74ca6SAnirudh Venkataramanan
372f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n",
373f8c74ca6SAnirudh Venkataramanan prefix, report_mode);
374f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps);
375f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix,
376bdeff971SLev Faerman pcaps->low_power_ctrl_an);
377f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix,
378f8c74ca6SAnirudh Venkataramanan pcaps->eee_cap);
379f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix,
38055df52a0SPaul Greenwalt pcaps->eeer_value);
381f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix,
38255df52a0SPaul Greenwalt pcaps->link_fec_options);
383f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n",
384f8c74ca6SAnirudh Venkataramanan prefix, pcaps->module_compliance_enforcement);
385f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n",
386f8c74ca6SAnirudh Venkataramanan prefix, pcaps->extended_compliance_code);
387f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix,
38855df52a0SPaul Greenwalt pcaps->module_type[0]);
389f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix,
39055df52a0SPaul Greenwalt pcaps->module_type[1]);
391f8c74ca6SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix,
39255df52a0SPaul Greenwalt pcaps->module_type[2]);
393dc49c772SAnirudh Venkataramanan
394d6730a87SAnirudh Venkataramanan if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
395dc49c772SAnirudh Venkataramanan pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low);
396aef74145SAnirudh Venkataramanan pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high);
397c2b35226SPaul M Stillwell Jr memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
398c2b35226SPaul M Stillwell Jr sizeof(pi->phy.link_info.module_type));
399aef74145SAnirudh Venkataramanan }
400dc49c772SAnirudh Venkataramanan
401dc49c772SAnirudh Venkataramanan return status;
402dc49c772SAnirudh Venkataramanan }
403dc49c772SAnirudh Venkataramanan
404dc49c772SAnirudh Venkataramanan /**
4058ea1da59SPaul Greenwalt * ice_aq_get_link_topo_handle - get link topology node return status
4068ea1da59SPaul Greenwalt * @pi: port information structure
4078ea1da59SPaul Greenwalt * @node_type: requested node type
4088ea1da59SPaul Greenwalt * @cd: pointer to command details structure or NULL
4098ea1da59SPaul Greenwalt *
4108ea1da59SPaul Greenwalt * Get link topology node return status for specified node type (0x06E0)
4118ea1da59SPaul Greenwalt *
4128ea1da59SPaul Greenwalt * Node type cage can be used to determine if cage is present. If AQC
4138ea1da59SPaul Greenwalt * returns error (ENOENT), then no cage present. If no cage present, then
4148ea1da59SPaul Greenwalt * connection type is backplane or BASE-T.
4158ea1da59SPaul Greenwalt */
4165e24d598STony Nguyen static int
ice_aq_get_link_topo_handle(struct ice_port_info * pi,u8 node_type,struct ice_sq_cd * cd)4178ea1da59SPaul Greenwalt ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
4188ea1da59SPaul Greenwalt struct ice_sq_cd *cd)
4198ea1da59SPaul Greenwalt {
4208ea1da59SPaul Greenwalt struct ice_aqc_get_link_topo *cmd;
4218ea1da59SPaul Greenwalt struct ice_aq_desc desc;
4228ea1da59SPaul Greenwalt
4238ea1da59SPaul Greenwalt cmd = &desc.params.get_link_topo;
4248ea1da59SPaul Greenwalt
4258ea1da59SPaul Greenwalt ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
4268ea1da59SPaul Greenwalt
427e00ae1a2SMaciej Machnikowski cmd->addr.topo_params.node_type_ctx =
428e00ae1a2SMaciej Machnikowski (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
4298ea1da59SPaul Greenwalt ICE_AQC_LINK_TOPO_NODE_CTX_S);
4308ea1da59SPaul Greenwalt
4318ea1da59SPaul Greenwalt /* set node type */
432e00ae1a2SMaciej Machnikowski cmd->addr.topo_params.node_type_ctx |=
433e00ae1a2SMaciej Machnikowski (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
4348ea1da59SPaul Greenwalt
4358ea1da59SPaul Greenwalt return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
4368ea1da59SPaul Greenwalt }
4378ea1da59SPaul Greenwalt
4388ea1da59SPaul Greenwalt /**
4398ea1da59SPaul Greenwalt * ice_is_media_cage_present
4408ea1da59SPaul Greenwalt * @pi: port information structure
4418ea1da59SPaul Greenwalt *
4428ea1da59SPaul Greenwalt * Returns true if media cage is present, else false. If no cage, then
4438ea1da59SPaul Greenwalt * media type is backplane or BASE-T.
4448ea1da59SPaul Greenwalt */
ice_is_media_cage_present(struct ice_port_info * pi)4458ea1da59SPaul Greenwalt static bool ice_is_media_cage_present(struct ice_port_info *pi)
4468ea1da59SPaul Greenwalt {
4478ea1da59SPaul Greenwalt /* Node type cage can be used to determine if cage is present. If AQC
4488ea1da59SPaul Greenwalt * returns error (ENOENT), then no cage present. If no cage present then
4498ea1da59SPaul Greenwalt * connection type is backplane or BASE-T.
4508ea1da59SPaul Greenwalt */
4518ea1da59SPaul Greenwalt return !ice_aq_get_link_topo_handle(pi,
4528ea1da59SPaul Greenwalt ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
4538ea1da59SPaul Greenwalt NULL);
4548ea1da59SPaul Greenwalt }
4558ea1da59SPaul Greenwalt
4568ea1da59SPaul Greenwalt /**
457dc49c772SAnirudh Venkataramanan * ice_get_media_type - Gets media type
458dc49c772SAnirudh Venkataramanan * @pi: port information structure
459dc49c772SAnirudh Venkataramanan */
ice_get_media_type(struct ice_port_info * pi)460dc49c772SAnirudh Venkataramanan static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
461dc49c772SAnirudh Venkataramanan {
462dc49c772SAnirudh Venkataramanan struct ice_link_status *hw_link_info;
463dc49c772SAnirudh Venkataramanan
464dc49c772SAnirudh Venkataramanan if (!pi)
465dc49c772SAnirudh Venkataramanan return ICE_MEDIA_UNKNOWN;
466dc49c772SAnirudh Venkataramanan
467dc49c772SAnirudh Venkataramanan hw_link_info = &pi->phy.link_info;
468aef74145SAnirudh Venkataramanan if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
469aef74145SAnirudh Venkataramanan /* If more than one media type is selected, report unknown */
470aef74145SAnirudh Venkataramanan return ICE_MEDIA_UNKNOWN;
471dc49c772SAnirudh Venkataramanan
472dc49c772SAnirudh Venkataramanan if (hw_link_info->phy_type_low) {
473c2b35226SPaul M Stillwell Jr /* 1G SGMII is a special case where some DA cable PHYs
474c2b35226SPaul M Stillwell Jr * may show this as an option when it really shouldn't
475c2b35226SPaul M Stillwell Jr * be since SGMII is meant to be between a MAC and a PHY
476c2b35226SPaul M Stillwell Jr * in a backplane. Try to detect this case and handle it
477c2b35226SPaul M Stillwell Jr */
478c2b35226SPaul M Stillwell Jr if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
479c2b35226SPaul M Stillwell Jr (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
480c2b35226SPaul M Stillwell Jr ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
481c2b35226SPaul M Stillwell Jr hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
482c2b35226SPaul M Stillwell Jr ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
483c2b35226SPaul M Stillwell Jr return ICE_MEDIA_DA;
484c2b35226SPaul M Stillwell Jr
485dc49c772SAnirudh Venkataramanan switch (hw_link_info->phy_type_low) {
486dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_1000BASE_SX:
487dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_1000BASE_LX:
488dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10GBASE_SR:
489dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10GBASE_LR:
490dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
491dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_SR:
492dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_LR:
493dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_40GBASE_SR4:
494dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_40GBASE_LR4:
495aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_SR2:
496aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_LR2:
497aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_SR:
498aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_FR:
499aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_LR:
500aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_SR4:
501aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_LR4:
502aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_SR2:
503aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_DR:
504c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
505c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
506c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
507c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
508c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
509c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
510c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
511c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
512dc49c772SAnirudh Venkataramanan return ICE_MEDIA_FIBER;
513dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100BASE_TX:
514dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_1000BASE_T:
515dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_2500BASE_T:
516dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_5GBASE_T:
517dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10GBASE_T:
518dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_T:
519dc49c772SAnirudh Venkataramanan return ICE_MEDIA_BASET;
520dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10G_SFI_DA:
521dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_CR:
522dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
523dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_CR1:
524dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_40GBASE_CR4:
525aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_CR2:
526aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_CP:
527aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CR4:
528aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
529aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CP2:
530dc49c772SAnirudh Venkataramanan return ICE_MEDIA_DA;
5318ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
5328ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_40G_XLAUI:
5338ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_50G_LAUI2:
5348ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_50G_AUI2:
5358ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_50G_AUI1:
5368ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_100G_AUI4:
5378ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_100G_CAUI4:
5388ea1da59SPaul Greenwalt if (ice_is_media_cage_present(pi))
5398ea1da59SPaul Greenwalt return ICE_MEDIA_DA;
5408ea1da59SPaul Greenwalt fallthrough;
541dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_1000BASE_KX:
542dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_2500BASE_KX:
543dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_2500BASE_X:
544dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_5GBASE_KR:
545dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
546dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_KR:
547dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_KR1:
548dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
549dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_40GBASE_KR4:
550aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
551aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_KR2:
552aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_KR4:
553aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
554aef74145SAnirudh Venkataramanan return ICE_MEDIA_BACKPLANE;
555aef74145SAnirudh Venkataramanan }
556aef74145SAnirudh Venkataramanan } else {
557aef74145SAnirudh Venkataramanan switch (hw_link_info->phy_type_high) {
5588ea1da59SPaul Greenwalt case ICE_PHY_TYPE_HIGH_100G_AUI2:
5598ea1da59SPaul Greenwalt case ICE_PHY_TYPE_HIGH_100G_CAUI2:
5608ea1da59SPaul Greenwalt if (ice_is_media_cage_present(pi))
5618ea1da59SPaul Greenwalt return ICE_MEDIA_DA;
5628ea1da59SPaul Greenwalt fallthrough;
563aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
564dc49c772SAnirudh Venkataramanan return ICE_MEDIA_BACKPLANE;
565c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
566c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
567c1eb3b6bSDoug Dziggel return ICE_MEDIA_FIBER;
568dc49c772SAnirudh Venkataramanan }
569dc49c772SAnirudh Venkataramanan }
570dc49c772SAnirudh Venkataramanan return ICE_MEDIA_UNKNOWN;
571dc49c772SAnirudh Venkataramanan }
572dc49c772SAnirudh Venkataramanan
573dc49c772SAnirudh Venkataramanan /**
574dc49c772SAnirudh Venkataramanan * ice_aq_get_link_info
575dc49c772SAnirudh Venkataramanan * @pi: port information structure
576dc49c772SAnirudh Venkataramanan * @ena_lse: enable/disable LinkStatusEvent reporting
577dc49c772SAnirudh Venkataramanan * @link: pointer to link status structure - optional
578dc49c772SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
579dc49c772SAnirudh Venkataramanan *
580dc49c772SAnirudh Venkataramanan * Get Link Status (0x607). Returns the link status of the adapter.
581dc49c772SAnirudh Venkataramanan */
5825e24d598STony Nguyen int
ice_aq_get_link_info(struct ice_port_info * pi,bool ena_lse,struct ice_link_status * link,struct ice_sq_cd * cd)583dc49c772SAnirudh Venkataramanan ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
584dc49c772SAnirudh Venkataramanan struct ice_link_status *link, struct ice_sq_cd *cd)
585dc49c772SAnirudh Venkataramanan {
586dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status_data link_data = { 0 };
587dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status *resp;
588dc67039bSJesse Brandeburg struct ice_link_status *li_old, *li;
589dc49c772SAnirudh Venkataramanan enum ice_media_type *hw_media_type;
590dc49c772SAnirudh Venkataramanan struct ice_fc_info *hw_fc_info;
591dc49c772SAnirudh Venkataramanan bool tx_pause, rx_pause;
592dc49c772SAnirudh Venkataramanan struct ice_aq_desc desc;
593dc67039bSJesse Brandeburg struct ice_hw *hw;
594dc49c772SAnirudh Venkataramanan u16 cmd_flags;
5955518ac2aSTony Nguyen int status;
596dc49c772SAnirudh Venkataramanan
597dc49c772SAnirudh Venkataramanan if (!pi)
598d54699e2STony Nguyen return -EINVAL;
599dc67039bSJesse Brandeburg hw = pi->hw;
600dc67039bSJesse Brandeburg li_old = &pi->phy.link_info_old;
601dc49c772SAnirudh Venkataramanan hw_media_type = &pi->phy.media_type;
602dc67039bSJesse Brandeburg li = &pi->phy.link_info;
603dc49c772SAnirudh Venkataramanan hw_fc_info = &pi->fc;
604dc49c772SAnirudh Venkataramanan
605dc49c772SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
606dc49c772SAnirudh Venkataramanan cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
607dc49c772SAnirudh Venkataramanan resp = &desc.params.get_link_status;
608dc49c772SAnirudh Venkataramanan resp->cmd_flags = cpu_to_le16(cmd_flags);
609dc49c772SAnirudh Venkataramanan resp->lport_num = pi->lport;
610dc49c772SAnirudh Venkataramanan
611dc67039bSJesse Brandeburg status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
612dc49c772SAnirudh Venkataramanan
613dc49c772SAnirudh Venkataramanan if (status)
614dc49c772SAnirudh Venkataramanan return status;
615dc49c772SAnirudh Venkataramanan
616dc49c772SAnirudh Venkataramanan /* save off old link status information */
617dc67039bSJesse Brandeburg *li_old = *li;
618dc49c772SAnirudh Venkataramanan
619dc49c772SAnirudh Venkataramanan /* update current link status information */
620dc67039bSJesse Brandeburg li->link_speed = le16_to_cpu(link_data.link_speed);
621dc67039bSJesse Brandeburg li->phy_type_low = le64_to_cpu(link_data.phy_type_low);
622dc67039bSJesse Brandeburg li->phy_type_high = le64_to_cpu(link_data.phy_type_high);
623dc49c772SAnirudh Venkataramanan *hw_media_type = ice_get_media_type(pi);
624dc67039bSJesse Brandeburg li->link_info = link_data.link_info;
625c77849f5SAnirudh Venkataramanan li->link_cfg_err = link_data.link_cfg_err;
626dc67039bSJesse Brandeburg li->an_info = link_data.an_info;
627dc67039bSJesse Brandeburg li->ext_info = link_data.ext_info;
628dc67039bSJesse Brandeburg li->max_frame_size = le16_to_cpu(link_data.max_frame_size);
629dc67039bSJesse Brandeburg li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
630dc67039bSJesse Brandeburg li->topo_media_conflict = link_data.topo_media_conflict;
631dc67039bSJesse Brandeburg li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
632dc67039bSJesse Brandeburg ICE_AQ_CFG_PACING_TYPE_M);
633dc49c772SAnirudh Venkataramanan
634dc49c772SAnirudh Venkataramanan /* update fc info */
635dc49c772SAnirudh Venkataramanan tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
636dc49c772SAnirudh Venkataramanan rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
637dc49c772SAnirudh Venkataramanan if (tx_pause && rx_pause)
638dc49c772SAnirudh Venkataramanan hw_fc_info->current_mode = ICE_FC_FULL;
639dc49c772SAnirudh Venkataramanan else if (tx_pause)
640dc49c772SAnirudh Venkataramanan hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
641dc49c772SAnirudh Venkataramanan else if (rx_pause)
642dc49c772SAnirudh Venkataramanan hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
643dc49c772SAnirudh Venkataramanan else
644dc49c772SAnirudh Venkataramanan hw_fc_info->current_mode = ICE_FC_NONE;
645dc49c772SAnirudh Venkataramanan
646dc67039bSJesse Brandeburg li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED));
647dc67039bSJesse Brandeburg
64855df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, "get link info\n");
649dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
650dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
651dc67039bSJesse Brandeburg (unsigned long long)li->phy_type_low);
652dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
653dc67039bSJesse Brandeburg (unsigned long long)li->phy_type_high);
654dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
655dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
656c77849f5SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err);
657dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
658dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
65955df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
660dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
66155df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
66255df52a0SPaul Greenwalt li->max_frame_size);
663dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
664dc49c772SAnirudh Venkataramanan
665dc49c772SAnirudh Venkataramanan /* save link status information */
666dc49c772SAnirudh Venkataramanan if (link)
667dc67039bSJesse Brandeburg *link = *li;
668dc49c772SAnirudh Venkataramanan
669dc49c772SAnirudh Venkataramanan /* flag cleared so calling functions don't call AQ again */
670dc49c772SAnirudh Venkataramanan pi->phy.get_link_info = false;
671dc49c772SAnirudh Venkataramanan
6721b5c19c7SBruce Allan return 0;
673dc49c772SAnirudh Venkataramanan }
674dc49c772SAnirudh Venkataramanan
675dc49c772SAnirudh Venkataramanan /**
67642449105SAnirudh Venkataramanan * ice_fill_tx_timer_and_fc_thresh
67742449105SAnirudh Venkataramanan * @hw: pointer to the HW struct
67842449105SAnirudh Venkataramanan * @cmd: pointer to MAC cfg structure
67942449105SAnirudh Venkataramanan *
68042449105SAnirudh Venkataramanan * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
68142449105SAnirudh Venkataramanan * descriptor
68242449105SAnirudh Venkataramanan */
68342449105SAnirudh Venkataramanan static void
ice_fill_tx_timer_and_fc_thresh(struct ice_hw * hw,struct ice_aqc_set_mac_cfg * cmd)68442449105SAnirudh Venkataramanan ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
68542449105SAnirudh Venkataramanan struct ice_aqc_set_mac_cfg *cmd)
68642449105SAnirudh Venkataramanan {
68742449105SAnirudh Venkataramanan u16 fc_thres_val, tx_timer_val;
68842449105SAnirudh Venkataramanan u32 val;
68942449105SAnirudh Venkataramanan
69042449105SAnirudh Venkataramanan /* We read back the transmit timer and FC threshold value of
69142449105SAnirudh Venkataramanan * LFC. Thus, we will use index =
69242449105SAnirudh Venkataramanan * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
69342449105SAnirudh Venkataramanan *
69442449105SAnirudh Venkataramanan * Also, because we are operating on transmit timer and FC
69542449105SAnirudh Venkataramanan * threshold of LFC, we don't turn on any bit in tx_tmr_priority
69642449105SAnirudh Venkataramanan */
69742449105SAnirudh Venkataramanan #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
69842449105SAnirudh Venkataramanan
69942449105SAnirudh Venkataramanan /* Retrieve the transmit timer */
70042449105SAnirudh Venkataramanan val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
70142449105SAnirudh Venkataramanan tx_timer_val = val &
70242449105SAnirudh Venkataramanan PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
70342449105SAnirudh Venkataramanan cmd->tx_tmr_value = cpu_to_le16(tx_timer_val);
70442449105SAnirudh Venkataramanan
70542449105SAnirudh Venkataramanan /* Retrieve the FC threshold */
70642449105SAnirudh Venkataramanan val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
70742449105SAnirudh Venkataramanan fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
70842449105SAnirudh Venkataramanan
70942449105SAnirudh Venkataramanan cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val);
71042449105SAnirudh Venkataramanan }
71142449105SAnirudh Venkataramanan
71242449105SAnirudh Venkataramanan /**
71342449105SAnirudh Venkataramanan * ice_aq_set_mac_cfg
71442449105SAnirudh Venkataramanan * @hw: pointer to the HW struct
71542449105SAnirudh Venkataramanan * @max_frame_size: Maximum Frame Size to be supported
71642449105SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
71742449105SAnirudh Venkataramanan *
71842449105SAnirudh Venkataramanan * Set MAC configuration (0x0603)
71942449105SAnirudh Venkataramanan */
7205e24d598STony Nguyen int
ice_aq_set_mac_cfg(struct ice_hw * hw,u16 max_frame_size,struct ice_sq_cd * cd)72142449105SAnirudh Venkataramanan ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
72242449105SAnirudh Venkataramanan {
72342449105SAnirudh Venkataramanan struct ice_aqc_set_mac_cfg *cmd;
72442449105SAnirudh Venkataramanan struct ice_aq_desc desc;
72542449105SAnirudh Venkataramanan
72642449105SAnirudh Venkataramanan cmd = &desc.params.set_mac_cfg;
72742449105SAnirudh Venkataramanan
72842449105SAnirudh Venkataramanan if (max_frame_size == 0)
729d54699e2STony Nguyen return -EINVAL;
73042449105SAnirudh Venkataramanan
73142449105SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
73242449105SAnirudh Venkataramanan
73342449105SAnirudh Venkataramanan cmd->max_frame_size = cpu_to_le16(max_frame_size);
73442449105SAnirudh Venkataramanan
73542449105SAnirudh Venkataramanan ice_fill_tx_timer_and_fc_thresh(hw, cmd);
73642449105SAnirudh Venkataramanan
73742449105SAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
73842449105SAnirudh Venkataramanan }
73942449105SAnirudh Venkataramanan
74042449105SAnirudh Venkataramanan /**
7419daf8208SAnirudh Venkataramanan * ice_init_fltr_mgmt_struct - initializes filter management list and locks
742f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
7439daf8208SAnirudh Venkataramanan */
ice_init_fltr_mgmt_struct(struct ice_hw * hw)7445e24d598STony Nguyen static int ice_init_fltr_mgmt_struct(struct ice_hw *hw)
7459daf8208SAnirudh Venkataramanan {
7469daf8208SAnirudh Venkataramanan struct ice_switch_info *sw;
7475e24d598STony Nguyen int status;
7489daf8208SAnirudh Venkataramanan
7499daf8208SAnirudh Venkataramanan hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw),
7509daf8208SAnirudh Venkataramanan sizeof(*hw->switch_info), GFP_KERNEL);
7519daf8208SAnirudh Venkataramanan sw = hw->switch_info;
7529daf8208SAnirudh Venkataramanan
7539daf8208SAnirudh Venkataramanan if (!sw)
754d54699e2STony Nguyen return -ENOMEM;
7559daf8208SAnirudh Venkataramanan
7569daf8208SAnirudh Venkataramanan INIT_LIST_HEAD(&sw->vsi_list_map_head);
7570f94570dSGrishma Kotecha sw->prof_res_bm_init = 0;
7589daf8208SAnirudh Venkataramanan
7591aaef2bcSSurabhi Boob status = ice_init_def_sw_recp(hw);
7601aaef2bcSSurabhi Boob if (status) {
7611aaef2bcSSurabhi Boob devm_kfree(ice_hw_to_dev(hw), hw->switch_info);
7621aaef2bcSSurabhi Boob return status;
7631aaef2bcSSurabhi Boob }
7641aaef2bcSSurabhi Boob return 0;
7659daf8208SAnirudh Venkataramanan }
7669daf8208SAnirudh Venkataramanan
7679daf8208SAnirudh Venkataramanan /**
7689daf8208SAnirudh Venkataramanan * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
769f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
7709daf8208SAnirudh Venkataramanan */
ice_cleanup_fltr_mgmt_struct(struct ice_hw * hw)7719daf8208SAnirudh Venkataramanan static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
7729daf8208SAnirudh Venkataramanan {
7739daf8208SAnirudh Venkataramanan struct ice_switch_info *sw = hw->switch_info;
7749daf8208SAnirudh Venkataramanan struct ice_vsi_list_map_info *v_pos_map;
7759daf8208SAnirudh Venkataramanan struct ice_vsi_list_map_info *v_tmp_map;
77680d144c9SAnirudh Venkataramanan struct ice_sw_recipe *recps;
77780d144c9SAnirudh Venkataramanan u8 i;
7789daf8208SAnirudh Venkataramanan
7799daf8208SAnirudh Venkataramanan list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
7809daf8208SAnirudh Venkataramanan list_entry) {
7819daf8208SAnirudh Venkataramanan list_del(&v_pos_map->list_entry);
7829daf8208SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), v_pos_map);
7839daf8208SAnirudh Venkataramanan }
7848b8ef05bSVictor Raj recps = sw->recp_list;
7858b8ef05bSVictor Raj for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
7868b8ef05bSVictor Raj struct ice_recp_grp_entry *rg_entry, *tmprg_entry;
7879daf8208SAnirudh Venkataramanan
78880d144c9SAnirudh Venkataramanan recps[i].root_rid = i;
7898b8ef05bSVictor Raj list_for_each_entry_safe(rg_entry, tmprg_entry,
7908b8ef05bSVictor Raj &recps[i].rg_list, l_entry) {
7918b8ef05bSVictor Raj list_del(&rg_entry->l_entry);
7928b8ef05bSVictor Raj devm_kfree(ice_hw_to_dev(hw), rg_entry);
7938b8ef05bSVictor Raj }
7948b8ef05bSVictor Raj
7958b8ef05bSVictor Raj if (recps[i].adv_rule) {
7968b8ef05bSVictor Raj struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
7978b8ef05bSVictor Raj struct ice_adv_fltr_mgmt_list_entry *lst_itr;
7988b8ef05bSVictor Raj
79980d144c9SAnirudh Venkataramanan mutex_destroy(&recps[i].filt_rule_lock);
80080d144c9SAnirudh Venkataramanan list_for_each_entry_safe(lst_itr, tmp_entry,
8018b8ef05bSVictor Raj &recps[i].filt_rules,
8028b8ef05bSVictor Raj list_entry) {
8038b8ef05bSVictor Raj list_del(&lst_itr->list_entry);
8048b8ef05bSVictor Raj devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups);
8058b8ef05bSVictor Raj devm_kfree(ice_hw_to_dev(hw), lst_itr);
8068b8ef05bSVictor Raj }
8078b8ef05bSVictor Raj } else {
8088b8ef05bSVictor Raj struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
8098b8ef05bSVictor Raj
8108b8ef05bSVictor Raj mutex_destroy(&recps[i].filt_rule_lock);
8118b8ef05bSVictor Raj list_for_each_entry_safe(lst_itr, tmp_entry,
8128b8ef05bSVictor Raj &recps[i].filt_rules,
8138b8ef05bSVictor Raj list_entry) {
81480d144c9SAnirudh Venkataramanan list_del(&lst_itr->list_entry);
81580d144c9SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), lst_itr);
81680d144c9SAnirudh Venkataramanan }
81780d144c9SAnirudh Venkataramanan }
8188b8ef05bSVictor Raj devm_kfree(ice_hw_to_dev(hw), recps[i].root_buf);
8198b8ef05bSVictor Raj }
820334cb062SAnirudh Venkataramanan ice_rm_all_sw_replay_rule_info(hw);
82180d144c9SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), sw->recp_list);
8229daf8208SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), sw);
8239daf8208SAnirudh Venkataramanan }
8249daf8208SAnirudh Venkataramanan
8258b97ceb1SHieu Tran /**
82611fe1b3aSDan Nowlin * ice_get_fw_log_cfg - get FW logging configuration
82711fe1b3aSDan Nowlin * @hw: pointer to the HW struct
82811fe1b3aSDan Nowlin */
ice_get_fw_log_cfg(struct ice_hw * hw)8295e24d598STony Nguyen static int ice_get_fw_log_cfg(struct ice_hw *hw)
83011fe1b3aSDan Nowlin {
83111fe1b3aSDan Nowlin struct ice_aq_desc desc;
832b3c38904SBruce Allan __le16 *config;
8335518ac2aSTony Nguyen int status;
83411fe1b3aSDan Nowlin u16 size;
83511fe1b3aSDan Nowlin
836b3c38904SBruce Allan size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX;
8371dacc497SChristophe JAILLET config = kzalloc(size, GFP_KERNEL);
83811fe1b3aSDan Nowlin if (!config)
839d54699e2STony Nguyen return -ENOMEM;
84011fe1b3aSDan Nowlin
84111fe1b3aSDan Nowlin ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info);
84211fe1b3aSDan Nowlin
84311fe1b3aSDan Nowlin status = ice_aq_send_cmd(hw, &desc, config, size, NULL);
84411fe1b3aSDan Nowlin if (!status) {
84511fe1b3aSDan Nowlin u16 i;
84611fe1b3aSDan Nowlin
8472f2da36eSAnirudh Venkataramanan /* Save FW logging information into the HW structure */
84811fe1b3aSDan Nowlin for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
84911fe1b3aSDan Nowlin u16 v, m, flgs;
85011fe1b3aSDan Nowlin
851b3c38904SBruce Allan v = le16_to_cpu(config[i]);
85211fe1b3aSDan Nowlin m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
85311fe1b3aSDan Nowlin flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S;
85411fe1b3aSDan Nowlin
85511fe1b3aSDan Nowlin if (m < ICE_AQC_FW_LOG_ID_MAX)
85611fe1b3aSDan Nowlin hw->fw_log.evnts[m].cur = flgs;
85711fe1b3aSDan Nowlin }
85811fe1b3aSDan Nowlin }
85911fe1b3aSDan Nowlin
8601dacc497SChristophe JAILLET kfree(config);
86111fe1b3aSDan Nowlin
86211fe1b3aSDan Nowlin return status;
86311fe1b3aSDan Nowlin }
86411fe1b3aSDan Nowlin
86511fe1b3aSDan Nowlin /**
8668b97ceb1SHieu Tran * ice_cfg_fw_log - configure FW logging
867f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
8688b97ceb1SHieu Tran * @enable: enable certain FW logging events if true, disable all if false
8698b97ceb1SHieu Tran *
8708b97ceb1SHieu Tran * This function enables/disables the FW logging via Rx CQ events and a UART
8718b97ceb1SHieu Tran * port based on predetermined configurations. FW logging via the Rx CQ can be
8728b97ceb1SHieu Tran * enabled/disabled for individual PF's. However, FW logging via the UART can
8738b97ceb1SHieu Tran * only be enabled/disabled for all PFs on the same device.
8748b97ceb1SHieu Tran *
8758b97ceb1SHieu Tran * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
8768b97ceb1SHieu Tran * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
8778b97ceb1SHieu Tran * before initializing the device.
8788b97ceb1SHieu Tran *
8798b97ceb1SHieu Tran * When re/configuring FW logging, callers need to update the "cfg" elements of
8808b97ceb1SHieu Tran * the hw->fw_log.evnts array with the desired logging event configurations for
8818b97ceb1SHieu Tran * modules of interest. When disabling FW logging completely, the callers can
8828b97ceb1SHieu Tran * just pass false in the "enable" parameter. On completion, the function will
8838b97ceb1SHieu Tran * update the "cur" element of the hw->fw_log.evnts array with the resulting
8848b97ceb1SHieu Tran * logging event configurations of the modules that are being re/configured. FW
8858b97ceb1SHieu Tran * logging modules that are not part of a reconfiguration operation retain their
8868b97ceb1SHieu Tran * previous states.
8878b97ceb1SHieu Tran *
8888b97ceb1SHieu Tran * Before resetting the device, it is recommended that the driver disables FW
8898b97ceb1SHieu Tran * logging before shutting down the control queue. When disabling FW logging
8908b97ceb1SHieu Tran * ("enable" = false), the latest configurations of FW logging events stored in
8918b97ceb1SHieu Tran * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
8928b97ceb1SHieu Tran * a device reset.
8938b97ceb1SHieu Tran *
8948b97ceb1SHieu Tran * When enabling FW logging to emit log messages via the Rx CQ during the
8958b97ceb1SHieu Tran * device's initialization phase, a mechanism alternative to interrupt handlers
8968b97ceb1SHieu Tran * needs to be used to extract FW log messages from the Rx CQ periodically and
8978b97ceb1SHieu Tran * to prevent the Rx CQ from being full and stalling other types of control
8988b97ceb1SHieu Tran * messages from FW to SW. Interrupts are typically disabled during the device's
8998b97ceb1SHieu Tran * initialization phase.
9008b97ceb1SHieu Tran */
ice_cfg_fw_log(struct ice_hw * hw,bool enable)9015e24d598STony Nguyen static int ice_cfg_fw_log(struct ice_hw *hw, bool enable)
9028b97ceb1SHieu Tran {
9038b97ceb1SHieu Tran struct ice_aqc_fw_logging *cmd;
9048b97ceb1SHieu Tran u16 i, chgs = 0, len = 0;
9058b97ceb1SHieu Tran struct ice_aq_desc desc;
906b3c38904SBruce Allan __le16 *data = NULL;
9078b97ceb1SHieu Tran u8 actv_evnts = 0;
9088b97ceb1SHieu Tran void *buf = NULL;
9095518ac2aSTony Nguyen int status = 0;
9108b97ceb1SHieu Tran
9118b97ceb1SHieu Tran if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
9128b97ceb1SHieu Tran return 0;
9138b97ceb1SHieu Tran
9148b97ceb1SHieu Tran /* Disable FW logging only when the control queue is still responsive */
9158b97ceb1SHieu Tran if (!enable &&
9168b97ceb1SHieu Tran (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
9178b97ceb1SHieu Tran return 0;
9188b97ceb1SHieu Tran
91911fe1b3aSDan Nowlin /* Get current FW log settings */
92011fe1b3aSDan Nowlin status = ice_get_fw_log_cfg(hw);
92111fe1b3aSDan Nowlin if (status)
92211fe1b3aSDan Nowlin return status;
92311fe1b3aSDan Nowlin
9248b97ceb1SHieu Tran ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
9258b97ceb1SHieu Tran cmd = &desc.params.fw_logging;
9268b97ceb1SHieu Tran
9278b97ceb1SHieu Tran /* Indicate which controls are valid */
9288b97ceb1SHieu Tran if (hw->fw_log.cq_en)
9298b97ceb1SHieu Tran cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
9308b97ceb1SHieu Tran
9318b97ceb1SHieu Tran if (hw->fw_log.uart_en)
9328b97ceb1SHieu Tran cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
9338b97ceb1SHieu Tran
9348b97ceb1SHieu Tran if (enable) {
9358b97ceb1SHieu Tran /* Fill in an array of entries with FW logging modules and
9368b97ceb1SHieu Tran * logging events being reconfigured.
9378b97ceb1SHieu Tran */
9388b97ceb1SHieu Tran for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
9398b97ceb1SHieu Tran u16 val;
9408b97ceb1SHieu Tran
9418b97ceb1SHieu Tran /* Keep track of enabled event types */
9428b97ceb1SHieu Tran actv_evnts |= hw->fw_log.evnts[i].cfg;
9438b97ceb1SHieu Tran
9448b97ceb1SHieu Tran if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
9458b97ceb1SHieu Tran continue;
9468b97ceb1SHieu Tran
9478b97ceb1SHieu Tran if (!data) {
948b3c38904SBruce Allan data = devm_kcalloc(ice_hw_to_dev(hw),
949b3c38904SBruce Allan ICE_AQC_FW_LOG_ID_MAX,
95059df14f9SBruce Allan sizeof(*data),
9518b97ceb1SHieu Tran GFP_KERNEL);
9528b97ceb1SHieu Tran if (!data)
953d54699e2STony Nguyen return -ENOMEM;
9548b97ceb1SHieu Tran }
9558b97ceb1SHieu Tran
9568b97ceb1SHieu Tran val = i << ICE_AQC_FW_LOG_ID_S;
9578b97ceb1SHieu Tran val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
958b3c38904SBruce Allan data[chgs++] = cpu_to_le16(val);
9598b97ceb1SHieu Tran }
9608b97ceb1SHieu Tran
9618b97ceb1SHieu Tran /* Only enable FW logging if at least one module is specified.
9628b97ceb1SHieu Tran * If FW logging is currently enabled but all modules are not
9638b97ceb1SHieu Tran * enabled to emit log messages, disable FW logging altogether.
9648b97ceb1SHieu Tran */
9658b97ceb1SHieu Tran if (actv_evnts) {
9668b97ceb1SHieu Tran /* Leave if there is effectively no change */
9678b97ceb1SHieu Tran if (!chgs)
9688b97ceb1SHieu Tran goto out;
9698b97ceb1SHieu Tran
9708b97ceb1SHieu Tran if (hw->fw_log.cq_en)
9718b97ceb1SHieu Tran cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
9728b97ceb1SHieu Tran
9738b97ceb1SHieu Tran if (hw->fw_log.uart_en)
9748b97ceb1SHieu Tran cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
9758b97ceb1SHieu Tran
9768b97ceb1SHieu Tran buf = data;
977b3c38904SBruce Allan len = sizeof(*data) * chgs;
9788b97ceb1SHieu Tran desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
9798b97ceb1SHieu Tran }
9808b97ceb1SHieu Tran }
9818b97ceb1SHieu Tran
9828b97ceb1SHieu Tran status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
9838b97ceb1SHieu Tran if (!status) {
9848b97ceb1SHieu Tran /* Update the current configuration to reflect events enabled.
9858b97ceb1SHieu Tran * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
9868b97ceb1SHieu Tran * logging mode is enabled for the device. They do not reflect
9878b97ceb1SHieu Tran * actual modules being enabled to emit log messages. So, their
9888b97ceb1SHieu Tran * values remain unchanged even when all modules are disabled.
9898b97ceb1SHieu Tran */
9908b97ceb1SHieu Tran u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
9918b97ceb1SHieu Tran
9928b97ceb1SHieu Tran hw->fw_log.actv_evnts = actv_evnts;
9938b97ceb1SHieu Tran for (i = 0; i < cnt; i++) {
9948b97ceb1SHieu Tran u16 v, m;
9958b97ceb1SHieu Tran
9968b97ceb1SHieu Tran if (!enable) {
9978b97ceb1SHieu Tran /* When disabling all FW logging events as part
9988b97ceb1SHieu Tran * of device's de-initialization, the original
9998b97ceb1SHieu Tran * configurations are retained, and can be used
10008b97ceb1SHieu Tran * to reconfigure FW logging later if the device
10018b97ceb1SHieu Tran * is re-initialized.
10028b97ceb1SHieu Tran */
10038b97ceb1SHieu Tran hw->fw_log.evnts[i].cur = 0;
10048b97ceb1SHieu Tran continue;
10058b97ceb1SHieu Tran }
10068b97ceb1SHieu Tran
1007b3c38904SBruce Allan v = le16_to_cpu(data[i]);
10088b97ceb1SHieu Tran m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
10098b97ceb1SHieu Tran hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
10108b97ceb1SHieu Tran }
10118b97ceb1SHieu Tran }
10128b97ceb1SHieu Tran
10138b97ceb1SHieu Tran out:
10148b97ceb1SHieu Tran devm_kfree(ice_hw_to_dev(hw), data);
10158b97ceb1SHieu Tran
10168b97ceb1SHieu Tran return status;
10178b97ceb1SHieu Tran }
10188b97ceb1SHieu Tran
10198b97ceb1SHieu Tran /**
10208b97ceb1SHieu Tran * ice_output_fw_log
1021f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
10228b97ceb1SHieu Tran * @desc: pointer to the AQ message descriptor
10238b97ceb1SHieu Tran * @buf: pointer to the buffer accompanying the AQ message
10248b97ceb1SHieu Tran *
10258b97ceb1SHieu Tran * Formats a FW Log message and outputs it via the standard driver logs.
10268b97ceb1SHieu Tran */
ice_output_fw_log(struct ice_hw * hw,struct ice_aq_desc * desc,void * buf)10278b97ceb1SHieu Tran void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
10288b97ceb1SHieu Tran {
10294f70daa0SJacob Keller ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n");
10304f70daa0SJacob Keller ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,
10318b97ceb1SHieu Tran le16_to_cpu(desc->datalen));
10324f70daa0SJacob Keller ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n");
10338b97ceb1SHieu Tran }
10348b97ceb1SHieu Tran
10359daf8208SAnirudh Venkataramanan /**
10364ee656bbSTony Nguyen * ice_get_itr_intrl_gran
1037f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
10389e4ab4c2SBrett Creeley *
10394ee656bbSTony Nguyen * Determines the ITR/INTRL granularities based on the maximum aggregate
10409e4ab4c2SBrett Creeley * bandwidth according to the device's configuration during power-on.
10419e4ab4c2SBrett Creeley */
ice_get_itr_intrl_gran(struct ice_hw * hw)1042fe7219faSBruce Allan static void ice_get_itr_intrl_gran(struct ice_hw *hw)
10439e4ab4c2SBrett Creeley {
10449e4ab4c2SBrett Creeley u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
10459e4ab4c2SBrett Creeley GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
10469e4ab4c2SBrett Creeley GL_PWR_MODE_CTL_CAR_MAX_BW_S;
10479e4ab4c2SBrett Creeley
10489e4ab4c2SBrett Creeley switch (max_agg_bw) {
10499e4ab4c2SBrett Creeley case ICE_MAX_AGG_BW_200G:
10509e4ab4c2SBrett Creeley case ICE_MAX_AGG_BW_100G:
10519e4ab4c2SBrett Creeley case ICE_MAX_AGG_BW_50G:
10529e4ab4c2SBrett Creeley hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
10539e4ab4c2SBrett Creeley hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
10549e4ab4c2SBrett Creeley break;
10559e4ab4c2SBrett Creeley case ICE_MAX_AGG_BW_25G:
10569e4ab4c2SBrett Creeley hw->itr_gran = ICE_ITR_GRAN_MAX_25;
10579e4ab4c2SBrett Creeley hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
10589e4ab4c2SBrett Creeley break;
10599e4ab4c2SBrett Creeley }
10609e4ab4c2SBrett Creeley }
10619e4ab4c2SBrett Creeley
10629e4ab4c2SBrett Creeley /**
1063f31e4b6fSAnirudh Venkataramanan * ice_init_hw - main hardware initialization routine
1064f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure
1065f31e4b6fSAnirudh Venkataramanan */
ice_init_hw(struct ice_hw * hw)10665e24d598STony Nguyen int ice_init_hw(struct ice_hw *hw)
1067f31e4b6fSAnirudh Venkataramanan {
1068dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps_data *pcaps;
1069dc49c772SAnirudh Venkataramanan u16 mac_buf_len;
1070dc49c772SAnirudh Venkataramanan void *mac_buf;
10715518ac2aSTony Nguyen int status;
1072f31e4b6fSAnirudh Venkataramanan
1073f31e4b6fSAnirudh Venkataramanan /* Set MAC type based on DeviceID */
1074f31e4b6fSAnirudh Venkataramanan status = ice_set_mac_type(hw);
1075f31e4b6fSAnirudh Venkataramanan if (status)
1076f31e4b6fSAnirudh Venkataramanan return status;
1077f31e4b6fSAnirudh Venkataramanan
1078f31e4b6fSAnirudh Venkataramanan hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
1079f31e4b6fSAnirudh Venkataramanan PF_FUNC_RID_FUNC_NUM_M) >>
1080f31e4b6fSAnirudh Venkataramanan PF_FUNC_RID_FUNC_NUM_S;
1081f31e4b6fSAnirudh Venkataramanan
1082f31e4b6fSAnirudh Venkataramanan status = ice_reset(hw, ICE_RESET_PFR);
1083f31e4b6fSAnirudh Venkataramanan if (status)
1084f31e4b6fSAnirudh Venkataramanan return status;
1085f31e4b6fSAnirudh Venkataramanan
1086fe7219faSBruce Allan ice_get_itr_intrl_gran(hw);
1087940b61afSAnirudh Venkataramanan
10885c91ecfdSJacob Keller status = ice_create_all_ctrlq(hw);
1089f31e4b6fSAnirudh Venkataramanan if (status)
1090f31e4b6fSAnirudh Venkataramanan goto err_unroll_cqinit;
1091f31e4b6fSAnirudh Venkataramanan
10928b97ceb1SHieu Tran /* Enable FW logging. Not fatal if this fails. */
10938b97ceb1SHieu Tran status = ice_cfg_fw_log(hw, true);
10948b97ceb1SHieu Tran if (status)
10958b97ceb1SHieu Tran ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
10968b97ceb1SHieu Tran
1097f31e4b6fSAnirudh Venkataramanan status = ice_clear_pf_cfg(hw);
1098f31e4b6fSAnirudh Venkataramanan if (status)
1099f31e4b6fSAnirudh Venkataramanan goto err_unroll_cqinit;
1100f31e4b6fSAnirudh Venkataramanan
1101148beb61SHenry Tieman /* Set bit to enable Flow Director filters */
1102148beb61SHenry Tieman wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
1103148beb61SHenry Tieman INIT_LIST_HEAD(&hw->fdir_list_head);
1104148beb61SHenry Tieman
1105f31e4b6fSAnirudh Venkataramanan ice_clear_pxe_mode(hw);
1106f31e4b6fSAnirudh Venkataramanan
1107f31e4b6fSAnirudh Venkataramanan status = ice_init_nvm(hw);
1108f31e4b6fSAnirudh Venkataramanan if (status)
1109f31e4b6fSAnirudh Venkataramanan goto err_unroll_cqinit;
1110f31e4b6fSAnirudh Venkataramanan
11119c20346bSAnirudh Venkataramanan status = ice_get_caps(hw);
11129c20346bSAnirudh Venkataramanan if (status)
11139c20346bSAnirudh Venkataramanan goto err_unroll_cqinit;
11149c20346bSAnirudh Venkataramanan
11155b246e53SMichal Swiatkowski if (!hw->port_info)
11169c20346bSAnirudh Venkataramanan hw->port_info = devm_kzalloc(ice_hw_to_dev(hw),
11175b246e53SMichal Swiatkowski sizeof(*hw->port_info),
11185b246e53SMichal Swiatkowski GFP_KERNEL);
11199c20346bSAnirudh Venkataramanan if (!hw->port_info) {
1120d54699e2STony Nguyen status = -ENOMEM;
11219c20346bSAnirudh Venkataramanan goto err_unroll_cqinit;
11229c20346bSAnirudh Venkataramanan }
11239c20346bSAnirudh Venkataramanan
1124f9867df6SAnirudh Venkataramanan /* set the back pointer to HW */
11259c20346bSAnirudh Venkataramanan hw->port_info->hw = hw;
11269c20346bSAnirudh Venkataramanan
11279c20346bSAnirudh Venkataramanan /* Initialize port_info struct with switch configuration data */
11289c20346bSAnirudh Venkataramanan status = ice_get_initial_sw_cfg(hw);
11299c20346bSAnirudh Venkataramanan if (status)
11309c20346bSAnirudh Venkataramanan goto err_unroll_alloc;
11319c20346bSAnirudh Venkataramanan
11329daf8208SAnirudh Venkataramanan hw->evb_veb = true;
11339daf8208SAnirudh Venkataramanan
113416dfa494SMichal Wilczynski /* init xarray for identifying scheduling nodes uniquely */
113516dfa494SMichal Wilczynski xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC);
113616dfa494SMichal Wilczynski
1137d337f2afSAnirudh Venkataramanan /* Query the allocated resources for Tx scheduler */
11389c20346bSAnirudh Venkataramanan status = ice_sched_query_res_alloc(hw);
11399c20346bSAnirudh Venkataramanan if (status) {
11409228d8b2SJacob Keller ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");
11419c20346bSAnirudh Venkataramanan goto err_unroll_alloc;
11429c20346bSAnirudh Venkataramanan }
11434f8a1497SBen Shelton ice_sched_get_psm_clk_freq(hw);
11449c20346bSAnirudh Venkataramanan
1145dc49c772SAnirudh Venkataramanan /* Initialize port_info struct with scheduler data */
1146dc49c772SAnirudh Venkataramanan status = ice_sched_init_port(hw->port_info);
1147dc49c772SAnirudh Venkataramanan if (status)
1148dc49c772SAnirudh Venkataramanan goto err_unroll_sched;
1149dc49c772SAnirudh Venkataramanan
1150dc49c772SAnirudh Venkataramanan pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
1151dc49c772SAnirudh Venkataramanan if (!pcaps) {
1152d54699e2STony Nguyen status = -ENOMEM;
1153dc49c772SAnirudh Venkataramanan goto err_unroll_sched;
1154dc49c772SAnirudh Venkataramanan }
1155dc49c772SAnirudh Venkataramanan
1156dc49c772SAnirudh Venkataramanan /* Initialize port_info struct with PHY capabilities */
1157dc49c772SAnirudh Venkataramanan status = ice_aq_get_phy_caps(hw->port_info, false,
1158d6730a87SAnirudh Venkataramanan ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps,
1159d6730a87SAnirudh Venkataramanan NULL);
1160dc49c772SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), pcaps);
1161dc49c772SAnirudh Venkataramanan if (status)
1162f2651a91SPaul M Stillwell Jr dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n",
1163f2651a91SPaul M Stillwell Jr status);
1164dc49c772SAnirudh Venkataramanan
1165dc49c772SAnirudh Venkataramanan /* Initialize port_info struct with link information */
1166dc49c772SAnirudh Venkataramanan status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
1167dc49c772SAnirudh Venkataramanan if (status)
1168dc49c772SAnirudh Venkataramanan goto err_unroll_sched;
1169dc49c772SAnirudh Venkataramanan
1170b36c598cSAnirudh Venkataramanan /* need a valid SW entry point to build a Tx tree */
1171b36c598cSAnirudh Venkataramanan if (!hw->sw_entry_point_layer) {
1172b36c598cSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
1173d54699e2STony Nguyen status = -EIO;
1174b36c598cSAnirudh Venkataramanan goto err_unroll_sched;
1175b36c598cSAnirudh Venkataramanan }
11769be1d6f8SAnirudh Venkataramanan INIT_LIST_HEAD(&hw->agg_list);
11771ddef455SUsha Ketineni /* Initialize max burst size */
11781ddef455SUsha Ketineni if (!hw->max_burst_size)
11791ddef455SUsha Ketineni ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
1180b36c598cSAnirudh Venkataramanan
11819daf8208SAnirudh Venkataramanan status = ice_init_fltr_mgmt_struct(hw);
11829daf8208SAnirudh Venkataramanan if (status)
11839daf8208SAnirudh Venkataramanan goto err_unroll_sched;
11849daf8208SAnirudh Venkataramanan
1185d6fef10cSMd Fahad Iqbal Polash /* Get MAC information */
1186d6fef10cSMd Fahad Iqbal Polash /* A single port can report up to two (LAN and WoL) addresses */
1187d6fef10cSMd Fahad Iqbal Polash mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2,
1188d6fef10cSMd Fahad Iqbal Polash sizeof(struct ice_aqc_manage_mac_read_resp),
1189d6fef10cSMd Fahad Iqbal Polash GFP_KERNEL);
1190d6fef10cSMd Fahad Iqbal Polash mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
1191dc49c772SAnirudh Venkataramanan
119263bb4e1eSWei Yongjun if (!mac_buf) {
1193d54699e2STony Nguyen status = -ENOMEM;
11949daf8208SAnirudh Venkataramanan goto err_unroll_fltr_mgmt_struct;
119563bb4e1eSWei Yongjun }
1196dc49c772SAnirudh Venkataramanan
1197dc49c772SAnirudh Venkataramanan status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
1198dc49c772SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), mac_buf);
1199dc49c772SAnirudh Venkataramanan
1200dc49c772SAnirudh Venkataramanan if (status)
12019daf8208SAnirudh Venkataramanan goto err_unroll_fltr_mgmt_struct;
120242449105SAnirudh Venkataramanan /* enable jumbo frame support at MAC level */
120342449105SAnirudh Venkataramanan status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
120442449105SAnirudh Venkataramanan if (status)
120542449105SAnirudh Venkataramanan goto err_unroll_fltr_mgmt_struct;
1206148beb61SHenry Tieman /* Obtain counter base index which would be used by flow director */
1207148beb61SHenry Tieman status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
1208148beb61SHenry Tieman if (status)
1209148beb61SHenry Tieman goto err_unroll_fltr_mgmt_struct;
121032d63fa1STony Nguyen status = ice_init_hw_tbls(hw);
121132d63fa1STony Nguyen if (status)
121232d63fa1STony Nguyen goto err_unroll_fltr_mgmt_struct;
1213a4e82a81STony Nguyen mutex_init(&hw->tnl_lock);
1214f31e4b6fSAnirudh Venkataramanan return 0;
1215f31e4b6fSAnirudh Venkataramanan
12169daf8208SAnirudh Venkataramanan err_unroll_fltr_mgmt_struct:
12179daf8208SAnirudh Venkataramanan ice_cleanup_fltr_mgmt_struct(hw);
1218dc49c772SAnirudh Venkataramanan err_unroll_sched:
1219dc49c772SAnirudh Venkataramanan ice_sched_cleanup_all(hw);
12209c20346bSAnirudh Venkataramanan err_unroll_alloc:
12219c20346bSAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), hw->port_info);
1222f31e4b6fSAnirudh Venkataramanan err_unroll_cqinit:
12235c91ecfdSJacob Keller ice_destroy_all_ctrlq(hw);
1224f31e4b6fSAnirudh Venkataramanan return status;
1225f31e4b6fSAnirudh Venkataramanan }
1226f31e4b6fSAnirudh Venkataramanan
1227f31e4b6fSAnirudh Venkataramanan /**
1228f31e4b6fSAnirudh Venkataramanan * ice_deinit_hw - unroll initialization operations done by ice_init_hw
1229f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure
1230ed14245aSAnirudh Venkataramanan *
1231ed14245aSAnirudh Venkataramanan * This should be called only during nominal operation, not as a result of
1232ed14245aSAnirudh Venkataramanan * ice_init_hw() failing since ice_init_hw() will take care of unrolling
1233ed14245aSAnirudh Venkataramanan * applicable initializations if it fails for any reason.
1234f31e4b6fSAnirudh Venkataramanan */
ice_deinit_hw(struct ice_hw * hw)1235f31e4b6fSAnirudh Venkataramanan void ice_deinit_hw(struct ice_hw *hw)
1236f31e4b6fSAnirudh Venkataramanan {
1237148beb61SHenry Tieman ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
12388b97ceb1SHieu Tran ice_cleanup_fltr_mgmt_struct(hw);
12398b97ceb1SHieu Tran
12409c20346bSAnirudh Venkataramanan ice_sched_cleanup_all(hw);
12419be1d6f8SAnirudh Venkataramanan ice_sched_clear_agg(hw);
1242c7648810STony Nguyen ice_free_seg(hw);
124332d63fa1STony Nguyen ice_free_hw_tbls(hw);
1244a4e82a81STony Nguyen mutex_destroy(&hw->tnl_lock);
1245dc49c772SAnirudh Venkataramanan
12468b97ceb1SHieu Tran /* Attempt to disable FW logging before shutting down control queues */
12478b97ceb1SHieu Tran ice_cfg_fw_log(hw, false);
12485c91ecfdSJacob Keller ice_destroy_all_ctrlq(hw);
124933e055fcSVictor Raj
125033e055fcSVictor Raj /* Clear VSI contexts if not already cleared */
125133e055fcSVictor Raj ice_clear_all_vsi_ctx(hw);
1252f31e4b6fSAnirudh Venkataramanan }
1253f31e4b6fSAnirudh Venkataramanan
1254f31e4b6fSAnirudh Venkataramanan /**
1255f31e4b6fSAnirudh Venkataramanan * ice_check_reset - Check to see if a global reset is complete
1256f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure
1257f31e4b6fSAnirudh Venkataramanan */
ice_check_reset(struct ice_hw * hw)12585e24d598STony Nguyen int ice_check_reset(struct ice_hw *hw)
1259f31e4b6fSAnirudh Venkataramanan {
1260585cdabdSNick Nunley u32 cnt, reg = 0, grst_timeout, uld_mask;
1261f31e4b6fSAnirudh Venkataramanan
1262f31e4b6fSAnirudh Venkataramanan /* Poll for Device Active state in case a recent CORER, GLOBR,
1263f31e4b6fSAnirudh Venkataramanan * or EMPR has occurred. The grst delay value is in 100ms units.
1264f31e4b6fSAnirudh Venkataramanan * Add 1sec for outstanding AQ commands that can take a long time.
1265f31e4b6fSAnirudh Venkataramanan */
1266585cdabdSNick Nunley grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
1267f31e4b6fSAnirudh Venkataramanan GLGEN_RSTCTL_GRSTDEL_S) + 10;
1268f31e4b6fSAnirudh Venkataramanan
1269585cdabdSNick Nunley for (cnt = 0; cnt < grst_timeout; cnt++) {
1270f31e4b6fSAnirudh Venkataramanan mdelay(100);
1271f31e4b6fSAnirudh Venkataramanan reg = rd32(hw, GLGEN_RSTAT);
1272f31e4b6fSAnirudh Venkataramanan if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1273f31e4b6fSAnirudh Venkataramanan break;
1274f31e4b6fSAnirudh Venkataramanan }
1275f31e4b6fSAnirudh Venkataramanan
1276585cdabdSNick Nunley if (cnt == grst_timeout) {
12779228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n");
1278d54699e2STony Nguyen return -EIO;
1279f31e4b6fSAnirudh Venkataramanan }
1280f31e4b6fSAnirudh Venkataramanan
1281cf8fc2a0SBruce Allan #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
1282cf8fc2a0SBruce Allan GLNVM_ULD_PCIER_DONE_1_M |\
1283cf8fc2a0SBruce Allan GLNVM_ULD_CORER_DONE_M |\
1284cf8fc2a0SBruce Allan GLNVM_ULD_GLOBR_DONE_M |\
1285cf8fc2a0SBruce Allan GLNVM_ULD_POR_DONE_M |\
1286cf8fc2a0SBruce Allan GLNVM_ULD_POR_DONE_1_M |\
1287cf8fc2a0SBruce Allan GLNVM_ULD_PCIER_DONE_2_M)
1288cf8fc2a0SBruce Allan
1289d25a0fc4SDave Ertman uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ?
1290d25a0fc4SDave Ertman GLNVM_ULD_PE_DONE_M : 0);
1291f31e4b6fSAnirudh Venkataramanan
1292f31e4b6fSAnirudh Venkataramanan /* Device is Active; check Global Reset processes are done */
1293f31e4b6fSAnirudh Venkataramanan for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1294cf8fc2a0SBruce Allan reg = rd32(hw, GLNVM_ULD) & uld_mask;
1295cf8fc2a0SBruce Allan if (reg == uld_mask) {
12969228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);
1297f31e4b6fSAnirudh Venkataramanan break;
1298f31e4b6fSAnirudh Venkataramanan }
1299f31e4b6fSAnirudh Venkataramanan mdelay(10);
1300f31e4b6fSAnirudh Venkataramanan }
1301f31e4b6fSAnirudh Venkataramanan
1302f31e4b6fSAnirudh Venkataramanan if (cnt == ICE_PF_RESET_WAIT_COUNT) {
13039228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1304f31e4b6fSAnirudh Venkataramanan reg);
1305d54699e2STony Nguyen return -EIO;
1306f31e4b6fSAnirudh Venkataramanan }
1307f31e4b6fSAnirudh Venkataramanan
1308f31e4b6fSAnirudh Venkataramanan return 0;
1309f31e4b6fSAnirudh Venkataramanan }
1310f31e4b6fSAnirudh Venkataramanan
1311f31e4b6fSAnirudh Venkataramanan /**
1312f31e4b6fSAnirudh Venkataramanan * ice_pf_reset - Reset the PF
1313f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure
1314f31e4b6fSAnirudh Venkataramanan *
1315f31e4b6fSAnirudh Venkataramanan * If a global reset has been triggered, this function checks
1316f31e4b6fSAnirudh Venkataramanan * for its completion and then issues the PF reset
1317f31e4b6fSAnirudh Venkataramanan */
ice_pf_reset(struct ice_hw * hw)13185e24d598STony Nguyen static int ice_pf_reset(struct ice_hw *hw)
1319f31e4b6fSAnirudh Venkataramanan {
1320f31e4b6fSAnirudh Venkataramanan u32 cnt, reg;
1321f31e4b6fSAnirudh Venkataramanan
1322f31e4b6fSAnirudh Venkataramanan /* If at function entry a global reset was already in progress, i.e.
1323f31e4b6fSAnirudh Venkataramanan * state is not 'device active' or any of the reset done bits are not
1324f31e4b6fSAnirudh Venkataramanan * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1325f31e4b6fSAnirudh Venkataramanan * global reset is done.
1326f31e4b6fSAnirudh Venkataramanan */
1327f31e4b6fSAnirudh Venkataramanan if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1328f31e4b6fSAnirudh Venkataramanan (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1329f31e4b6fSAnirudh Venkataramanan /* poll on global reset currently in progress until done */
1330f31e4b6fSAnirudh Venkataramanan if (ice_check_reset(hw))
1331d54699e2STony Nguyen return -EIO;
1332f31e4b6fSAnirudh Venkataramanan
1333f31e4b6fSAnirudh Venkataramanan return 0;
1334f31e4b6fSAnirudh Venkataramanan }
1335f31e4b6fSAnirudh Venkataramanan
1336f31e4b6fSAnirudh Venkataramanan /* Reset the PF */
1337f31e4b6fSAnirudh Venkataramanan reg = rd32(hw, PFGEN_CTRL);
1338f31e4b6fSAnirudh Venkataramanan
1339f31e4b6fSAnirudh Venkataramanan wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1340f31e4b6fSAnirudh Venkataramanan
1341c9a12d6dSDan Nowlin /* Wait for the PFR to complete. The wait time is the global config lock
1342c9a12d6dSDan Nowlin * timeout plus the PFR timeout which will account for a possible reset
1343c9a12d6dSDan Nowlin * that is occurring during a download package operation.
1344c9a12d6dSDan Nowlin */
1345c9a12d6dSDan Nowlin for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
1346c9a12d6dSDan Nowlin ICE_PF_RESET_WAIT_COUNT; cnt++) {
1347f31e4b6fSAnirudh Venkataramanan reg = rd32(hw, PFGEN_CTRL);
1348f31e4b6fSAnirudh Venkataramanan if (!(reg & PFGEN_CTRL_PFSWR_M))
1349f31e4b6fSAnirudh Venkataramanan break;
1350f31e4b6fSAnirudh Venkataramanan
1351f31e4b6fSAnirudh Venkataramanan mdelay(1);
1352f31e4b6fSAnirudh Venkataramanan }
1353f31e4b6fSAnirudh Venkataramanan
1354f31e4b6fSAnirudh Venkataramanan if (cnt == ICE_PF_RESET_WAIT_COUNT) {
13559228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");
1356d54699e2STony Nguyen return -EIO;
1357f31e4b6fSAnirudh Venkataramanan }
1358f31e4b6fSAnirudh Venkataramanan
1359f31e4b6fSAnirudh Venkataramanan return 0;
1360f31e4b6fSAnirudh Venkataramanan }
1361f31e4b6fSAnirudh Venkataramanan
1362f31e4b6fSAnirudh Venkataramanan /**
1363f31e4b6fSAnirudh Venkataramanan * ice_reset - Perform different types of reset
1364f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure
1365f31e4b6fSAnirudh Venkataramanan * @req: reset request
1366f31e4b6fSAnirudh Venkataramanan *
1367f31e4b6fSAnirudh Venkataramanan * This function triggers a reset as specified by the req parameter.
1368f31e4b6fSAnirudh Venkataramanan *
1369f31e4b6fSAnirudh Venkataramanan * Note:
1370f31e4b6fSAnirudh Venkataramanan * If anything other than a PF reset is triggered, PXE mode is restored.
1371f31e4b6fSAnirudh Venkataramanan * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1372f31e4b6fSAnirudh Venkataramanan * interface has been restored in the rebuild flow.
1373f31e4b6fSAnirudh Venkataramanan */
ice_reset(struct ice_hw * hw,enum ice_reset_req req)13745e24d598STony Nguyen int ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1375f31e4b6fSAnirudh Venkataramanan {
1376f31e4b6fSAnirudh Venkataramanan u32 val = 0;
1377f31e4b6fSAnirudh Venkataramanan
1378f31e4b6fSAnirudh Venkataramanan switch (req) {
1379f31e4b6fSAnirudh Venkataramanan case ICE_RESET_PFR:
1380f31e4b6fSAnirudh Venkataramanan return ice_pf_reset(hw);
1381f31e4b6fSAnirudh Venkataramanan case ICE_RESET_CORER:
1382f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1383f31e4b6fSAnirudh Venkataramanan val = GLGEN_RTRIG_CORER_M;
1384f31e4b6fSAnirudh Venkataramanan break;
1385f31e4b6fSAnirudh Venkataramanan case ICE_RESET_GLOBR:
1386f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1387f31e4b6fSAnirudh Venkataramanan val = GLGEN_RTRIG_GLOBR_M;
1388f31e4b6fSAnirudh Venkataramanan break;
13890f9d5027SAnirudh Venkataramanan default:
1390d54699e2STony Nguyen return -EINVAL;
1391f31e4b6fSAnirudh Venkataramanan }
1392f31e4b6fSAnirudh Venkataramanan
1393f31e4b6fSAnirudh Venkataramanan val |= rd32(hw, GLGEN_RTRIG);
1394f31e4b6fSAnirudh Venkataramanan wr32(hw, GLGEN_RTRIG, val);
1395f31e4b6fSAnirudh Venkataramanan ice_flush(hw);
1396f31e4b6fSAnirudh Venkataramanan
1397f31e4b6fSAnirudh Venkataramanan /* wait for the FW to be ready */
1398f31e4b6fSAnirudh Venkataramanan return ice_check_reset(hw);
1399f31e4b6fSAnirudh Venkataramanan }
1400f31e4b6fSAnirudh Venkataramanan
14017ec59eeaSAnirudh Venkataramanan /**
1402cdedef59SAnirudh Venkataramanan * ice_copy_rxq_ctx_to_hw
1403cdedef59SAnirudh Venkataramanan * @hw: pointer to the hardware structure
1404cdedef59SAnirudh Venkataramanan * @ice_rxq_ctx: pointer to the rxq context
1405d337f2afSAnirudh Venkataramanan * @rxq_index: the index of the Rx queue
1406cdedef59SAnirudh Venkataramanan *
1407f9867df6SAnirudh Venkataramanan * Copies rxq context from dense structure to HW register space
1408cdedef59SAnirudh Venkataramanan */
14095e24d598STony Nguyen static int
ice_copy_rxq_ctx_to_hw(struct ice_hw * hw,u8 * ice_rxq_ctx,u32 rxq_index)1410cdedef59SAnirudh Venkataramanan ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1411cdedef59SAnirudh Venkataramanan {
1412cdedef59SAnirudh Venkataramanan u8 i;
1413cdedef59SAnirudh Venkataramanan
1414cdedef59SAnirudh Venkataramanan if (!ice_rxq_ctx)
1415d54699e2STony Nguyen return -EINVAL;
1416cdedef59SAnirudh Venkataramanan
1417cdedef59SAnirudh Venkataramanan if (rxq_index > QRX_CTRL_MAX_INDEX)
1418d54699e2STony Nguyen return -EINVAL;
1419cdedef59SAnirudh Venkataramanan
1420f9867df6SAnirudh Venkataramanan /* Copy each dword separately to HW */
1421cdedef59SAnirudh Venkataramanan for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1422cdedef59SAnirudh Venkataramanan wr32(hw, QRX_CONTEXT(i, rxq_index),
1423cdedef59SAnirudh Venkataramanan *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1424cdedef59SAnirudh Venkataramanan
1425cdedef59SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1426cdedef59SAnirudh Venkataramanan *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1427cdedef59SAnirudh Venkataramanan }
1428cdedef59SAnirudh Venkataramanan
1429cdedef59SAnirudh Venkataramanan return 0;
1430cdedef59SAnirudh Venkataramanan }
1431cdedef59SAnirudh Venkataramanan
1432cdedef59SAnirudh Venkataramanan /* LAN Rx Queue Context */
1433cdedef59SAnirudh Venkataramanan static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1434cdedef59SAnirudh Venkataramanan /* Field Width LSB */
1435cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1436cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1437cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1438cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1439cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1440cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1441cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1442cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1443cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1444cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1445cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1446cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1447cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1448cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1449cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1450cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1451cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1452cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1453cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1454c31a5c25SBrett Creeley ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1455cdedef59SAnirudh Venkataramanan { 0 }
1456cdedef59SAnirudh Venkataramanan };
1457cdedef59SAnirudh Venkataramanan
1458cdedef59SAnirudh Venkataramanan /**
1459cdedef59SAnirudh Venkataramanan * ice_write_rxq_ctx
1460cdedef59SAnirudh Venkataramanan * @hw: pointer to the hardware structure
1461cdedef59SAnirudh Venkataramanan * @rlan_ctx: pointer to the rxq context
1462d337f2afSAnirudh Venkataramanan * @rxq_index: the index of the Rx queue
1463cdedef59SAnirudh Venkataramanan *
1464cdedef59SAnirudh Venkataramanan * Converts rxq context from sparse to dense structure and then writes
1465c31a5c25SBrett Creeley * it to HW register space and enables the hardware to prefetch descriptors
1466c31a5c25SBrett Creeley * instead of only fetching them on demand
1467cdedef59SAnirudh Venkataramanan */
14685e24d598STony Nguyen int
ice_write_rxq_ctx(struct ice_hw * hw,struct ice_rlan_ctx * rlan_ctx,u32 rxq_index)1469cdedef59SAnirudh Venkataramanan ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1470cdedef59SAnirudh Venkataramanan u32 rxq_index)
1471cdedef59SAnirudh Venkataramanan {
1472cdedef59SAnirudh Venkataramanan u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1473cdedef59SAnirudh Venkataramanan
1474c31a5c25SBrett Creeley if (!rlan_ctx)
1475d54699e2STony Nguyen return -EINVAL;
1476c31a5c25SBrett Creeley
1477c31a5c25SBrett Creeley rlan_ctx->prefena = 1;
1478c31a5c25SBrett Creeley
14797e34786aSBruce Allan ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1480cdedef59SAnirudh Venkataramanan return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1481cdedef59SAnirudh Venkataramanan }
1482cdedef59SAnirudh Venkataramanan
1483cdedef59SAnirudh Venkataramanan /* LAN Tx Queue Context */
1484cdedef59SAnirudh Venkataramanan const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1485cdedef59SAnirudh Venkataramanan /* Field Width LSB */
1486cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1487cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1488cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1489cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1490cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1491cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1492cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1493cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1494201beeb7SAshish Shah ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1495cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1496cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1497cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1498cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1499cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1500cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1501cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1502cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1503cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1504cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1505cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1506cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1507cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1508cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1509cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1510cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1511cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1512cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1513201beeb7SAshish Shah ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1514cdedef59SAnirudh Venkataramanan { 0 }
1515cdedef59SAnirudh Venkataramanan };
1516cdedef59SAnirudh Venkataramanan
15178f5ee3c4SJacob Keller /* Sideband Queue command wrappers */
15188f5ee3c4SJacob Keller
15198f5ee3c4SJacob Keller /**
15208f5ee3c4SJacob Keller * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue
15218f5ee3c4SJacob Keller * @hw: pointer to the HW struct
15228f5ee3c4SJacob Keller * @desc: descriptor describing the command
15238f5ee3c4SJacob Keller * @buf: buffer to use for indirect commands (NULL for direct commands)
15248f5ee3c4SJacob Keller * @buf_size: size of buffer for indirect commands (0 for direct commands)
15258f5ee3c4SJacob Keller * @cd: pointer to command details structure
15268f5ee3c4SJacob Keller */
15278f5ee3c4SJacob Keller static int
ice_sbq_send_cmd(struct ice_hw * hw,struct ice_sbq_cmd_desc * desc,void * buf,u16 buf_size,struct ice_sq_cd * cd)15288f5ee3c4SJacob Keller ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc,
15298f5ee3c4SJacob Keller void *buf, u16 buf_size, struct ice_sq_cd *cd)
15308f5ee3c4SJacob Keller {
1531d54699e2STony Nguyen return ice_sq_send_cmd(hw, ice_get_sbq(hw),
1532d54699e2STony Nguyen (struct ice_aq_desc *)desc, buf, buf_size, cd);
15338f5ee3c4SJacob Keller }
15348f5ee3c4SJacob Keller
15358f5ee3c4SJacob Keller /**
15368f5ee3c4SJacob Keller * ice_sbq_rw_reg - Fill Sideband Queue command
15378f5ee3c4SJacob Keller * @hw: pointer to the HW struct
15388f5ee3c4SJacob Keller * @in: message info to be filled in descriptor
15398f5ee3c4SJacob Keller */
ice_sbq_rw_reg(struct ice_hw * hw,struct ice_sbq_msg_input * in)15408f5ee3c4SJacob Keller int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in)
15418f5ee3c4SJacob Keller {
15428f5ee3c4SJacob Keller struct ice_sbq_cmd_desc desc = {0};
15438f5ee3c4SJacob Keller struct ice_sbq_msg_req msg = {0};
15448f5ee3c4SJacob Keller u16 msg_len;
15458f5ee3c4SJacob Keller int status;
15468f5ee3c4SJacob Keller
15478f5ee3c4SJacob Keller msg_len = sizeof(msg);
15488f5ee3c4SJacob Keller
15498f5ee3c4SJacob Keller msg.dest_dev = in->dest_dev;
15508f5ee3c4SJacob Keller msg.opcode = in->opcode;
15518f5ee3c4SJacob Keller msg.flags = ICE_SBQ_MSG_FLAGS;
15528f5ee3c4SJacob Keller msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE;
15538f5ee3c4SJacob Keller msg.msg_addr_low = cpu_to_le16(in->msg_addr_low);
15548f5ee3c4SJacob Keller msg.msg_addr_high = cpu_to_le32(in->msg_addr_high);
15558f5ee3c4SJacob Keller
15568f5ee3c4SJacob Keller if (in->opcode)
15578f5ee3c4SJacob Keller msg.data = cpu_to_le32(in->data);
15588f5ee3c4SJacob Keller else
15598f5ee3c4SJacob Keller /* data read comes back in completion, so shorten the struct by
15608f5ee3c4SJacob Keller * sizeof(msg.data)
15618f5ee3c4SJacob Keller */
15628f5ee3c4SJacob Keller msg_len -= sizeof(msg.data);
15638f5ee3c4SJacob Keller
15648f5ee3c4SJacob Keller desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD);
15658f5ee3c4SJacob Keller desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req);
15668f5ee3c4SJacob Keller desc.param0.cmd_len = cpu_to_le16(msg_len);
15678f5ee3c4SJacob Keller status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL);
15688f5ee3c4SJacob Keller if (!status && !in->opcode)
15698f5ee3c4SJacob Keller in->data = le32_to_cpu
15708f5ee3c4SJacob Keller (((struct ice_sbq_msg_cmpl *)&msg)->data);
15718f5ee3c4SJacob Keller return status;
15728f5ee3c4SJacob Keller }
15738f5ee3c4SJacob Keller
15747ec59eeaSAnirudh Venkataramanan /* FW Admin Queue command wrappers */
15757ec59eeaSAnirudh Venkataramanan
1576c7648810STony Nguyen /* Software lock/mutex that is meant to be held while the Global Config Lock
1577c7648810STony Nguyen * in firmware is acquired by the software to prevent most (but not all) types
1578c7648810STony Nguyen * of AQ commands from being sent to FW
1579c7648810STony Nguyen */
1580c7648810STony Nguyen DEFINE_MUTEX(ice_global_cfg_lock_sw);
1581c7648810STony Nguyen
15827ec59eeaSAnirudh Venkataramanan /**
15833056df93SChinh T Cao * ice_should_retry_sq_send_cmd
15843056df93SChinh T Cao * @opcode: AQ opcode
15853056df93SChinh T Cao *
15863056df93SChinh T Cao * Decide if we should retry the send command routine for the ATQ, depending
15873056df93SChinh T Cao * on the opcode.
15883056df93SChinh T Cao */
ice_should_retry_sq_send_cmd(u16 opcode)15893056df93SChinh T Cao static bool ice_should_retry_sq_send_cmd(u16 opcode)
15903056df93SChinh T Cao {
15913056df93SChinh T Cao switch (opcode) {
15923056df93SChinh T Cao case ice_aqc_opc_get_link_topo:
15933056df93SChinh T Cao case ice_aqc_opc_lldp_stop:
15943056df93SChinh T Cao case ice_aqc_opc_lldp_start:
15953056df93SChinh T Cao case ice_aqc_opc_lldp_filter_ctrl:
15963056df93SChinh T Cao return true;
15973056df93SChinh T Cao }
15983056df93SChinh T Cao
15993056df93SChinh T Cao return false;
16003056df93SChinh T Cao }
16013056df93SChinh T Cao
16023056df93SChinh T Cao /**
16033056df93SChinh T Cao * ice_sq_send_cmd_retry - send command to Control Queue (ATQ)
16043056df93SChinh T Cao * @hw: pointer to the HW struct
16053056df93SChinh T Cao * @cq: pointer to the specific Control queue
16063056df93SChinh T Cao * @desc: prefilled descriptor describing the command
16073056df93SChinh T Cao * @buf: buffer to use for indirect commands (or NULL for direct commands)
16083056df93SChinh T Cao * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
16093056df93SChinh T Cao * @cd: pointer to command details structure
16103056df93SChinh T Cao *
16113056df93SChinh T Cao * Retry sending the FW Admin Queue command, multiple times, to the FW Admin
16123056df93SChinh T Cao * Queue if the EBUSY AQ error is returned.
16133056df93SChinh T Cao */
16145e24d598STony Nguyen static int
ice_sq_send_cmd_retry(struct ice_hw * hw,struct ice_ctl_q_info * cq,struct ice_aq_desc * desc,void * buf,u16 buf_size,struct ice_sq_cd * cd)16153056df93SChinh T Cao ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq,
16163056df93SChinh T Cao struct ice_aq_desc *desc, void *buf, u16 buf_size,
16173056df93SChinh T Cao struct ice_sq_cd *cd)
16183056df93SChinh T Cao {
16193056df93SChinh T Cao struct ice_aq_desc desc_cpy;
16203056df93SChinh T Cao bool is_cmd_for_retry;
16213056df93SChinh T Cao u8 idx = 0;
16223056df93SChinh T Cao u16 opcode;
16235518ac2aSTony Nguyen int status;
16243056df93SChinh T Cao
16253056df93SChinh T Cao opcode = le16_to_cpu(desc->opcode);
16263056df93SChinh T Cao is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode);
16273056df93SChinh T Cao memset(&desc_cpy, 0, sizeof(desc_cpy));
16283056df93SChinh T Cao
16293056df93SChinh T Cao if (is_cmd_for_retry) {
163043a630e3SMichal Schmidt /* All retryable cmds are direct, without buf. */
163143a630e3SMichal Schmidt WARN_ON(buf);
16323056df93SChinh T Cao
16333056df93SChinh T Cao memcpy(&desc_cpy, desc, sizeof(desc_cpy));
16343056df93SChinh T Cao }
16353056df93SChinh T Cao
16363056df93SChinh T Cao do {
16373056df93SChinh T Cao status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd);
16383056df93SChinh T Cao
16393056df93SChinh T Cao if (!is_cmd_for_retry || !status ||
16403056df93SChinh T Cao hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY)
16413056df93SChinh T Cao break;
16423056df93SChinh T Cao
16433056df93SChinh T Cao memcpy(desc, &desc_cpy, sizeof(desc_cpy));
16443056df93SChinh T Cao
1645b488ae52SMichal Schmidt msleep(ICE_SQ_SEND_DELAY_TIME_MS);
16463056df93SChinh T Cao
16473056df93SChinh T Cao } while (++idx < ICE_SQ_SEND_MAX_EXECUTE);
16483056df93SChinh T Cao
16493056df93SChinh T Cao return status;
16503056df93SChinh T Cao }
16513056df93SChinh T Cao
16523056df93SChinh T Cao /**
16537ec59eeaSAnirudh Venkataramanan * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1654f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
16557ec59eeaSAnirudh Venkataramanan * @desc: descriptor describing the command
16567ec59eeaSAnirudh Venkataramanan * @buf: buffer to use for indirect commands (NULL for direct commands)
16577ec59eeaSAnirudh Venkataramanan * @buf_size: size of buffer for indirect commands (0 for direct commands)
16587ec59eeaSAnirudh Venkataramanan * @cd: pointer to command details structure
16597ec59eeaSAnirudh Venkataramanan *
16607ec59eeaSAnirudh Venkataramanan * Helper function to send FW Admin Queue commands to the FW Admin Queue.
16617ec59eeaSAnirudh Venkataramanan */
16625e24d598STony Nguyen int
ice_aq_send_cmd(struct ice_hw * hw,struct ice_aq_desc * desc,void * buf,u16 buf_size,struct ice_sq_cd * cd)16637ec59eeaSAnirudh Venkataramanan ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
16647ec59eeaSAnirudh Venkataramanan u16 buf_size, struct ice_sq_cd *cd)
16657ec59eeaSAnirudh Venkataramanan {
1666c7648810STony Nguyen struct ice_aqc_req_res *cmd = &desc->params.res_owner;
1667c7648810STony Nguyen bool lock_acquired = false;
16685e24d598STony Nguyen int status;
1669c7648810STony Nguyen
1670c7648810STony Nguyen /* When a package download is in process (i.e. when the firmware's
1671c7648810STony Nguyen * Global Configuration Lock resource is held), only the Download
1672a1ffafb0SBrett Creeley * Package, Get Version, Get Package Info List, Upload Section,
1673a1ffafb0SBrett Creeley * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters,
1674a1ffafb0SBrett Creeley * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get
1675a1ffafb0SBrett Creeley * Recipes to Profile Association, and Release Resource (with resource
1676a1ffafb0SBrett Creeley * ID set to Global Config Lock) AdminQ commands are allowed; all others
1677a1ffafb0SBrett Creeley * must block until the package download completes and the Global Config
1678a1ffafb0SBrett Creeley * Lock is released. See also ice_acquire_global_cfg_lock().
1679c7648810STony Nguyen */
1680c7648810STony Nguyen switch (le16_to_cpu(desc->opcode)) {
1681c7648810STony Nguyen case ice_aqc_opc_download_pkg:
1682c7648810STony Nguyen case ice_aqc_opc_get_pkg_info_list:
1683c7648810STony Nguyen case ice_aqc_opc_get_ver:
1684a1ffafb0SBrett Creeley case ice_aqc_opc_upload_section:
1685a1ffafb0SBrett Creeley case ice_aqc_opc_update_pkg:
1686a1ffafb0SBrett Creeley case ice_aqc_opc_set_port_params:
1687a1ffafb0SBrett Creeley case ice_aqc_opc_get_vlan_mode_parameters:
1688a1ffafb0SBrett Creeley case ice_aqc_opc_set_vlan_mode_parameters:
1689a1ffafb0SBrett Creeley case ice_aqc_opc_add_recipe:
1690a1ffafb0SBrett Creeley case ice_aqc_opc_recipe_to_profile:
1691a1ffafb0SBrett Creeley case ice_aqc_opc_get_recipe:
1692a1ffafb0SBrett Creeley case ice_aqc_opc_get_recipe_to_profile:
1693c7648810STony Nguyen break;
1694c7648810STony Nguyen case ice_aqc_opc_release_res:
1695c7648810STony Nguyen if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK)
1696c7648810STony Nguyen break;
16974e83fc93SBruce Allan fallthrough;
1698c7648810STony Nguyen default:
1699c7648810STony Nguyen mutex_lock(&ice_global_cfg_lock_sw);
1700c7648810STony Nguyen lock_acquired = true;
1701c7648810STony Nguyen break;
1702c7648810STony Nguyen }
1703c7648810STony Nguyen
17043056df93SChinh T Cao status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd);
1705c7648810STony Nguyen if (lock_acquired)
1706c7648810STony Nguyen mutex_unlock(&ice_global_cfg_lock_sw);
1707c7648810STony Nguyen
1708c7648810STony Nguyen return status;
17097ec59eeaSAnirudh Venkataramanan }
17107ec59eeaSAnirudh Venkataramanan
17117ec59eeaSAnirudh Venkataramanan /**
17127ec59eeaSAnirudh Venkataramanan * ice_aq_get_fw_ver
1713f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
17147ec59eeaSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
17157ec59eeaSAnirudh Venkataramanan *
17167ec59eeaSAnirudh Venkataramanan * Get the firmware version (0x0001) from the admin queue commands
17177ec59eeaSAnirudh Venkataramanan */
ice_aq_get_fw_ver(struct ice_hw * hw,struct ice_sq_cd * cd)17185e24d598STony Nguyen int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
17197ec59eeaSAnirudh Venkataramanan {
17207ec59eeaSAnirudh Venkataramanan struct ice_aqc_get_ver *resp;
17217ec59eeaSAnirudh Venkataramanan struct ice_aq_desc desc;
17225e24d598STony Nguyen int status;
17237ec59eeaSAnirudh Venkataramanan
17247ec59eeaSAnirudh Venkataramanan resp = &desc.params.get_ver;
17257ec59eeaSAnirudh Venkataramanan
17267ec59eeaSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
17277ec59eeaSAnirudh Venkataramanan
17287ec59eeaSAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
17297ec59eeaSAnirudh Venkataramanan
17307ec59eeaSAnirudh Venkataramanan if (!status) {
17317ec59eeaSAnirudh Venkataramanan hw->fw_branch = resp->fw_branch;
17327ec59eeaSAnirudh Venkataramanan hw->fw_maj_ver = resp->fw_major;
17337ec59eeaSAnirudh Venkataramanan hw->fw_min_ver = resp->fw_minor;
17347ec59eeaSAnirudh Venkataramanan hw->fw_patch = resp->fw_patch;
17357ec59eeaSAnirudh Venkataramanan hw->fw_build = le32_to_cpu(resp->fw_build);
17367ec59eeaSAnirudh Venkataramanan hw->api_branch = resp->api_branch;
17377ec59eeaSAnirudh Venkataramanan hw->api_maj_ver = resp->api_major;
17387ec59eeaSAnirudh Venkataramanan hw->api_min_ver = resp->api_minor;
17397ec59eeaSAnirudh Venkataramanan hw->api_patch = resp->api_patch;
17407ec59eeaSAnirudh Venkataramanan }
17417ec59eeaSAnirudh Venkataramanan
17427ec59eeaSAnirudh Venkataramanan return status;
17437ec59eeaSAnirudh Venkataramanan }
17447ec59eeaSAnirudh Venkataramanan
17457ec59eeaSAnirudh Venkataramanan /**
1746e3710a01SPaul M Stillwell Jr * ice_aq_send_driver_ver
1747e3710a01SPaul M Stillwell Jr * @hw: pointer to the HW struct
1748e3710a01SPaul M Stillwell Jr * @dv: driver's major, minor version
1749e3710a01SPaul M Stillwell Jr * @cd: pointer to command details structure or NULL
1750e3710a01SPaul M Stillwell Jr *
1751e3710a01SPaul M Stillwell Jr * Send the driver version (0x0002) to the firmware
1752e3710a01SPaul M Stillwell Jr */
17535e24d598STony Nguyen int
ice_aq_send_driver_ver(struct ice_hw * hw,struct ice_driver_ver * dv,struct ice_sq_cd * cd)1754e3710a01SPaul M Stillwell Jr ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1755e3710a01SPaul M Stillwell Jr struct ice_sq_cd *cd)
1756e3710a01SPaul M Stillwell Jr {
1757e3710a01SPaul M Stillwell Jr struct ice_aqc_driver_ver *cmd;
1758e3710a01SPaul M Stillwell Jr struct ice_aq_desc desc;
1759e3710a01SPaul M Stillwell Jr u16 len;
1760e3710a01SPaul M Stillwell Jr
1761e3710a01SPaul M Stillwell Jr cmd = &desc.params.driver_ver;
1762e3710a01SPaul M Stillwell Jr
1763e3710a01SPaul M Stillwell Jr if (!dv)
1764d54699e2STony Nguyen return -EINVAL;
1765e3710a01SPaul M Stillwell Jr
1766e3710a01SPaul M Stillwell Jr ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1767e3710a01SPaul M Stillwell Jr
1768e3710a01SPaul M Stillwell Jr desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1769e3710a01SPaul M Stillwell Jr cmd->major_ver = dv->major_ver;
1770e3710a01SPaul M Stillwell Jr cmd->minor_ver = dv->minor_ver;
1771e3710a01SPaul M Stillwell Jr cmd->build_ver = dv->build_ver;
1772e3710a01SPaul M Stillwell Jr cmd->subbuild_ver = dv->subbuild_ver;
1773e3710a01SPaul M Stillwell Jr
1774e3710a01SPaul M Stillwell Jr len = 0;
1775e3710a01SPaul M Stillwell Jr while (len < sizeof(dv->driver_string) &&
1776e3710a01SPaul M Stillwell Jr isascii(dv->driver_string[len]) && dv->driver_string[len])
1777e3710a01SPaul M Stillwell Jr len++;
1778e3710a01SPaul M Stillwell Jr
1779e3710a01SPaul M Stillwell Jr return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1780e3710a01SPaul M Stillwell Jr }
1781e3710a01SPaul M Stillwell Jr
1782e3710a01SPaul M Stillwell Jr /**
17837ec59eeaSAnirudh Venkataramanan * ice_aq_q_shutdown
1784f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
17857ec59eeaSAnirudh Venkataramanan * @unloading: is the driver unloading itself
17867ec59eeaSAnirudh Venkataramanan *
17877ec59eeaSAnirudh Venkataramanan * Tell the Firmware that we're shutting down the AdminQ and whether
17887ec59eeaSAnirudh Venkataramanan * or not the driver is unloading as well (0x0003).
17897ec59eeaSAnirudh Venkataramanan */
ice_aq_q_shutdown(struct ice_hw * hw,bool unloading)17905e24d598STony Nguyen int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
17917ec59eeaSAnirudh Venkataramanan {
17927ec59eeaSAnirudh Venkataramanan struct ice_aqc_q_shutdown *cmd;
17937ec59eeaSAnirudh Venkataramanan struct ice_aq_desc desc;
17947ec59eeaSAnirudh Venkataramanan
17957ec59eeaSAnirudh Venkataramanan cmd = &desc.params.q_shutdown;
17967ec59eeaSAnirudh Venkataramanan
17977ec59eeaSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
17987ec59eeaSAnirudh Venkataramanan
17997ec59eeaSAnirudh Venkataramanan if (unloading)
18007404e84aSBruce Allan cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
18017ec59eeaSAnirudh Venkataramanan
18027ec59eeaSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
18037ec59eeaSAnirudh Venkataramanan }
1804f31e4b6fSAnirudh Venkataramanan
1805f31e4b6fSAnirudh Venkataramanan /**
1806f31e4b6fSAnirudh Venkataramanan * ice_aq_req_res
1807f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
1808f9867df6SAnirudh Venkataramanan * @res: resource ID
1809f31e4b6fSAnirudh Venkataramanan * @access: access type
1810f31e4b6fSAnirudh Venkataramanan * @sdp_number: resource number
1811f31e4b6fSAnirudh Venkataramanan * @timeout: the maximum time in ms that the driver may hold the resource
1812f31e4b6fSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
1813f31e4b6fSAnirudh Venkataramanan *
1814ff2b1321SDan Nowlin * Requests common resource using the admin queue commands (0x0008).
1815ff2b1321SDan Nowlin * When attempting to acquire the Global Config Lock, the driver can
1816ff2b1321SDan Nowlin * learn of three states:
1817d54699e2STony Nguyen * 1) 0 - acquired lock, and can perform download package
1818d54699e2STony Nguyen * 2) -EIO - did not get lock, driver should fail to load
1819d54699e2STony Nguyen * 3) -EALREADY - did not get lock, but another driver has
1820ff2b1321SDan Nowlin * successfully downloaded the package; the driver does
1821ff2b1321SDan Nowlin * not have to download the package and can continue
1822ff2b1321SDan Nowlin * loading
1823ff2b1321SDan Nowlin *
1824ff2b1321SDan Nowlin * Note that if the caller is in an acquire lock, perform action, release lock
1825ff2b1321SDan Nowlin * phase of operation, it is possible that the FW may detect a timeout and issue
1826ff2b1321SDan Nowlin * a CORER. In this case, the driver will receive a CORER interrupt and will
1827ff2b1321SDan Nowlin * have to determine its cause. The calling thread that is handling this flow
1828ff2b1321SDan Nowlin * will likely get an error propagated back to it indicating the Download
1829ff2b1321SDan Nowlin * Package, Update Package or the Release Resource AQ commands timed out.
1830f31e4b6fSAnirudh Venkataramanan */
18315e24d598STony Nguyen static int
ice_aq_req_res(struct ice_hw * hw,enum ice_aq_res_ids res,enum ice_aq_res_access_type access,u8 sdp_number,u32 * timeout,struct ice_sq_cd * cd)1832f31e4b6fSAnirudh Venkataramanan ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1833f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1834f31e4b6fSAnirudh Venkataramanan struct ice_sq_cd *cd)
1835f31e4b6fSAnirudh Venkataramanan {
1836f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res *cmd_resp;
1837f31e4b6fSAnirudh Venkataramanan struct ice_aq_desc desc;
18385e24d598STony Nguyen int status;
1839f31e4b6fSAnirudh Venkataramanan
1840f31e4b6fSAnirudh Venkataramanan cmd_resp = &desc.params.res_owner;
1841f31e4b6fSAnirudh Venkataramanan
1842f31e4b6fSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1843f31e4b6fSAnirudh Venkataramanan
1844f31e4b6fSAnirudh Venkataramanan cmd_resp->res_id = cpu_to_le16(res);
1845f31e4b6fSAnirudh Venkataramanan cmd_resp->access_type = cpu_to_le16(access);
1846f31e4b6fSAnirudh Venkataramanan cmd_resp->res_number = cpu_to_le32(sdp_number);
1847ff2b1321SDan Nowlin cmd_resp->timeout = cpu_to_le32(*timeout);
1848ff2b1321SDan Nowlin *timeout = 0;
1849f31e4b6fSAnirudh Venkataramanan
1850f31e4b6fSAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1851ff2b1321SDan Nowlin
1852f31e4b6fSAnirudh Venkataramanan /* The completion specifies the maximum time in ms that the driver
1853f31e4b6fSAnirudh Venkataramanan * may hold the resource in the Timeout field.
1854ff2b1321SDan Nowlin */
1855ff2b1321SDan Nowlin
1856ff2b1321SDan Nowlin /* Global config lock response utilizes an additional status field.
1857ff2b1321SDan Nowlin *
1858ff2b1321SDan Nowlin * If the Global config lock resource is held by some other driver, the
1859ff2b1321SDan Nowlin * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1860ff2b1321SDan Nowlin * and the timeout field indicates the maximum time the current owner
1861ff2b1321SDan Nowlin * of the resource has to free it.
1862ff2b1321SDan Nowlin */
1863ff2b1321SDan Nowlin if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1864ff2b1321SDan Nowlin if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1865ff2b1321SDan Nowlin *timeout = le32_to_cpu(cmd_resp->timeout);
1866ff2b1321SDan Nowlin return 0;
1867ff2b1321SDan Nowlin } else if (le16_to_cpu(cmd_resp->status) ==
1868ff2b1321SDan Nowlin ICE_AQ_RES_GLBL_IN_PROG) {
1869ff2b1321SDan Nowlin *timeout = le32_to_cpu(cmd_resp->timeout);
1870d54699e2STony Nguyen return -EIO;
1871ff2b1321SDan Nowlin } else if (le16_to_cpu(cmd_resp->status) ==
1872ff2b1321SDan Nowlin ICE_AQ_RES_GLBL_DONE) {
1873d54699e2STony Nguyen return -EALREADY;
1874ff2b1321SDan Nowlin }
1875ff2b1321SDan Nowlin
1876ff2b1321SDan Nowlin /* invalid FW response, force a timeout immediately */
1877ff2b1321SDan Nowlin *timeout = 0;
1878d54699e2STony Nguyen return -EIO;
1879ff2b1321SDan Nowlin }
1880ff2b1321SDan Nowlin
1881ff2b1321SDan Nowlin /* If the resource is held by some other driver, the command completes
1882ff2b1321SDan Nowlin * with a busy return value and the timeout field indicates the maximum
1883ff2b1321SDan Nowlin * time the current owner of the resource has to free it.
1884f31e4b6fSAnirudh Venkataramanan */
1885f31e4b6fSAnirudh Venkataramanan if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1886f31e4b6fSAnirudh Venkataramanan *timeout = le32_to_cpu(cmd_resp->timeout);
1887f31e4b6fSAnirudh Venkataramanan
1888f31e4b6fSAnirudh Venkataramanan return status;
1889f31e4b6fSAnirudh Venkataramanan }
1890f31e4b6fSAnirudh Venkataramanan
1891f31e4b6fSAnirudh Venkataramanan /**
1892f31e4b6fSAnirudh Venkataramanan * ice_aq_release_res
1893f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
1894f9867df6SAnirudh Venkataramanan * @res: resource ID
1895f31e4b6fSAnirudh Venkataramanan * @sdp_number: resource number
1896f31e4b6fSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
1897f31e4b6fSAnirudh Venkataramanan *
1898f31e4b6fSAnirudh Venkataramanan * release common resource using the admin queue commands (0x0009)
1899f31e4b6fSAnirudh Venkataramanan */
19005e24d598STony Nguyen static int
ice_aq_release_res(struct ice_hw * hw,enum ice_aq_res_ids res,u8 sdp_number,struct ice_sq_cd * cd)1901f31e4b6fSAnirudh Venkataramanan ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1902f31e4b6fSAnirudh Venkataramanan struct ice_sq_cd *cd)
1903f31e4b6fSAnirudh Venkataramanan {
1904f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res *cmd;
1905f31e4b6fSAnirudh Venkataramanan struct ice_aq_desc desc;
1906f31e4b6fSAnirudh Venkataramanan
1907f31e4b6fSAnirudh Venkataramanan cmd = &desc.params.res_owner;
1908f31e4b6fSAnirudh Venkataramanan
1909f31e4b6fSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1910f31e4b6fSAnirudh Venkataramanan
1911f31e4b6fSAnirudh Venkataramanan cmd->res_id = cpu_to_le16(res);
1912f31e4b6fSAnirudh Venkataramanan cmd->res_number = cpu_to_le32(sdp_number);
1913f31e4b6fSAnirudh Venkataramanan
1914f31e4b6fSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1915f31e4b6fSAnirudh Venkataramanan }
1916f31e4b6fSAnirudh Venkataramanan
1917f31e4b6fSAnirudh Venkataramanan /**
1918f31e4b6fSAnirudh Venkataramanan * ice_acquire_res
1919f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the HW structure
1920f9867df6SAnirudh Venkataramanan * @res: resource ID
1921f31e4b6fSAnirudh Venkataramanan * @access: access type (read or write)
1922ff2b1321SDan Nowlin * @timeout: timeout in milliseconds
1923f31e4b6fSAnirudh Venkataramanan *
1924f31e4b6fSAnirudh Venkataramanan * This function will attempt to acquire the ownership of a resource.
1925f31e4b6fSAnirudh Venkataramanan */
19265e24d598STony Nguyen int
ice_acquire_res(struct ice_hw * hw,enum ice_aq_res_ids res,enum ice_aq_res_access_type access,u32 timeout)1927f31e4b6fSAnirudh Venkataramanan ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1928ff2b1321SDan Nowlin enum ice_aq_res_access_type access, u32 timeout)
1929f31e4b6fSAnirudh Venkataramanan {
1930f31e4b6fSAnirudh Venkataramanan #define ICE_RES_POLLING_DELAY_MS 10
1931f31e4b6fSAnirudh Venkataramanan u32 delay = ICE_RES_POLLING_DELAY_MS;
1932ff2b1321SDan Nowlin u32 time_left = timeout;
19335e24d598STony Nguyen int status;
1934f31e4b6fSAnirudh Venkataramanan
1935f31e4b6fSAnirudh Venkataramanan status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1936f31e4b6fSAnirudh Venkataramanan
1937d54699e2STony Nguyen /* A return code of -EALREADY means that another driver has
1938ff2b1321SDan Nowlin * previously acquired the resource and performed any necessary updates;
1939ff2b1321SDan Nowlin * in this case the caller does not obtain the resource and has no
1940ff2b1321SDan Nowlin * further work to do.
1941f31e4b6fSAnirudh Venkataramanan */
1942d54699e2STony Nguyen if (status == -EALREADY)
1943f31e4b6fSAnirudh Venkataramanan goto ice_acquire_res_exit;
1944f31e4b6fSAnirudh Venkataramanan
1945f31e4b6fSAnirudh Venkataramanan if (status)
19469228d8b2SJacob Keller ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access);
1947f31e4b6fSAnirudh Venkataramanan
1948f31e4b6fSAnirudh Venkataramanan /* If necessary, poll until the current lock owner timeouts */
1949f31e4b6fSAnirudh Venkataramanan timeout = time_left;
1950f31e4b6fSAnirudh Venkataramanan while (status && timeout && time_left) {
1951f31e4b6fSAnirudh Venkataramanan mdelay(delay);
1952f31e4b6fSAnirudh Venkataramanan timeout = (timeout > delay) ? timeout - delay : 0;
1953f31e4b6fSAnirudh Venkataramanan status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1954f31e4b6fSAnirudh Venkataramanan
1955d54699e2STony Nguyen if (status == -EALREADY)
1956f31e4b6fSAnirudh Venkataramanan /* lock free, but no work to do */
1957f31e4b6fSAnirudh Venkataramanan break;
1958f31e4b6fSAnirudh Venkataramanan
1959f31e4b6fSAnirudh Venkataramanan if (!status)
1960f31e4b6fSAnirudh Venkataramanan /* lock acquired */
1961f31e4b6fSAnirudh Venkataramanan break;
1962f31e4b6fSAnirudh Venkataramanan }
1963d54699e2STony Nguyen if (status && status != -EALREADY)
1964f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1965f31e4b6fSAnirudh Venkataramanan
1966f31e4b6fSAnirudh Venkataramanan ice_acquire_res_exit:
1967d54699e2STony Nguyen if (status == -EALREADY) {
1968f31e4b6fSAnirudh Venkataramanan if (access == ICE_RES_WRITE)
19699228d8b2SJacob Keller ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n");
1970f31e4b6fSAnirudh Venkataramanan else
1971d54699e2STony Nguyen ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n");
1972f31e4b6fSAnirudh Venkataramanan }
1973f31e4b6fSAnirudh Venkataramanan return status;
1974f31e4b6fSAnirudh Venkataramanan }
1975f31e4b6fSAnirudh Venkataramanan
1976f31e4b6fSAnirudh Venkataramanan /**
1977f31e4b6fSAnirudh Venkataramanan * ice_release_res
1978f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the HW structure
1979f9867df6SAnirudh Venkataramanan * @res: resource ID
1980f31e4b6fSAnirudh Venkataramanan *
1981f31e4b6fSAnirudh Venkataramanan * This function will release a resource using the proper Admin Command.
1982f31e4b6fSAnirudh Venkataramanan */
ice_release_res(struct ice_hw * hw,enum ice_aq_res_ids res)1983f31e4b6fSAnirudh Venkataramanan void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1984f31e4b6fSAnirudh Venkataramanan {
1985f86d6f9cSMichal Schmidt unsigned long timeout;
19865518ac2aSTony Nguyen int status;
1987f31e4b6fSAnirudh Venkataramanan
1988f31e4b6fSAnirudh Venkataramanan /* there are some rare cases when trying to release the resource
1989f9867df6SAnirudh Venkataramanan * results in an admin queue timeout, so handle them correctly
1990f31e4b6fSAnirudh Venkataramanan */
1991f86d6f9cSMichal Schmidt timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT;
1992f86d6f9cSMichal Schmidt do {
1993f31e4b6fSAnirudh Venkataramanan status = ice_aq_release_res(hw, res, 0, NULL);
1994f86d6f9cSMichal Schmidt if (status != -EIO)
1995f86d6f9cSMichal Schmidt break;
1996f86d6f9cSMichal Schmidt usleep_range(1000, 2000);
1997f86d6f9cSMichal Schmidt } while (time_before(jiffies, timeout));
1998f31e4b6fSAnirudh Venkataramanan }
1999f31e4b6fSAnirudh Venkataramanan
2000f31e4b6fSAnirudh Venkataramanan /**
200131ad4e4eSTony Nguyen * ice_aq_alloc_free_res - command to allocate/free resources
200231ad4e4eSTony Nguyen * @hw: pointer to the HW struct
200331ad4e4eSTony Nguyen * @buf: Indirect buffer to hold data parameters and response
200431ad4e4eSTony Nguyen * @buf_size: size of buffer for indirect commands
200531ad4e4eSTony Nguyen * @opc: pass in the command opcode
200631ad4e4eSTony Nguyen *
200731ad4e4eSTony Nguyen * Helper function to allocate/free resources using the admin queue commands
200831ad4e4eSTony Nguyen */
ice_aq_alloc_free_res(struct ice_hw * hw,struct ice_aqc_alloc_free_res_elem * buf,u16 buf_size,enum ice_adminq_opc opc)2009*52da2fb2SPrzemek Kitszel int ice_aq_alloc_free_res(struct ice_hw *hw,
201031ad4e4eSTony Nguyen struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
2011*52da2fb2SPrzemek Kitszel enum ice_adminq_opc opc)
201231ad4e4eSTony Nguyen {
201331ad4e4eSTony Nguyen struct ice_aqc_alloc_free_res_cmd *cmd;
201431ad4e4eSTony Nguyen struct ice_aq_desc desc;
201531ad4e4eSTony Nguyen
201631ad4e4eSTony Nguyen cmd = &desc.params.sw_res_ctrl;
201731ad4e4eSTony Nguyen
2018*52da2fb2SPrzemek Kitszel if (!buf || buf_size < flex_array_size(buf, elem, 1))
2019d54699e2STony Nguyen return -EINVAL;
202031ad4e4eSTony Nguyen
202131ad4e4eSTony Nguyen ice_fill_dflt_direct_cmd_desc(&desc, opc);
202231ad4e4eSTony Nguyen
202331ad4e4eSTony Nguyen desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
202431ad4e4eSTony Nguyen
2025*52da2fb2SPrzemek Kitszel cmd->num_entries = cpu_to_le16(1);
202631ad4e4eSTony Nguyen
2027*52da2fb2SPrzemek Kitszel return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL);
202831ad4e4eSTony Nguyen }
202931ad4e4eSTony Nguyen
203031ad4e4eSTony Nguyen /**
203131ad4e4eSTony Nguyen * ice_alloc_hw_res - allocate resource
203231ad4e4eSTony Nguyen * @hw: pointer to the HW struct
203331ad4e4eSTony Nguyen * @type: type of resource
203431ad4e4eSTony Nguyen * @num: number of resources to allocate
203531ad4e4eSTony Nguyen * @btm: allocate from bottom
203631ad4e4eSTony Nguyen * @res: pointer to array that will receive the resources
203731ad4e4eSTony Nguyen */
20385e24d598STony Nguyen int
ice_alloc_hw_res(struct ice_hw * hw,u16 type,u16 num,bool btm,u16 * res)203931ad4e4eSTony Nguyen ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
204031ad4e4eSTony Nguyen {
204131ad4e4eSTony Nguyen struct ice_aqc_alloc_free_res_elem *buf;
204231ad4e4eSTony Nguyen u16 buf_len;
20435518ac2aSTony Nguyen int status;
204431ad4e4eSTony Nguyen
204566486d89SBruce Allan buf_len = struct_size(buf, elem, num);
204631ad4e4eSTony Nguyen buf = kzalloc(buf_len, GFP_KERNEL);
204731ad4e4eSTony Nguyen if (!buf)
2048d54699e2STony Nguyen return -ENOMEM;
204931ad4e4eSTony Nguyen
205031ad4e4eSTony Nguyen /* Prepare buffer to allocate resource. */
205131ad4e4eSTony Nguyen buf->num_elems = cpu_to_le16(num);
205231ad4e4eSTony Nguyen buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
205331ad4e4eSTony Nguyen ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
205431ad4e4eSTony Nguyen if (btm)
205531ad4e4eSTony Nguyen buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
205631ad4e4eSTony Nguyen
2057*52da2fb2SPrzemek Kitszel status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res);
205831ad4e4eSTony Nguyen if (status)
205931ad4e4eSTony Nguyen goto ice_alloc_res_exit;
206031ad4e4eSTony Nguyen
206166486d89SBruce Allan memcpy(res, buf->elem, sizeof(*buf->elem) * num);
206231ad4e4eSTony Nguyen
206331ad4e4eSTony Nguyen ice_alloc_res_exit:
206431ad4e4eSTony Nguyen kfree(buf);
206531ad4e4eSTony Nguyen return status;
206631ad4e4eSTony Nguyen }
206731ad4e4eSTony Nguyen
206831ad4e4eSTony Nguyen /**
2069451f2c44STony Nguyen * ice_free_hw_res - free allocated HW resource
2070451f2c44STony Nguyen * @hw: pointer to the HW struct
2071451f2c44STony Nguyen * @type: type of resource to free
2072451f2c44STony Nguyen * @num: number of resources
2073451f2c44STony Nguyen * @res: pointer to array that contains the resources to free
2074451f2c44STony Nguyen */
ice_free_hw_res(struct ice_hw * hw,u16 type,u16 num,u16 * res)20755e24d598STony Nguyen int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
2076451f2c44STony Nguyen {
2077451f2c44STony Nguyen struct ice_aqc_alloc_free_res_elem *buf;
2078451f2c44STony Nguyen u16 buf_len;
20795518ac2aSTony Nguyen int status;
2080451f2c44STony Nguyen
208166486d89SBruce Allan buf_len = struct_size(buf, elem, num);
2082451f2c44STony Nguyen buf = kzalloc(buf_len, GFP_KERNEL);
2083451f2c44STony Nguyen if (!buf)
2084d54699e2STony Nguyen return -ENOMEM;
2085451f2c44STony Nguyen
2086451f2c44STony Nguyen /* Prepare buffer to free resource. */
2087451f2c44STony Nguyen buf->num_elems = cpu_to_le16(num);
2088451f2c44STony Nguyen buf->res_type = cpu_to_le16(type);
208966486d89SBruce Allan memcpy(buf->elem, res, sizeof(*buf->elem) * num);
2090451f2c44STony Nguyen
2091*52da2fb2SPrzemek Kitszel status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res);
2092451f2c44STony Nguyen if (status)
2093451f2c44STony Nguyen ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
2094451f2c44STony Nguyen
2095451f2c44STony Nguyen kfree(buf);
2096451f2c44STony Nguyen return status;
2097451f2c44STony Nguyen }
2098451f2c44STony Nguyen
2099451f2c44STony Nguyen /**
21007a1f7111SBrett Creeley * ice_get_num_per_func - determine number of resources per PF
2101f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW structure
21027a1f7111SBrett Creeley * @max: value to be evenly split between each PF
2103995c90f2SAnirudh Venkataramanan *
2104995c90f2SAnirudh Venkataramanan * Determine the number of valid functions by going through the bitmap returned
21057a1f7111SBrett Creeley * from parsing capabilities and use this to calculate the number of resources
21067a1f7111SBrett Creeley * per PF based on the max value passed in.
2107995c90f2SAnirudh Venkataramanan */
ice_get_num_per_func(struct ice_hw * hw,u32 max)21087a1f7111SBrett Creeley static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
2109995c90f2SAnirudh Venkataramanan {
2110995c90f2SAnirudh Venkataramanan u8 funcs;
2111995c90f2SAnirudh Venkataramanan
2112995c90f2SAnirudh Venkataramanan #define ICE_CAPS_VALID_FUNCS_M 0xFF
2113995c90f2SAnirudh Venkataramanan funcs = hweight8(hw->dev_caps.common_cap.valid_functions &
2114995c90f2SAnirudh Venkataramanan ICE_CAPS_VALID_FUNCS_M);
2115995c90f2SAnirudh Venkataramanan
2116995c90f2SAnirudh Venkataramanan if (!funcs)
2117995c90f2SAnirudh Venkataramanan return 0;
2118995c90f2SAnirudh Venkataramanan
21197a1f7111SBrett Creeley return max / funcs;
2120995c90f2SAnirudh Venkataramanan }
2121995c90f2SAnirudh Venkataramanan
2122995c90f2SAnirudh Venkataramanan /**
2123595b13e2SJacob Keller * ice_parse_common_caps - parse common device/function capabilities
2124f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
2125595b13e2SJacob Keller * @caps: pointer to common capabilities structure
2126595b13e2SJacob Keller * @elem: the capability element to parse
2127595b13e2SJacob Keller * @prefix: message prefix for tracing capabilities
21289c20346bSAnirudh Venkataramanan *
2129595b13e2SJacob Keller * Given a capability element, extract relevant details into the common
2130595b13e2SJacob Keller * capability structure.
2131595b13e2SJacob Keller *
2132595b13e2SJacob Keller * Returns: true if the capability matches one of the common capability ids,
2133595b13e2SJacob Keller * false otherwise.
21349c20346bSAnirudh Venkataramanan */
2135595b13e2SJacob Keller static bool
ice_parse_common_caps(struct ice_hw * hw,struct ice_hw_common_caps * caps,struct ice_aqc_list_caps_elem * elem,const char * prefix)2136595b13e2SJacob Keller ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
2137595b13e2SJacob Keller struct ice_aqc_list_caps_elem *elem, const char *prefix)
21389c20346bSAnirudh Venkataramanan {
2139595b13e2SJacob Keller u32 logical_id = le32_to_cpu(elem->logical_id);
2140595b13e2SJacob Keller u32 phys_id = le32_to_cpu(elem->phys_id);
2141595b13e2SJacob Keller u32 number = le32_to_cpu(elem->number);
2142595b13e2SJacob Keller u16 cap = le16_to_cpu(elem->cap);
2143595b13e2SJacob Keller bool found = true;
21449c20346bSAnirudh Venkataramanan
21459c20346bSAnirudh Venkataramanan switch (cap) {
2146995c90f2SAnirudh Venkataramanan case ICE_AQC_CAPS_VALID_FUNCTIONS:
2147995c90f2SAnirudh Venkataramanan caps->valid_functions = number;
21489228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,
2149995c90f2SAnirudh Venkataramanan caps->valid_functions);
2150995c90f2SAnirudh Venkataramanan break;
215175d2b253SAnirudh Venkataramanan case ICE_AQC_CAPS_SRIOV:
215275d2b253SAnirudh Venkataramanan caps->sr_iov_1_1 = (number == 1);
21539228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix,
2154a84db525SAnirudh Venkataramanan caps->sr_iov_1_1);
215575d2b253SAnirudh Venkataramanan break;
2156a257f188SUsha Ketineni case ICE_AQC_CAPS_DCB:
2157a257f188SUsha Ketineni caps->dcb = (number == 1);
2158a257f188SUsha Ketineni caps->active_tc_bitmap = logical_id;
2159a257f188SUsha Ketineni caps->maxtc = phys_id;
21609228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);
21619228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,
2162a257f188SUsha Ketineni caps->active_tc_bitmap);
21639228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);
2164a257f188SUsha Ketineni break;
21659c20346bSAnirudh Venkataramanan case ICE_AQC_CAPS_RSS:
21669c20346bSAnirudh Venkataramanan caps->rss_table_size = number;
21679c20346bSAnirudh Venkataramanan caps->rss_table_entry_width = logical_id;
21689228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,
21699c20346bSAnirudh Venkataramanan caps->rss_table_size);
21709228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,
21719c20346bSAnirudh Venkataramanan caps->rss_table_entry_width);
21729c20346bSAnirudh Venkataramanan break;
21739c20346bSAnirudh Venkataramanan case ICE_AQC_CAPS_RXQS:
21749c20346bSAnirudh Venkataramanan caps->num_rxq = number;
21759c20346bSAnirudh Venkataramanan caps->rxq_first_id = phys_id;
21769228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,
2177a84db525SAnirudh Venkataramanan caps->num_rxq);
21789228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,
21799c20346bSAnirudh Venkataramanan caps->rxq_first_id);
21809c20346bSAnirudh Venkataramanan break;
21819c20346bSAnirudh Venkataramanan case ICE_AQC_CAPS_TXQS:
21829c20346bSAnirudh Venkataramanan caps->num_txq = number;
21839c20346bSAnirudh Venkataramanan caps->txq_first_id = phys_id;
21849228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
2185a84db525SAnirudh Venkataramanan caps->num_txq);
21869228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,
21879c20346bSAnirudh Venkataramanan caps->txq_first_id);
21889c20346bSAnirudh Venkataramanan break;
21899c20346bSAnirudh Venkataramanan case ICE_AQC_CAPS_MSIX:
21909c20346bSAnirudh Venkataramanan caps->num_msix_vectors = number;
21919c20346bSAnirudh Venkataramanan caps->msix_vector_first_id = phys_id;
21929228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,
21939c20346bSAnirudh Venkataramanan caps->num_msix_vectors);
21949228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,
21959c20346bSAnirudh Venkataramanan caps->msix_vector_first_id);
21969c20346bSAnirudh Venkataramanan break;
21972ab560a7SJacob Keller case ICE_AQC_CAPS_PENDING_NVM_VER:
21982ab560a7SJacob Keller caps->nvm_update_pending_nvm = true;
21992ab560a7SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix);
22002ab560a7SJacob Keller break;
22012ab560a7SJacob Keller case ICE_AQC_CAPS_PENDING_OROM_VER:
22022ab560a7SJacob Keller caps->nvm_update_pending_orom = true;
22032ab560a7SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix);
22042ab560a7SJacob Keller break;
22052ab560a7SJacob Keller case ICE_AQC_CAPS_PENDING_NET_VER:
22062ab560a7SJacob Keller caps->nvm_update_pending_netlist = true;
22072ab560a7SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix);
22082ab560a7SJacob Keller break;
2209de9b277eSJacek Naczyk case ICE_AQC_CAPS_NVM_MGMT:
2210de9b277eSJacek Naczyk caps->nvm_unified_update =
2211de9b277eSJacek Naczyk (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
2212de9b277eSJacek Naczyk true : false;
2213de9b277eSJacek Naczyk ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
2214de9b277eSJacek Naczyk caps->nvm_unified_update);
2215de9b277eSJacek Naczyk break;
2216d25a0fc4SDave Ertman case ICE_AQC_CAPS_RDMA:
2217d25a0fc4SDave Ertman caps->rdma = (number == 1);
2218d25a0fc4SDave Ertman ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma);
2219d25a0fc4SDave Ertman break;
2220595b13e2SJacob Keller case ICE_AQC_CAPS_MAX_MTU:
2221595b13e2SJacob Keller caps->max_mtu = number;
2222595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
2223595b13e2SJacob Keller prefix, caps->max_mtu);
2224595b13e2SJacob Keller break;
2225399e27dbSJacob Keller case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE:
2226399e27dbSJacob Keller caps->pcie_reset_avoidance = (number > 0);
2227399e27dbSJacob Keller ice_debug(hw, ICE_DBG_INIT,
2228399e27dbSJacob Keller "%s: pcie_reset_avoidance = %d\n", prefix,
2229399e27dbSJacob Keller caps->pcie_reset_avoidance);
2230399e27dbSJacob Keller break;
2231399e27dbSJacob Keller case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT:
2232399e27dbSJacob Keller caps->reset_restrict_support = (number == 1);
2233399e27dbSJacob Keller ice_debug(hw, ICE_DBG_INIT,
2234399e27dbSJacob Keller "%s: reset_restrict_support = %d\n", prefix,
2235399e27dbSJacob Keller caps->reset_restrict_support);
2236399e27dbSJacob Keller break;
2237bb52f42aSDave Ertman case ICE_AQC_CAPS_FW_LAG_SUPPORT:
2238bb52f42aSDave Ertman caps->roce_lag = !!(number & ICE_AQC_BIT_ROCEV2_LAG);
2239bb52f42aSDave Ertman ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n",
2240bb52f42aSDave Ertman prefix, caps->roce_lag);
2241bb52f42aSDave Ertman caps->sriov_lag = !!(number & ICE_AQC_BIT_SRIOV_LAG);
2242bb52f42aSDave Ertman ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n",
2243bb52f42aSDave Ertman prefix, caps->sriov_lag);
2244bb52f42aSDave Ertman break;
2245595b13e2SJacob Keller default:
2246595b13e2SJacob Keller /* Not one of the recognized common capabilities */
2247595b13e2SJacob Keller found = false;
2248148beb61SHenry Tieman }
2249595b13e2SJacob Keller
2250595b13e2SJacob Keller return found;
2251595b13e2SJacob Keller }
2252595b13e2SJacob Keller
2253595b13e2SJacob Keller /**
2254595b13e2SJacob Keller * ice_recalc_port_limited_caps - Recalculate port limited capabilities
2255595b13e2SJacob Keller * @hw: pointer to the HW structure
2256595b13e2SJacob Keller * @caps: pointer to capabilities structure to fix
2257595b13e2SJacob Keller *
2258595b13e2SJacob Keller * Re-calculate the capabilities that are dependent on the number of physical
2259595b13e2SJacob Keller * ports; i.e. some features are not supported or function differently on
2260595b13e2SJacob Keller * devices with more than 4 ports.
2261595b13e2SJacob Keller */
2262595b13e2SJacob Keller static void
ice_recalc_port_limited_caps(struct ice_hw * hw,struct ice_hw_common_caps * caps)2263595b13e2SJacob Keller ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
2264595b13e2SJacob Keller {
2265595b13e2SJacob Keller /* This assumes device capabilities are always scanned before function
2266595b13e2SJacob Keller * capabilities during the initialization flow.
2267595b13e2SJacob Keller */
2268595b13e2SJacob Keller if (hw->dev_caps.num_funcs > 4) {
2269595b13e2SJacob Keller /* Max 4 TCs per port */
2270595b13e2SJacob Keller caps->maxtc = 4;
22719228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",
2272595b13e2SJacob Keller caps->maxtc);
2273d25a0fc4SDave Ertman if (caps->rdma) {
2274d25a0fc4SDave Ertman ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n");
2275d25a0fc4SDave Ertman caps->rdma = 0;
2276d25a0fc4SDave Ertman }
2277d25a0fc4SDave Ertman
2278d25a0fc4SDave Ertman /* print message only when processing device capabilities
2279d25a0fc4SDave Ertman * during initialization.
2280d25a0fc4SDave Ertman */
2281d25a0fc4SDave Ertman if (caps == &hw->dev_caps.common_cap)
2282d25a0fc4SDave Ertman dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n");
2283595b13e2SJacob Keller }
2284595b13e2SJacob Keller }
2285595b13e2SJacob Keller
2286595b13e2SJacob Keller /**
2287595b13e2SJacob Keller * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps
2288595b13e2SJacob Keller * @hw: pointer to the HW struct
2289595b13e2SJacob Keller * @func_p: pointer to function capabilities structure
2290595b13e2SJacob Keller * @cap: pointer to the capability element to parse
2291595b13e2SJacob Keller *
2292595b13e2SJacob Keller * Extract function capabilities for ICE_AQC_CAPS_VF.
2293595b13e2SJacob Keller */
2294595b13e2SJacob Keller static void
ice_parse_vf_func_caps(struct ice_hw * hw,struct ice_hw_func_caps * func_p,struct ice_aqc_list_caps_elem * cap)2295595b13e2SJacob Keller ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2296595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap)
2297595b13e2SJacob Keller {
2298595b13e2SJacob Keller u32 logical_id = le32_to_cpu(cap->logical_id);
2299595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number);
2300595b13e2SJacob Keller
2301595b13e2SJacob Keller func_p->num_allocd_vfs = number;
2302595b13e2SJacob Keller func_p->vf_base_id = logical_id;
2303595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n",
2304595b13e2SJacob Keller func_p->num_allocd_vfs);
2305595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n",
2306595b13e2SJacob Keller func_p->vf_base_id);
2307595b13e2SJacob Keller }
2308595b13e2SJacob Keller
2309595b13e2SJacob Keller /**
2310595b13e2SJacob Keller * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
2311595b13e2SJacob Keller * @hw: pointer to the HW struct
2312595b13e2SJacob Keller * @func_p: pointer to function capabilities structure
2313595b13e2SJacob Keller * @cap: pointer to the capability element to parse
2314595b13e2SJacob Keller *
2315595b13e2SJacob Keller * Extract function capabilities for ICE_AQC_CAPS_VSI.
2316595b13e2SJacob Keller */
2317595b13e2SJacob Keller static void
ice_parse_vsi_func_caps(struct ice_hw * hw,struct ice_hw_func_caps * func_p,struct ice_aqc_list_caps_elem * cap)2318595b13e2SJacob Keller ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2319595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap)
2320595b13e2SJacob Keller {
2321595b13e2SJacob Keller func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
2322595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
2323595b13e2SJacob Keller le32_to_cpu(cap->number));
2324595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
2325595b13e2SJacob Keller func_p->guar_num_vsi);
2326595b13e2SJacob Keller }
2327595b13e2SJacob Keller
2328595b13e2SJacob Keller /**
23299733cc94SJacob Keller * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps
23309733cc94SJacob Keller * @hw: pointer to the HW struct
23319733cc94SJacob Keller * @func_p: pointer to function capabilities structure
23329733cc94SJacob Keller * @cap: pointer to the capability element to parse
23339733cc94SJacob Keller *
23349733cc94SJacob Keller * Extract function capabilities for ICE_AQC_CAPS_1588.
23359733cc94SJacob Keller */
23369733cc94SJacob Keller static void
ice_parse_1588_func_caps(struct ice_hw * hw,struct ice_hw_func_caps * func_p,struct ice_aqc_list_caps_elem * cap)23379733cc94SJacob Keller ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
23389733cc94SJacob Keller struct ice_aqc_list_caps_elem *cap)
23399733cc94SJacob Keller {
23409733cc94SJacob Keller struct ice_ts_func_info *info = &func_p->ts_func_info;
23419733cc94SJacob Keller u32 number = le32_to_cpu(cap->number);
23429733cc94SJacob Keller
23439733cc94SJacob Keller info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);
23449733cc94SJacob Keller func_p->common_cap.ieee_1588 = info->ena;
23459733cc94SJacob Keller
23469733cc94SJacob Keller info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0);
23479733cc94SJacob Keller info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0);
23489733cc94SJacob Keller info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
23499733cc94SJacob Keller info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);
23509733cc94SJacob Keller
23519733cc94SJacob Keller info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S;
23529733cc94SJacob Keller info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
23539733cc94SJacob Keller
2354405efa49SJacob Keller if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {
2355405efa49SJacob Keller info->time_ref = (enum ice_time_ref_freq)info->clk_freq;
2356405efa49SJacob Keller } else {
2357405efa49SJacob Keller /* Unknown clock frequency, so assume a (probably incorrect)
2358405efa49SJacob Keller * default to avoid out-of-bounds look ups of frequency
2359405efa49SJacob Keller * related information.
2360405efa49SJacob Keller */
2361405efa49SJacob Keller ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n",
2362405efa49SJacob Keller info->clk_freq);
2363405efa49SJacob Keller info->time_ref = ICE_TIME_REF_FREQ_25_000;
2364405efa49SJacob Keller }
2365405efa49SJacob Keller
23669733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
23679733cc94SJacob Keller func_p->common_cap.ieee_1588);
23689733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n",
23699733cc94SJacob Keller info->src_tmr_owned);
23709733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n",
23719733cc94SJacob Keller info->tmr_ena);
23729733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n",
23739733cc94SJacob Keller info->tmr_index_owned);
23749733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n",
23759733cc94SJacob Keller info->tmr_index_assoc);
23769733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n",
23779733cc94SJacob Keller info->clk_freq);
23789733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n",
23799733cc94SJacob Keller info->clk_src);
23809733cc94SJacob Keller }
23819733cc94SJacob Keller
23829733cc94SJacob Keller /**
2383595b13e2SJacob Keller * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
2384595b13e2SJacob Keller * @hw: pointer to the HW struct
2385595b13e2SJacob Keller * @func_p: pointer to function capabilities structure
2386595b13e2SJacob Keller *
2387595b13e2SJacob Keller * Extract function capabilities for ICE_AQC_CAPS_FD.
2388595b13e2SJacob Keller */
2389595b13e2SJacob Keller static void
ice_parse_fdir_func_caps(struct ice_hw * hw,struct ice_hw_func_caps * func_p)2390595b13e2SJacob Keller ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
2391595b13e2SJacob Keller {
2392148beb61SHenry Tieman u32 reg_val, val;
2393148beb61SHenry Tieman
2394148beb61SHenry Tieman reg_val = rd32(hw, GLQF_FD_SIZE);
2395148beb61SHenry Tieman val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
2396148beb61SHenry Tieman GLQF_FD_SIZE_FD_GSIZE_S;
2397148beb61SHenry Tieman func_p->fd_fltr_guar =
2398148beb61SHenry Tieman ice_get_num_per_func(hw, val);
2399148beb61SHenry Tieman val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
2400148beb61SHenry Tieman GLQF_FD_SIZE_FD_BSIZE_S;
2401148beb61SHenry Tieman func_p->fd_fltr_best_effort = val;
2402595b13e2SJacob Keller
24039228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",
2404595b13e2SJacob Keller func_p->fd_fltr_guar);
24059228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n",
2406595b13e2SJacob Keller func_p->fd_fltr_best_effort);
2407148beb61SHenry Tieman }
2408595b13e2SJacob Keller
2409595b13e2SJacob Keller /**
2410595b13e2SJacob Keller * ice_parse_func_caps - Parse function capabilities
2411595b13e2SJacob Keller * @hw: pointer to the HW struct
2412595b13e2SJacob Keller * @func_p: pointer to function capabilities structure
2413595b13e2SJacob Keller * @buf: buffer containing the function capability records
2414595b13e2SJacob Keller * @cap_count: the number of capabilities
2415595b13e2SJacob Keller *
2416595b13e2SJacob Keller * Helper function to parse function (0x000A) capabilities list. For
2417595b13e2SJacob Keller * capabilities shared between device and function, this relies on
2418595b13e2SJacob Keller * ice_parse_common_caps.
2419595b13e2SJacob Keller *
2420595b13e2SJacob Keller * Loop through the list of provided capabilities and extract the relevant
2421595b13e2SJacob Keller * data into the function capabilities structured.
2422595b13e2SJacob Keller */
2423595b13e2SJacob Keller static void
ice_parse_func_caps(struct ice_hw * hw,struct ice_hw_func_caps * func_p,void * buf,u32 cap_count)2424595b13e2SJacob Keller ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2425595b13e2SJacob Keller void *buf, u32 cap_count)
2426595b13e2SJacob Keller {
2427595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap_resp;
2428595b13e2SJacob Keller u32 i;
2429595b13e2SJacob Keller
24307a63dae0SBruce Allan cap_resp = buf;
2431595b13e2SJacob Keller
2432595b13e2SJacob Keller memset(func_p, 0, sizeof(*func_p));
2433595b13e2SJacob Keller
2434595b13e2SJacob Keller for (i = 0; i < cap_count; i++) {
2435595b13e2SJacob Keller u16 cap = le16_to_cpu(cap_resp[i].cap);
2436595b13e2SJacob Keller bool found;
2437595b13e2SJacob Keller
2438595b13e2SJacob Keller found = ice_parse_common_caps(hw, &func_p->common_cap,
2439595b13e2SJacob Keller &cap_resp[i], "func caps");
2440595b13e2SJacob Keller
2441595b13e2SJacob Keller switch (cap) {
2442595b13e2SJacob Keller case ICE_AQC_CAPS_VF:
2443595b13e2SJacob Keller ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]);
2444148beb61SHenry Tieman break;
2445595b13e2SJacob Keller case ICE_AQC_CAPS_VSI:
2446595b13e2SJacob Keller ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
2447595b13e2SJacob Keller break;
24489733cc94SJacob Keller case ICE_AQC_CAPS_1588:
24499733cc94SJacob Keller ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]);
24509733cc94SJacob Keller break;
2451595b13e2SJacob Keller case ICE_AQC_CAPS_FD:
2452595b13e2SJacob Keller ice_parse_fdir_func_caps(hw, func_p);
24539c20346bSAnirudh Venkataramanan break;
24549c20346bSAnirudh Venkataramanan default:
2455595b13e2SJacob Keller /* Don't list common capabilities as unknown */
2456595b13e2SJacob Keller if (!found)
24579228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n",
2458a84db525SAnirudh Venkataramanan i, cap);
24599c20346bSAnirudh Venkataramanan break;
24609c20346bSAnirudh Venkataramanan }
24619c20346bSAnirudh Venkataramanan }
24629164f761SBruce Allan
2463595b13e2SJacob Keller ice_recalc_port_limited_caps(hw, &func_p->common_cap);
24649164f761SBruce Allan }
2465595b13e2SJacob Keller
2466595b13e2SJacob Keller /**
2467595b13e2SJacob Keller * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2468595b13e2SJacob Keller * @hw: pointer to the HW struct
2469595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure
2470595b13e2SJacob Keller * @cap: capability element to parse
2471595b13e2SJacob Keller *
2472595b13e2SJacob Keller * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
2473595b13e2SJacob Keller */
2474595b13e2SJacob Keller static void
ice_parse_valid_functions_cap(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,struct ice_aqc_list_caps_elem * cap)2475595b13e2SJacob Keller ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2476595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap)
2477595b13e2SJacob Keller {
2478595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number);
2479595b13e2SJacob Keller
2480595b13e2SJacob Keller dev_p->num_funcs = hweight32(number);
2481595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
2482595b13e2SJacob Keller dev_p->num_funcs);
2483595b13e2SJacob Keller }
2484595b13e2SJacob Keller
2485595b13e2SJacob Keller /**
2486595b13e2SJacob Keller * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps
2487595b13e2SJacob Keller * @hw: pointer to the HW struct
2488595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure
2489595b13e2SJacob Keller * @cap: capability element to parse
2490595b13e2SJacob Keller *
2491595b13e2SJacob Keller * Parse ICE_AQC_CAPS_VF for device capabilities.
2492595b13e2SJacob Keller */
2493595b13e2SJacob Keller static void
ice_parse_vf_dev_caps(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,struct ice_aqc_list_caps_elem * cap)2494595b13e2SJacob Keller ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2495595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap)
2496595b13e2SJacob Keller {
2497595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number);
2498595b13e2SJacob Keller
2499595b13e2SJacob Keller dev_p->num_vfs_exposed = number;
2500595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n",
2501595b13e2SJacob Keller dev_p->num_vfs_exposed);
2502595b13e2SJacob Keller }
2503595b13e2SJacob Keller
2504595b13e2SJacob Keller /**
2505595b13e2SJacob Keller * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2506595b13e2SJacob Keller * @hw: pointer to the HW struct
2507595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure
2508595b13e2SJacob Keller * @cap: capability element to parse
2509595b13e2SJacob Keller *
2510595b13e2SJacob Keller * Parse ICE_AQC_CAPS_VSI for device capabilities.
2511595b13e2SJacob Keller */
2512595b13e2SJacob Keller static void
ice_parse_vsi_dev_caps(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,struct ice_aqc_list_caps_elem * cap)2513595b13e2SJacob Keller ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2514595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap)
2515595b13e2SJacob Keller {
2516595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number);
2517595b13e2SJacob Keller
2518595b13e2SJacob Keller dev_p->num_vsi_allocd_to_host = number;
2519595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
2520595b13e2SJacob Keller dev_p->num_vsi_allocd_to_host);
2521595b13e2SJacob Keller }
2522595b13e2SJacob Keller
2523595b13e2SJacob Keller /**
25249733cc94SJacob Keller * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps
25259733cc94SJacob Keller * @hw: pointer to the HW struct
25269733cc94SJacob Keller * @dev_p: pointer to device capabilities structure
25279733cc94SJacob Keller * @cap: capability element to parse
25289733cc94SJacob Keller *
25299733cc94SJacob Keller * Parse ICE_AQC_CAPS_1588 for device capabilities.
25309733cc94SJacob Keller */
25319733cc94SJacob Keller static void
ice_parse_1588_dev_caps(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,struct ice_aqc_list_caps_elem * cap)25329733cc94SJacob Keller ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
25339733cc94SJacob Keller struct ice_aqc_list_caps_elem *cap)
25349733cc94SJacob Keller {
25359733cc94SJacob Keller struct ice_ts_dev_info *info = &dev_p->ts_dev_info;
25369733cc94SJacob Keller u32 logical_id = le32_to_cpu(cap->logical_id);
25379733cc94SJacob Keller u32 phys_id = le32_to_cpu(cap->phys_id);
25389733cc94SJacob Keller u32 number = le32_to_cpu(cap->number);
25399733cc94SJacob Keller
25409733cc94SJacob Keller info->ena = ((number & ICE_TS_DEV_ENA_M) != 0);
25419733cc94SJacob Keller dev_p->common_cap.ieee_1588 = info->ena;
25429733cc94SJacob Keller
25439733cc94SJacob Keller info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M;
25449733cc94SJacob Keller info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0);
25459733cc94SJacob Keller info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0);
25469733cc94SJacob Keller
25479733cc94SJacob Keller info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S;
25489733cc94SJacob Keller info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);
25499733cc94SJacob Keller info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);
25509733cc94SJacob Keller
25511229b339SKarol Kolacinski info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0);
25521229b339SKarol Kolacinski
25539733cc94SJacob Keller info->ena_ports = logical_id;
25549733cc94SJacob Keller info->tmr_own_map = phys_id;
25559733cc94SJacob Keller
25569733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n",
25579733cc94SJacob Keller dev_p->common_cap.ieee_1588);
25589733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n",
25599733cc94SJacob Keller info->tmr0_owner);
25609733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n",
25619733cc94SJacob Keller info->tmr0_owned);
25629733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n",
25639733cc94SJacob Keller info->tmr0_ena);
25649733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n",
25659733cc94SJacob Keller info->tmr1_owner);
25669733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n",
25679733cc94SJacob Keller info->tmr1_owned);
25689733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n",
25699733cc94SJacob Keller info->tmr1_ena);
25701229b339SKarol Kolacinski ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n",
25711229b339SKarol Kolacinski info->ts_ll_read);
25729733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
25739733cc94SJacob Keller info->ena_ports);
25749733cc94SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
25759733cc94SJacob Keller info->tmr_own_map);
25769733cc94SJacob Keller }
25779733cc94SJacob Keller
25789733cc94SJacob Keller /**
2579595b13e2SJacob Keller * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2580595b13e2SJacob Keller * @hw: pointer to the HW struct
2581595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure
2582595b13e2SJacob Keller * @cap: capability element to parse
2583595b13e2SJacob Keller *
2584595b13e2SJacob Keller * Parse ICE_AQC_CAPS_FD for device capabilities.
2585595b13e2SJacob Keller */
2586595b13e2SJacob Keller static void
ice_parse_fdir_dev_caps(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,struct ice_aqc_list_caps_elem * cap)2587595b13e2SJacob Keller ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2588595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap)
2589595b13e2SJacob Keller {
2590595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number);
2591595b13e2SJacob Keller
2592595b13e2SJacob Keller dev_p->num_flow_director_fltr = number;
2593595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
2594595b13e2SJacob Keller dev_p->num_flow_director_fltr);
2595595b13e2SJacob Keller }
2596595b13e2SJacob Keller
2597595b13e2SJacob Keller /**
2598595b13e2SJacob Keller * ice_parse_dev_caps - Parse device capabilities
2599595b13e2SJacob Keller * @hw: pointer to the HW struct
2600595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure
2601595b13e2SJacob Keller * @buf: buffer containing the device capability records
2602595b13e2SJacob Keller * @cap_count: the number of capabilities
2603595b13e2SJacob Keller *
2604595b13e2SJacob Keller * Helper device to parse device (0x000B) capabilities list. For
26057dbc63f0STony Nguyen * capabilities shared between device and function, this relies on
2606595b13e2SJacob Keller * ice_parse_common_caps.
2607595b13e2SJacob Keller *
2608595b13e2SJacob Keller * Loop through the list of provided capabilities and extract the relevant
2609595b13e2SJacob Keller * data into the device capabilities structured.
2610595b13e2SJacob Keller */
2611595b13e2SJacob Keller static void
ice_parse_dev_caps(struct ice_hw * hw,struct ice_hw_dev_caps * dev_p,void * buf,u32 cap_count)2612595b13e2SJacob Keller ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2613595b13e2SJacob Keller void *buf, u32 cap_count)
2614595b13e2SJacob Keller {
2615595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap_resp;
2616595b13e2SJacob Keller u32 i;
2617595b13e2SJacob Keller
26187a63dae0SBruce Allan cap_resp = buf;
2619595b13e2SJacob Keller
2620595b13e2SJacob Keller memset(dev_p, 0, sizeof(*dev_p));
2621595b13e2SJacob Keller
2622595b13e2SJacob Keller for (i = 0; i < cap_count; i++) {
2623595b13e2SJacob Keller u16 cap = le16_to_cpu(cap_resp[i].cap);
2624595b13e2SJacob Keller bool found;
2625595b13e2SJacob Keller
2626595b13e2SJacob Keller found = ice_parse_common_caps(hw, &dev_p->common_cap,
2627595b13e2SJacob Keller &cap_resp[i], "dev caps");
2628595b13e2SJacob Keller
2629595b13e2SJacob Keller switch (cap) {
2630595b13e2SJacob Keller case ICE_AQC_CAPS_VALID_FUNCTIONS:
2631595b13e2SJacob Keller ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
2632595b13e2SJacob Keller break;
2633595b13e2SJacob Keller case ICE_AQC_CAPS_VF:
2634595b13e2SJacob Keller ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]);
2635595b13e2SJacob Keller break;
2636595b13e2SJacob Keller case ICE_AQC_CAPS_VSI:
2637595b13e2SJacob Keller ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
2638595b13e2SJacob Keller break;
26399733cc94SJacob Keller case ICE_AQC_CAPS_1588:
26409733cc94SJacob Keller ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);
26419733cc94SJacob Keller break;
2642595b13e2SJacob Keller case ICE_AQC_CAPS_FD:
2643595b13e2SJacob Keller ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
2644595b13e2SJacob Keller break;
2645595b13e2SJacob Keller default:
2646595b13e2SJacob Keller /* Don't list common capabilities as unknown */
2647595b13e2SJacob Keller if (!found)
26489228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n",
2649595b13e2SJacob Keller i, cap);
2650595b13e2SJacob Keller break;
2651595b13e2SJacob Keller }
2652595b13e2SJacob Keller }
2653595b13e2SJacob Keller
2654595b13e2SJacob Keller ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
2655595b13e2SJacob Keller }
2656595b13e2SJacob Keller
2657595b13e2SJacob Keller /**
2658272ad794SKarol Kolacinski * ice_aq_get_netlist_node
2659272ad794SKarol Kolacinski * @hw: pointer to the hw struct
2660272ad794SKarol Kolacinski * @cmd: get_link_topo AQ structure
2661272ad794SKarol Kolacinski * @node_part_number: output node part number if node found
2662272ad794SKarol Kolacinski * @node_handle: output node handle parameter if node found
2663272ad794SKarol Kolacinski */
2664272ad794SKarol Kolacinski static int
ice_aq_get_netlist_node(struct ice_hw * hw,struct ice_aqc_get_link_topo * cmd,u8 * node_part_number,u16 * node_handle)2665272ad794SKarol Kolacinski ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd,
2666272ad794SKarol Kolacinski u8 *node_part_number, u16 *node_handle)
2667272ad794SKarol Kolacinski {
2668272ad794SKarol Kolacinski struct ice_aq_desc desc;
2669272ad794SKarol Kolacinski
2670272ad794SKarol Kolacinski ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
2671272ad794SKarol Kolacinski desc.params.get_link_topo = *cmd;
2672272ad794SKarol Kolacinski
2673272ad794SKarol Kolacinski if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL))
2674272ad794SKarol Kolacinski return -EIO;
2675272ad794SKarol Kolacinski
2676272ad794SKarol Kolacinski if (node_handle)
2677272ad794SKarol Kolacinski *node_handle = le16_to_cpu(desc.params.get_link_topo.addr.handle);
2678272ad794SKarol Kolacinski if (node_part_number)
2679272ad794SKarol Kolacinski *node_part_number = desc.params.get_link_topo.node_part_num;
2680272ad794SKarol Kolacinski
2681272ad794SKarol Kolacinski return 0;
2682272ad794SKarol Kolacinski }
2683272ad794SKarol Kolacinski
2684272ad794SKarol Kolacinski /**
2685272ad794SKarol Kolacinski * ice_is_pf_c827 - check if pf contains c827 phy
2686272ad794SKarol Kolacinski * @hw: pointer to the hw struct
2687272ad794SKarol Kolacinski */
ice_is_pf_c827(struct ice_hw * hw)2688272ad794SKarol Kolacinski bool ice_is_pf_c827(struct ice_hw *hw)
2689272ad794SKarol Kolacinski {
2690272ad794SKarol Kolacinski struct ice_aqc_get_link_topo cmd = {};
2691272ad794SKarol Kolacinski u8 node_part_number;
2692272ad794SKarol Kolacinski u16 node_handle;
2693272ad794SKarol Kolacinski int status;
2694272ad794SKarol Kolacinski
2695272ad794SKarol Kolacinski if (hw->mac_type != ICE_MAC_E810)
2696272ad794SKarol Kolacinski return false;
2697272ad794SKarol Kolacinski
2698272ad794SKarol Kolacinski if (hw->device_id != ICE_DEV_ID_E810C_QSFP)
2699272ad794SKarol Kolacinski return true;
2700272ad794SKarol Kolacinski
2701272ad794SKarol Kolacinski cmd.addr.topo_params.node_type_ctx =
2702272ad794SKarol Kolacinski FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) |
2703272ad794SKarol Kolacinski FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT);
2704272ad794SKarol Kolacinski cmd.addr.topo_params.index = 0;
2705272ad794SKarol Kolacinski
2706272ad794SKarol Kolacinski status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number,
2707272ad794SKarol Kolacinski &node_handle);
2708272ad794SKarol Kolacinski
2709272ad794SKarol Kolacinski if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827)
2710272ad794SKarol Kolacinski return false;
2711272ad794SKarol Kolacinski
2712272ad794SKarol Kolacinski if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE)
2713272ad794SKarol Kolacinski return true;
2714272ad794SKarol Kolacinski
2715272ad794SKarol Kolacinski return false;
2716272ad794SKarol Kolacinski }
2717272ad794SKarol Kolacinski
2718272ad794SKarol Kolacinski /**
27198d7aab35SJacob Keller * ice_aq_list_caps - query function/device capabilities
2720f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
27218d7aab35SJacob Keller * @buf: a buffer to hold the capabilities
27228d7aab35SJacob Keller * @buf_size: size of the buffer
27238d7aab35SJacob Keller * @cap_count: if not NULL, set to the number of capabilities reported
27248d7aab35SJacob Keller * @opc: capabilities type to discover, device or function
27259c20346bSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
27269c20346bSAnirudh Venkataramanan *
27278d7aab35SJacob Keller * Get the function (0x000A) or device (0x000B) capabilities description from
27288d7aab35SJacob Keller * firmware and store it in the buffer.
27298d7aab35SJacob Keller *
27308d7aab35SJacob Keller * If the cap_count pointer is not NULL, then it is set to the number of
27318d7aab35SJacob Keller * capabilities firmware will report. Note that if the buffer size is too
27328d7aab35SJacob Keller * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
27338d7aab35SJacob Keller * cap_count will still be updated in this case. It is recommended that the
27348d7aab35SJacob Keller * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
27358d7aab35SJacob Keller * firmware could return) to avoid this.
27369c20346bSAnirudh Venkataramanan */
27375e24d598STony Nguyen int
ice_aq_list_caps(struct ice_hw * hw,void * buf,u16 buf_size,u32 * cap_count,enum ice_adminq_opc opc,struct ice_sq_cd * cd)27388d7aab35SJacob Keller ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
27399c20346bSAnirudh Venkataramanan enum ice_adminq_opc opc, struct ice_sq_cd *cd)
27409c20346bSAnirudh Venkataramanan {
27419c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps *cmd;
27429c20346bSAnirudh Venkataramanan struct ice_aq_desc desc;
27435e24d598STony Nguyen int status;
27449c20346bSAnirudh Venkataramanan
27459c20346bSAnirudh Venkataramanan cmd = &desc.params.get_cap;
27469c20346bSAnirudh Venkataramanan
27479c20346bSAnirudh Venkataramanan if (opc != ice_aqc_opc_list_func_caps &&
27489c20346bSAnirudh Venkataramanan opc != ice_aqc_opc_list_dev_caps)
2749d54699e2STony Nguyen return -EINVAL;
27509c20346bSAnirudh Venkataramanan
27519c20346bSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, opc);
27529c20346bSAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
27538d7aab35SJacob Keller
27548d7aab35SJacob Keller if (cap_count)
275599189e8bSAnirudh Venkataramanan *cap_count = le32_to_cpu(cmd->count);
27568d7aab35SJacob Keller
27578d7aab35SJacob Keller return status;
27588d7aab35SJacob Keller }
27598d7aab35SJacob Keller
27608d7aab35SJacob Keller /**
276181aed647SJacob Keller * ice_discover_dev_caps - Read and extract device capabilities
27627d86cf38SAnirudh Venkataramanan * @hw: pointer to the hardware structure
276381aed647SJacob Keller * @dev_caps: pointer to device capabilities structure
276481aed647SJacob Keller *
276581aed647SJacob Keller * Read the device capabilities and extract them into the dev_caps structure
276681aed647SJacob Keller * for later use.
27677d86cf38SAnirudh Venkataramanan */
27685e24d598STony Nguyen int
ice_discover_dev_caps(struct ice_hw * hw,struct ice_hw_dev_caps * dev_caps)276981aed647SJacob Keller ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
27707d86cf38SAnirudh Venkataramanan {
277181aed647SJacob Keller u32 cap_count = 0;
27727d86cf38SAnirudh Venkataramanan void *cbuf;
27735518ac2aSTony Nguyen int status;
27747d86cf38SAnirudh Venkataramanan
27751082b360SJacob Keller cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
27767d86cf38SAnirudh Venkataramanan if (!cbuf)
2777d54699e2STony Nguyen return -ENOMEM;
27787d86cf38SAnirudh Venkataramanan
27791082b360SJacob Keller /* Although the driver doesn't know the number of capabilities the
27801082b360SJacob Keller * device will return, we can simply send a 4KB buffer, the maximum
27811082b360SJacob Keller * possible size that firmware can return.
27821082b360SJacob Keller */
27831082b360SJacob Keller cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
27841082b360SJacob Keller
278581aed647SJacob Keller status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
278681aed647SJacob Keller ice_aqc_opc_list_dev_caps, NULL);
278781aed647SJacob Keller if (!status)
278881aed647SJacob Keller ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count);
278981aed647SJacob Keller kfree(cbuf);
279081aed647SJacob Keller
279181aed647SJacob Keller return status;
279281aed647SJacob Keller }
279381aed647SJacob Keller
279481aed647SJacob Keller /**
279581aed647SJacob Keller * ice_discover_func_caps - Read and extract function capabilities
279681aed647SJacob Keller * @hw: pointer to the hardware structure
279781aed647SJacob Keller * @func_caps: pointer to function capabilities structure
279881aed647SJacob Keller *
279981aed647SJacob Keller * Read the function capabilities and extract them into the func_caps structure
280081aed647SJacob Keller * for later use.
280181aed647SJacob Keller */
28025e24d598STony Nguyen static int
ice_discover_func_caps(struct ice_hw * hw,struct ice_hw_func_caps * func_caps)280381aed647SJacob Keller ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
280481aed647SJacob Keller {
280581aed647SJacob Keller u32 cap_count = 0;
280681aed647SJacob Keller void *cbuf;
28075518ac2aSTony Nguyen int status;
280881aed647SJacob Keller
280981aed647SJacob Keller cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
281081aed647SJacob Keller if (!cbuf)
2811d54699e2STony Nguyen return -ENOMEM;
281281aed647SJacob Keller
281381aed647SJacob Keller /* Although the driver doesn't know the number of capabilities the
281481aed647SJacob Keller * device will return, we can simply send a 4KB buffer, the maximum
281581aed647SJacob Keller * possible size that firmware can return.
281681aed647SJacob Keller */
281781aed647SJacob Keller cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
281881aed647SJacob Keller
281981aed647SJacob Keller status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
282081aed647SJacob Keller ice_aqc_opc_list_func_caps, NULL);
282181aed647SJacob Keller if (!status)
282281aed647SJacob Keller ice_parse_func_caps(hw, func_caps, cbuf, cap_count);
28231082b360SJacob Keller kfree(cbuf);
28249c20346bSAnirudh Venkataramanan
28259c20346bSAnirudh Venkataramanan return status;
28269c20346bSAnirudh Venkataramanan }
28279c20346bSAnirudh Venkataramanan
28289c20346bSAnirudh Venkataramanan /**
2829462acf6aSTony Nguyen * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2830462acf6aSTony Nguyen * @hw: pointer to the hardware structure
2831462acf6aSTony Nguyen */
ice_set_safe_mode_caps(struct ice_hw * hw)2832462acf6aSTony Nguyen void ice_set_safe_mode_caps(struct ice_hw *hw)
2833462acf6aSTony Nguyen {
2834462acf6aSTony Nguyen struct ice_hw_func_caps *func_caps = &hw->func_caps;
2835462acf6aSTony Nguyen struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2836be49b1adSJacob Keller struct ice_hw_common_caps cached_caps;
2837eae1bbb2SBruce Allan u32 num_funcs;
2838462acf6aSTony Nguyen
2839462acf6aSTony Nguyen /* cache some func_caps values that should be restored after memset */
2840be49b1adSJacob Keller cached_caps = func_caps->common_cap;
2841462acf6aSTony Nguyen
2842462acf6aSTony Nguyen /* unset func capabilities */
2843462acf6aSTony Nguyen memset(func_caps, 0, sizeof(*func_caps));
2844462acf6aSTony Nguyen
2845be49b1adSJacob Keller #define ICE_RESTORE_FUNC_CAP(name) \
2846be49b1adSJacob Keller func_caps->common_cap.name = cached_caps.name
2847be49b1adSJacob Keller
2848462acf6aSTony Nguyen /* restore cached values */
2849be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(valid_functions);
2850be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(txq_first_id);
2851be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(rxq_first_id);
2852be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(msix_vector_first_id);
2853be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(max_mtu);
2854be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(nvm_unified_update);
2855be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm);
2856be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom);
2857be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist);
2858462acf6aSTony Nguyen
2859462acf6aSTony Nguyen /* one Tx and one Rx queue in safe mode */
2860462acf6aSTony Nguyen func_caps->common_cap.num_rxq = 1;
2861462acf6aSTony Nguyen func_caps->common_cap.num_txq = 1;
2862462acf6aSTony Nguyen
2863462acf6aSTony Nguyen /* two MSIX vectors, one for traffic and one for misc causes */
2864462acf6aSTony Nguyen func_caps->common_cap.num_msix_vectors = 2;
2865462acf6aSTony Nguyen func_caps->guar_num_vsi = 1;
2866462acf6aSTony Nguyen
2867462acf6aSTony Nguyen /* cache some dev_caps values that should be restored after memset */
2868be49b1adSJacob Keller cached_caps = dev_caps->common_cap;
2869eae1bbb2SBruce Allan num_funcs = dev_caps->num_funcs;
2870462acf6aSTony Nguyen
2871462acf6aSTony Nguyen /* unset dev capabilities */
2872462acf6aSTony Nguyen memset(dev_caps, 0, sizeof(*dev_caps));
2873462acf6aSTony Nguyen
2874be49b1adSJacob Keller #define ICE_RESTORE_DEV_CAP(name) \
2875be49b1adSJacob Keller dev_caps->common_cap.name = cached_caps.name
2876be49b1adSJacob Keller
2877462acf6aSTony Nguyen /* restore cached values */
2878be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(valid_functions);
2879be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(txq_first_id);
2880be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(rxq_first_id);
2881be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(msix_vector_first_id);
2882be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(max_mtu);
2883be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(nvm_unified_update);
2884be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm);
2885be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(nvm_update_pending_orom);
2886be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist);
2887eae1bbb2SBruce Allan dev_caps->num_funcs = num_funcs;
2888462acf6aSTony Nguyen
2889462acf6aSTony Nguyen /* one Tx and one Rx queue per function in safe mode */
2890eae1bbb2SBruce Allan dev_caps->common_cap.num_rxq = num_funcs;
2891eae1bbb2SBruce Allan dev_caps->common_cap.num_txq = num_funcs;
2892462acf6aSTony Nguyen
2893462acf6aSTony Nguyen /* two MSIX vectors per function */
2894eae1bbb2SBruce Allan dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2895462acf6aSTony Nguyen }
2896462acf6aSTony Nguyen
2897462acf6aSTony Nguyen /**
28989c20346bSAnirudh Venkataramanan * ice_get_caps - get info about the HW
28999c20346bSAnirudh Venkataramanan * @hw: pointer to the hardware structure
29009c20346bSAnirudh Venkataramanan */
ice_get_caps(struct ice_hw * hw)29015e24d598STony Nguyen int ice_get_caps(struct ice_hw *hw)
29029c20346bSAnirudh Venkataramanan {
29035e24d598STony Nguyen int status;
29049c20346bSAnirudh Venkataramanan
290581aed647SJacob Keller status = ice_discover_dev_caps(hw, &hw->dev_caps);
290681aed647SJacob Keller if (status)
29079c20346bSAnirudh Venkataramanan return status;
290881aed647SJacob Keller
290981aed647SJacob Keller return ice_discover_func_caps(hw, &hw->func_caps);
29109c20346bSAnirudh Venkataramanan }
29119c20346bSAnirudh Venkataramanan
29129c20346bSAnirudh Venkataramanan /**
2913e94d4478SAnirudh Venkataramanan * ice_aq_manage_mac_write - manage MAC address write command
2914f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
2915e94d4478SAnirudh Venkataramanan * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2916e94d4478SAnirudh Venkataramanan * @flags: flags to control write behavior
2917e94d4478SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
2918e94d4478SAnirudh Venkataramanan *
2919e94d4478SAnirudh Venkataramanan * This function is used to write MAC address to the NVM (0x0108).
2920e94d4478SAnirudh Venkataramanan */
29215e24d598STony Nguyen int
ice_aq_manage_mac_write(struct ice_hw * hw,const u8 * mac_addr,u8 flags,struct ice_sq_cd * cd)2922d671e3e0SJacob Keller ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2923e94d4478SAnirudh Venkataramanan struct ice_sq_cd *cd)
2924e94d4478SAnirudh Venkataramanan {
2925e94d4478SAnirudh Venkataramanan struct ice_aqc_manage_mac_write *cmd;
2926e94d4478SAnirudh Venkataramanan struct ice_aq_desc desc;
2927e94d4478SAnirudh Venkataramanan
2928e94d4478SAnirudh Venkataramanan cmd = &desc.params.mac_write;
2929e94d4478SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2930e94d4478SAnirudh Venkataramanan
2931e94d4478SAnirudh Venkataramanan cmd->flags = flags;
29325df42c82SJesse Brandeburg ether_addr_copy(cmd->mac_addr, mac_addr);
2933e94d4478SAnirudh Venkataramanan
2934e94d4478SAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2935e94d4478SAnirudh Venkataramanan }
2936e94d4478SAnirudh Venkataramanan
2937e94d4478SAnirudh Venkataramanan /**
2938f31e4b6fSAnirudh Venkataramanan * ice_aq_clear_pxe_mode
2939f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
2940f31e4b6fSAnirudh Venkataramanan *
2941f31e4b6fSAnirudh Venkataramanan * Tell the firmware that the driver is taking over from PXE (0x0110).
2942f31e4b6fSAnirudh Venkataramanan */
ice_aq_clear_pxe_mode(struct ice_hw * hw)29435e24d598STony Nguyen static int ice_aq_clear_pxe_mode(struct ice_hw *hw)
2944f31e4b6fSAnirudh Venkataramanan {
2945f31e4b6fSAnirudh Venkataramanan struct ice_aq_desc desc;
2946f31e4b6fSAnirudh Venkataramanan
2947f31e4b6fSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2948f31e4b6fSAnirudh Venkataramanan desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2949f31e4b6fSAnirudh Venkataramanan
2950f31e4b6fSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2951f31e4b6fSAnirudh Venkataramanan }
2952f31e4b6fSAnirudh Venkataramanan
2953f31e4b6fSAnirudh Venkataramanan /**
2954f31e4b6fSAnirudh Venkataramanan * ice_clear_pxe_mode - clear pxe operations mode
2955f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
2956f31e4b6fSAnirudh Venkataramanan *
2957f31e4b6fSAnirudh Venkataramanan * Make sure all PXE mode settings are cleared, including things
2958f31e4b6fSAnirudh Venkataramanan * like descriptor fetch/write-back mode.
2959f31e4b6fSAnirudh Venkataramanan */
ice_clear_pxe_mode(struct ice_hw * hw)2960f31e4b6fSAnirudh Venkataramanan void ice_clear_pxe_mode(struct ice_hw *hw)
2961f31e4b6fSAnirudh Venkataramanan {
2962f31e4b6fSAnirudh Venkataramanan if (ice_check_sq_alive(hw, &hw->adminq))
2963f31e4b6fSAnirudh Venkataramanan ice_aq_clear_pxe_mode(hw);
2964f31e4b6fSAnirudh Venkataramanan }
2965cdedef59SAnirudh Venkataramanan
2966cdedef59SAnirudh Venkataramanan /**
2967a1ffafb0SBrett Creeley * ice_aq_set_port_params - set physical port parameters.
2968a1ffafb0SBrett Creeley * @pi: pointer to the port info struct
2969a1ffafb0SBrett Creeley * @double_vlan: if set double VLAN is enabled
2970a1ffafb0SBrett Creeley * @cd: pointer to command details structure or NULL
2971a1ffafb0SBrett Creeley *
2972a1ffafb0SBrett Creeley * Set Physical port parameters (0x0203)
2973a1ffafb0SBrett Creeley */
2974a1ffafb0SBrett Creeley int
ice_aq_set_port_params(struct ice_port_info * pi,bool double_vlan,struct ice_sq_cd * cd)2975a1ffafb0SBrett Creeley ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan,
2976a1ffafb0SBrett Creeley struct ice_sq_cd *cd)
2977a1ffafb0SBrett Creeley
2978a1ffafb0SBrett Creeley {
2979a1ffafb0SBrett Creeley struct ice_aqc_set_port_params *cmd;
2980a1ffafb0SBrett Creeley struct ice_hw *hw = pi->hw;
2981a1ffafb0SBrett Creeley struct ice_aq_desc desc;
2982a1ffafb0SBrett Creeley u16 cmd_flags = 0;
2983a1ffafb0SBrett Creeley
2984a1ffafb0SBrett Creeley cmd = &desc.params.set_port_params;
2985a1ffafb0SBrett Creeley
2986a1ffafb0SBrett Creeley ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params);
2987a1ffafb0SBrett Creeley if (double_vlan)
2988a1ffafb0SBrett Creeley cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA;
2989a1ffafb0SBrett Creeley cmd->cmd_flags = cpu_to_le16(cmd_flags);
2990a1ffafb0SBrett Creeley
2991a1ffafb0SBrett Creeley return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2992a1ffafb0SBrett Creeley }
2993a1ffafb0SBrett Creeley
2994a1ffafb0SBrett Creeley /**
299539ed02a4SAnirudh Venkataramanan * ice_is_100m_speed_supported
299639ed02a4SAnirudh Venkataramanan * @hw: pointer to the HW struct
299739ed02a4SAnirudh Venkataramanan *
299839ed02a4SAnirudh Venkataramanan * returns true if 100M speeds are supported by the device,
299939ed02a4SAnirudh Venkataramanan * false otherwise.
300039ed02a4SAnirudh Venkataramanan */
ice_is_100m_speed_supported(struct ice_hw * hw)300139ed02a4SAnirudh Venkataramanan bool ice_is_100m_speed_supported(struct ice_hw *hw)
300239ed02a4SAnirudh Venkataramanan {
300339ed02a4SAnirudh Venkataramanan switch (hw->device_id) {
300439ed02a4SAnirudh Venkataramanan case ICE_DEV_ID_E822C_SGMII:
300539ed02a4SAnirudh Venkataramanan case ICE_DEV_ID_E822L_SGMII:
300639ed02a4SAnirudh Venkataramanan case ICE_DEV_ID_E823L_1GBE:
300739ed02a4SAnirudh Venkataramanan case ICE_DEV_ID_E823C_SGMII:
300839ed02a4SAnirudh Venkataramanan return true;
300939ed02a4SAnirudh Venkataramanan default:
301039ed02a4SAnirudh Venkataramanan return false;
301139ed02a4SAnirudh Venkataramanan }
301239ed02a4SAnirudh Venkataramanan }
301339ed02a4SAnirudh Venkataramanan
301439ed02a4SAnirudh Venkataramanan /**
301548cb27f2SChinh Cao * ice_get_link_speed_based_on_phy_type - returns link speed
301648cb27f2SChinh Cao * @phy_type_low: lower part of phy_type
3017aef74145SAnirudh Venkataramanan * @phy_type_high: higher part of phy_type
301848cb27f2SChinh Cao *
3019f9867df6SAnirudh Venkataramanan * This helper function will convert an entry in PHY type structure
3020aef74145SAnirudh Venkataramanan * [phy_type_low, phy_type_high] to its corresponding link speed.
3021aef74145SAnirudh Venkataramanan * Note: In the structure of [phy_type_low, phy_type_high], there should
3022f9867df6SAnirudh Venkataramanan * be one bit set, as this function will convert one PHY type to its
302348cb27f2SChinh Cao * speed.
30241d0e28a9SBrett Creeley * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
30251d0e28a9SBrett Creeley * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
302648cb27f2SChinh Cao */
3027aef74145SAnirudh Venkataramanan static u16
ice_get_link_speed_based_on_phy_type(u64 phy_type_low,u64 phy_type_high)3028aef74145SAnirudh Venkataramanan ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
302948cb27f2SChinh Cao {
3030aef74145SAnirudh Venkataramanan u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
303148cb27f2SChinh Cao u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
303248cb27f2SChinh Cao
303348cb27f2SChinh Cao switch (phy_type_low) {
303448cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_100BASE_TX:
303548cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_100M_SGMII:
303648cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
303748cb27f2SChinh Cao break;
303848cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1000BASE_T:
303948cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1000BASE_SX:
304048cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1000BASE_LX:
304148cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1000BASE_KX:
304248cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1G_SGMII:
304348cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
304448cb27f2SChinh Cao break;
304548cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_2500BASE_T:
304648cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_2500BASE_X:
304748cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_2500BASE_KX:
304848cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
304948cb27f2SChinh Cao break;
305048cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_5GBASE_T:
305148cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_5GBASE_KR:
305248cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
305348cb27f2SChinh Cao break;
305448cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10GBASE_T:
305548cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10G_SFI_DA:
305648cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10GBASE_SR:
305748cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10GBASE_LR:
305848cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
305948cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
306048cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
306148cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
306248cb27f2SChinh Cao break;
306348cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_T:
306448cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_CR:
306548cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
306648cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_CR1:
306748cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_SR:
306848cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_LR:
306948cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_KR:
307048cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
307148cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_KR1:
307248cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
307348cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
307448cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
307548cb27f2SChinh Cao break;
307648cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40GBASE_CR4:
307748cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40GBASE_SR4:
307848cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40GBASE_LR4:
307948cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40GBASE_KR4:
308048cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
308148cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40G_XLAUI:
308248cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
308348cb27f2SChinh Cao break;
3084aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_CR2:
3085aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_SR2:
3086aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_LR2:
3087aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_KR2:
3088aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
3089aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_LAUI2:
3090aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
3091aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_AUI2:
3092aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_CP:
3093aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_SR:
3094aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_FR:
3095aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_LR:
3096aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
3097aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
3098aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_AUI1:
3099aef74145SAnirudh Venkataramanan speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
3100aef74145SAnirudh Venkataramanan break;
3101aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CR4:
3102aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_SR4:
3103aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_LR4:
3104aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_KR4:
3105aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
3106aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100G_CAUI4:
3107aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
3108aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100G_AUI4:
3109aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
3110aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
3111aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CP2:
3112aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_SR2:
3113aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_DR:
3114aef74145SAnirudh Venkataramanan speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
3115aef74145SAnirudh Venkataramanan break;
311648cb27f2SChinh Cao default:
311748cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
311848cb27f2SChinh Cao break;
311948cb27f2SChinh Cao }
312048cb27f2SChinh Cao
3121aef74145SAnirudh Venkataramanan switch (phy_type_high) {
3122aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
3123aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
3124aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100G_CAUI2:
3125aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
3126aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100G_AUI2:
3127aef74145SAnirudh Venkataramanan speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
3128aef74145SAnirudh Venkataramanan break;
3129aef74145SAnirudh Venkataramanan default:
3130aef74145SAnirudh Venkataramanan speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
3131aef74145SAnirudh Venkataramanan break;
3132aef74145SAnirudh Venkataramanan }
3133aef74145SAnirudh Venkataramanan
3134aef74145SAnirudh Venkataramanan if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
3135aef74145SAnirudh Venkataramanan speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3136aef74145SAnirudh Venkataramanan return ICE_AQ_LINK_SPEED_UNKNOWN;
3137aef74145SAnirudh Venkataramanan else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3138aef74145SAnirudh Venkataramanan speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
3139aef74145SAnirudh Venkataramanan return ICE_AQ_LINK_SPEED_UNKNOWN;
3140aef74145SAnirudh Venkataramanan else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3141aef74145SAnirudh Venkataramanan speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
314248cb27f2SChinh Cao return speed_phy_type_low;
3143aef74145SAnirudh Venkataramanan else
3144aef74145SAnirudh Venkataramanan return speed_phy_type_high;
314548cb27f2SChinh Cao }
314648cb27f2SChinh Cao
314748cb27f2SChinh Cao /**
314848cb27f2SChinh Cao * ice_update_phy_type
314948cb27f2SChinh Cao * @phy_type_low: pointer to the lower part of phy_type
3150aef74145SAnirudh Venkataramanan * @phy_type_high: pointer to the higher part of phy_type
315148cb27f2SChinh Cao * @link_speeds_bitmap: targeted link speeds bitmap
315248cb27f2SChinh Cao *
315348cb27f2SChinh Cao * Note: For the link_speeds_bitmap structure, you can check it at
315448cb27f2SChinh Cao * [ice_aqc_get_link_status->link_speed]. Caller can pass in
315548cb27f2SChinh Cao * link_speeds_bitmap include multiple speeds.
315648cb27f2SChinh Cao *
3157aef74145SAnirudh Venkataramanan * Each entry in this [phy_type_low, phy_type_high] structure will
3158aef74145SAnirudh Venkataramanan * present a certain link speed. This helper function will turn on bits
3159aef74145SAnirudh Venkataramanan * in [phy_type_low, phy_type_high] structure based on the value of
316048cb27f2SChinh Cao * link_speeds_bitmap input parameter.
316148cb27f2SChinh Cao */
3162aef74145SAnirudh Venkataramanan void
ice_update_phy_type(u64 * phy_type_low,u64 * phy_type_high,u16 link_speeds_bitmap)3163aef74145SAnirudh Venkataramanan ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
3164aef74145SAnirudh Venkataramanan u16 link_speeds_bitmap)
316548cb27f2SChinh Cao {
3166aef74145SAnirudh Venkataramanan u64 pt_high;
316748cb27f2SChinh Cao u64 pt_low;
316848cb27f2SChinh Cao int index;
3169207e3721SBruce Allan u16 speed;
317048cb27f2SChinh Cao
317148cb27f2SChinh Cao /* We first check with low part of phy_type */
317248cb27f2SChinh Cao for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
317348cb27f2SChinh Cao pt_low = BIT_ULL(index);
3174aef74145SAnirudh Venkataramanan speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
317548cb27f2SChinh Cao
317648cb27f2SChinh Cao if (link_speeds_bitmap & speed)
317748cb27f2SChinh Cao *phy_type_low |= BIT_ULL(index);
317848cb27f2SChinh Cao }
3179aef74145SAnirudh Venkataramanan
3180aef74145SAnirudh Venkataramanan /* We then check with high part of phy_type */
3181aef74145SAnirudh Venkataramanan for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
3182aef74145SAnirudh Venkataramanan pt_high = BIT_ULL(index);
3183aef74145SAnirudh Venkataramanan speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
3184aef74145SAnirudh Venkataramanan
3185aef74145SAnirudh Venkataramanan if (link_speeds_bitmap & speed)
3186aef74145SAnirudh Venkataramanan *phy_type_high |= BIT_ULL(index);
3187aef74145SAnirudh Venkataramanan }
318848cb27f2SChinh Cao }
318948cb27f2SChinh Cao
319048cb27f2SChinh Cao /**
3191fcea6f3dSAnirudh Venkataramanan * ice_aq_set_phy_cfg
3192f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
31931a3571b5SPaul Greenwalt * @pi: port info structure of the interested logical port
3194fcea6f3dSAnirudh Venkataramanan * @cfg: structure with PHY configuration data to be set
3195fcea6f3dSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
3196fcea6f3dSAnirudh Venkataramanan *
3197fcea6f3dSAnirudh Venkataramanan * Set the various PHY configuration parameters supported on the Port.
3198fcea6f3dSAnirudh Venkataramanan * One or more of the Set PHY config parameters may be ignored in an MFP
3199fcea6f3dSAnirudh Venkataramanan * mode as the PF may not have the privilege to set some of the PHY Config
3200fcea6f3dSAnirudh Venkataramanan * parameters. This status will be indicated by the command response (0x0601).
3201fcea6f3dSAnirudh Venkataramanan */
32025e24d598STony Nguyen int
ice_aq_set_phy_cfg(struct ice_hw * hw,struct ice_port_info * pi,struct ice_aqc_set_phy_cfg_data * cfg,struct ice_sq_cd * cd)32031a3571b5SPaul Greenwalt ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
3204fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
3205fcea6f3dSAnirudh Venkataramanan {
3206fcea6f3dSAnirudh Venkataramanan struct ice_aq_desc desc;
32075e24d598STony Nguyen int status;
3208fcea6f3dSAnirudh Venkataramanan
3209fcea6f3dSAnirudh Venkataramanan if (!cfg)
3210d54699e2STony Nguyen return -EINVAL;
3211fcea6f3dSAnirudh Venkataramanan
3212d8df260aSChinh T Cao /* Ensure that only valid bits of cfg->caps can be turned on. */
3213d8df260aSChinh T Cao if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
32149228d8b2SJacob Keller ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
3215d8df260aSChinh T Cao cfg->caps);
3216d8df260aSChinh T Cao
3217d8df260aSChinh T Cao cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
3218d8df260aSChinh T Cao }
3219d8df260aSChinh T Cao
3220fcea6f3dSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
32211a3571b5SPaul Greenwalt desc.params.set_phy.lport_num = pi->lport;
322248cb27f2SChinh Cao desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3223fcea6f3dSAnirudh Venkataramanan
322455df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
3225dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
3226dc67039bSJesse Brandeburg (unsigned long long)le64_to_cpu(cfg->phy_type_low));
3227dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
3228dc67039bSJesse Brandeburg (unsigned long long)le64_to_cpu(cfg->phy_type_high));
3229dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
3230bdeff971SLev Faerman ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
3231bdeff971SLev Faerman cfg->low_power_ctrl_an);
3232dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
3233dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
323455df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
323555df52a0SPaul Greenwalt cfg->link_fec_opt);
3236dc67039bSJesse Brandeburg
3237b5e19a64SChinh T Cao status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
3238b5e19a64SChinh T Cao if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
3239b5e19a64SChinh T Cao status = 0;
3240b5e19a64SChinh T Cao
32411a3571b5SPaul Greenwalt if (!status)
32421a3571b5SPaul Greenwalt pi->phy.curr_user_phy_cfg = *cfg;
32431a3571b5SPaul Greenwalt
3244b5e19a64SChinh T Cao return status;
3245fcea6f3dSAnirudh Venkataramanan }
3246fcea6f3dSAnirudh Venkataramanan
3247fcea6f3dSAnirudh Venkataramanan /**
3248fcea6f3dSAnirudh Venkataramanan * ice_update_link_info - update status of the HW network link
3249fcea6f3dSAnirudh Venkataramanan * @pi: port info structure of the interested logical port
3250fcea6f3dSAnirudh Venkataramanan */
ice_update_link_info(struct ice_port_info * pi)32515e24d598STony Nguyen int ice_update_link_info(struct ice_port_info *pi)
3252fcea6f3dSAnirudh Venkataramanan {
3253092a33d4SBruce Allan struct ice_link_status *li;
32545e24d598STony Nguyen int status;
3255fcea6f3dSAnirudh Venkataramanan
3256fcea6f3dSAnirudh Venkataramanan if (!pi)
3257d54699e2STony Nguyen return -EINVAL;
3258fcea6f3dSAnirudh Venkataramanan
3259092a33d4SBruce Allan li = &pi->phy.link_info;
3260fcea6f3dSAnirudh Venkataramanan
3261092a33d4SBruce Allan status = ice_aq_get_link_info(pi, true, NULL, NULL);
3262092a33d4SBruce Allan if (status)
3263092a33d4SBruce Allan return status;
3264092a33d4SBruce Allan
3265092a33d4SBruce Allan if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
3266092a33d4SBruce Allan struct ice_aqc_get_phy_caps_data *pcaps;
3267092a33d4SBruce Allan struct ice_hw *hw;
3268092a33d4SBruce Allan
3269092a33d4SBruce Allan hw = pi->hw;
3270092a33d4SBruce Allan pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps),
3271092a33d4SBruce Allan GFP_KERNEL);
3272fcea6f3dSAnirudh Venkataramanan if (!pcaps)
3273d54699e2STony Nguyen return -ENOMEM;
3274fcea6f3dSAnirudh Venkataramanan
3275d6730a87SAnirudh Venkataramanan status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
3276fcea6f3dSAnirudh Venkataramanan pcaps, NULL);
3277fcea6f3dSAnirudh Venkataramanan
3278fcea6f3dSAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), pcaps);
3279092a33d4SBruce Allan }
3280092a33d4SBruce Allan
3281fcea6f3dSAnirudh Venkataramanan return status;
3282fcea6f3dSAnirudh Venkataramanan }
3283fcea6f3dSAnirudh Venkataramanan
3284fcea6f3dSAnirudh Venkataramanan /**
32851a3571b5SPaul Greenwalt * ice_cache_phy_user_req
32861a3571b5SPaul Greenwalt * @pi: port information structure
32871a3571b5SPaul Greenwalt * @cache_data: PHY logging data
32881a3571b5SPaul Greenwalt * @cache_mode: PHY logging mode
32891a3571b5SPaul Greenwalt *
32901a3571b5SPaul Greenwalt * Log the user request on (FC, FEC, SPEED) for later use.
32911a3571b5SPaul Greenwalt */
32921a3571b5SPaul Greenwalt static void
ice_cache_phy_user_req(struct ice_port_info * pi,struct ice_phy_cache_mode_data cache_data,enum ice_phy_cache_mode cache_mode)32931a3571b5SPaul Greenwalt ice_cache_phy_user_req(struct ice_port_info *pi,
32941a3571b5SPaul Greenwalt struct ice_phy_cache_mode_data cache_data,
32951a3571b5SPaul Greenwalt enum ice_phy_cache_mode cache_mode)
32961a3571b5SPaul Greenwalt {
32971a3571b5SPaul Greenwalt if (!pi)
32981a3571b5SPaul Greenwalt return;
32991a3571b5SPaul Greenwalt
33001a3571b5SPaul Greenwalt switch (cache_mode) {
33011a3571b5SPaul Greenwalt case ICE_FC_MODE:
33021a3571b5SPaul Greenwalt pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
33031a3571b5SPaul Greenwalt break;
33041a3571b5SPaul Greenwalt case ICE_SPEED_MODE:
33051a3571b5SPaul Greenwalt pi->phy.curr_user_speed_req =
33061a3571b5SPaul Greenwalt cache_data.data.curr_user_speed_req;
33071a3571b5SPaul Greenwalt break;
33081a3571b5SPaul Greenwalt case ICE_FEC_MODE:
33091a3571b5SPaul Greenwalt pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
33101a3571b5SPaul Greenwalt break;
33111a3571b5SPaul Greenwalt default:
33121a3571b5SPaul Greenwalt break;
33131a3571b5SPaul Greenwalt }
33141a3571b5SPaul Greenwalt }
33151a3571b5SPaul Greenwalt
33161a3571b5SPaul Greenwalt /**
33171a3571b5SPaul Greenwalt * ice_caps_to_fc_mode
33181a3571b5SPaul Greenwalt * @caps: PHY capabilities
33191a3571b5SPaul Greenwalt *
33201a3571b5SPaul Greenwalt * Convert PHY FC capabilities to ice FC mode
33211a3571b5SPaul Greenwalt */
ice_caps_to_fc_mode(u8 caps)33221a3571b5SPaul Greenwalt enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
33231a3571b5SPaul Greenwalt {
33241a3571b5SPaul Greenwalt if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
33251a3571b5SPaul Greenwalt caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
33261a3571b5SPaul Greenwalt return ICE_FC_FULL;
33271a3571b5SPaul Greenwalt
33281a3571b5SPaul Greenwalt if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
33291a3571b5SPaul Greenwalt return ICE_FC_TX_PAUSE;
33301a3571b5SPaul Greenwalt
33311a3571b5SPaul Greenwalt if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
33321a3571b5SPaul Greenwalt return ICE_FC_RX_PAUSE;
33331a3571b5SPaul Greenwalt
33341a3571b5SPaul Greenwalt return ICE_FC_NONE;
33351a3571b5SPaul Greenwalt }
33361a3571b5SPaul Greenwalt
33371a3571b5SPaul Greenwalt /**
33381a3571b5SPaul Greenwalt * ice_caps_to_fec_mode
33391a3571b5SPaul Greenwalt * @caps: PHY capabilities
33401a3571b5SPaul Greenwalt * @fec_options: Link FEC options
33411a3571b5SPaul Greenwalt *
33421a3571b5SPaul Greenwalt * Convert PHY FEC capabilities to ice FEC mode
33431a3571b5SPaul Greenwalt */
ice_caps_to_fec_mode(u8 caps,u8 fec_options)33441a3571b5SPaul Greenwalt enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
33451a3571b5SPaul Greenwalt {
33461a3571b5SPaul Greenwalt if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
33471a3571b5SPaul Greenwalt return ICE_FEC_AUTO;
33481a3571b5SPaul Greenwalt
33491a3571b5SPaul Greenwalt if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
33501a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
33511a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
33521a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_25G_KR_REQ))
33531a3571b5SPaul Greenwalt return ICE_FEC_BASER;
33541a3571b5SPaul Greenwalt
33551a3571b5SPaul Greenwalt if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
33561a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_25G_RS_544_REQ |
33571a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
33581a3571b5SPaul Greenwalt return ICE_FEC_RS;
33591a3571b5SPaul Greenwalt
33601a3571b5SPaul Greenwalt return ICE_FEC_NONE;
33611a3571b5SPaul Greenwalt }
33621a3571b5SPaul Greenwalt
33631a3571b5SPaul Greenwalt /**
33642ffb6085SPaul Greenwalt * ice_cfg_phy_fc - Configure PHY FC data based on FC mode
33651a3571b5SPaul Greenwalt * @pi: port information structure
33662ffb6085SPaul Greenwalt * @cfg: PHY configuration data to set FC mode
33672ffb6085SPaul Greenwalt * @req_mode: FC mode to configure
3368fcea6f3dSAnirudh Venkataramanan */
33695e24d598STony Nguyen int
ice_cfg_phy_fc(struct ice_port_info * pi,struct ice_aqc_set_phy_cfg_data * cfg,enum ice_fc_mode req_mode)33701a3571b5SPaul Greenwalt ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
33711a3571b5SPaul Greenwalt enum ice_fc_mode req_mode)
3372fcea6f3dSAnirudh Venkataramanan {
33731a3571b5SPaul Greenwalt struct ice_phy_cache_mode_data cache_data;
3374fcea6f3dSAnirudh Venkataramanan u8 pause_mask = 0x0;
3375fcea6f3dSAnirudh Venkataramanan
33761a3571b5SPaul Greenwalt if (!pi || !cfg)
3377d54699e2STony Nguyen return -EINVAL;
3378fcea6f3dSAnirudh Venkataramanan
33792ffb6085SPaul Greenwalt switch (req_mode) {
3380fcea6f3dSAnirudh Venkataramanan case ICE_FC_FULL:
3381fcea6f3dSAnirudh Venkataramanan pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3382fcea6f3dSAnirudh Venkataramanan pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3383fcea6f3dSAnirudh Venkataramanan break;
3384fcea6f3dSAnirudh Venkataramanan case ICE_FC_RX_PAUSE:
3385fcea6f3dSAnirudh Venkataramanan pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3386fcea6f3dSAnirudh Venkataramanan break;
3387fcea6f3dSAnirudh Venkataramanan case ICE_FC_TX_PAUSE:
3388fcea6f3dSAnirudh Venkataramanan pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3389fcea6f3dSAnirudh Venkataramanan break;
3390fcea6f3dSAnirudh Venkataramanan default:
3391fcea6f3dSAnirudh Venkataramanan break;
3392fcea6f3dSAnirudh Venkataramanan }
3393fcea6f3dSAnirudh Venkataramanan
33942ffb6085SPaul Greenwalt /* clear the old pause settings */
33952ffb6085SPaul Greenwalt cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
33962ffb6085SPaul Greenwalt ICE_AQC_PHY_EN_RX_LINK_PAUSE);
33972ffb6085SPaul Greenwalt
33982ffb6085SPaul Greenwalt /* set the new capabilities */
33992ffb6085SPaul Greenwalt cfg->caps |= pause_mask;
34002ffb6085SPaul Greenwalt
34011a3571b5SPaul Greenwalt /* Cache user FC request */
34021a3571b5SPaul Greenwalt cache_data.data.curr_user_fc_req = req_mode;
34031a3571b5SPaul Greenwalt ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
34041a3571b5SPaul Greenwalt
34052ffb6085SPaul Greenwalt return 0;
34062ffb6085SPaul Greenwalt }
34072ffb6085SPaul Greenwalt
34082ffb6085SPaul Greenwalt /**
34092ffb6085SPaul Greenwalt * ice_set_fc
34102ffb6085SPaul Greenwalt * @pi: port information structure
34112ffb6085SPaul Greenwalt * @aq_failures: pointer to status code, specific to ice_set_fc routine
34122ffb6085SPaul Greenwalt * @ena_auto_link_update: enable automatic link update
34132ffb6085SPaul Greenwalt *
34142ffb6085SPaul Greenwalt * Set the requested flow control mode.
34152ffb6085SPaul Greenwalt */
34165e24d598STony Nguyen int
ice_set_fc(struct ice_port_info * pi,u8 * aq_failures,bool ena_auto_link_update)34172ffb6085SPaul Greenwalt ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
34182ffb6085SPaul Greenwalt {
34192ffb6085SPaul Greenwalt struct ice_aqc_set_phy_cfg_data cfg = { 0 };
34202ffb6085SPaul Greenwalt struct ice_aqc_get_phy_caps_data *pcaps;
34212ffb6085SPaul Greenwalt struct ice_hw *hw;
34225518ac2aSTony Nguyen int status;
34232ffb6085SPaul Greenwalt
34241a3571b5SPaul Greenwalt if (!pi || !aq_failures)
3425d54699e2STony Nguyen return -EINVAL;
34262ffb6085SPaul Greenwalt
34272ffb6085SPaul Greenwalt *aq_failures = 0;
34282ffb6085SPaul Greenwalt hw = pi->hw;
34292ffb6085SPaul Greenwalt
3430fcea6f3dSAnirudh Venkataramanan pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
3431fcea6f3dSAnirudh Venkataramanan if (!pcaps)
3432d54699e2STony Nguyen return -ENOMEM;
3433fcea6f3dSAnirudh Venkataramanan
3434f9867df6SAnirudh Venkataramanan /* Get the current PHY config */
3435d6730a87SAnirudh Venkataramanan status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3436d6730a87SAnirudh Venkataramanan pcaps, NULL);
3437fcea6f3dSAnirudh Venkataramanan if (status) {
3438fcea6f3dSAnirudh Venkataramanan *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
3439fcea6f3dSAnirudh Venkataramanan goto out;
3440fcea6f3dSAnirudh Venkataramanan }
3441fcea6f3dSAnirudh Venkataramanan
3442ea78ce4dSPaul Greenwalt ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
3443d8df260aSChinh T Cao
34442ffb6085SPaul Greenwalt /* Configure the set PHY data */
34451a3571b5SPaul Greenwalt status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
34462ffb6085SPaul Greenwalt if (status)
34472ffb6085SPaul Greenwalt goto out;
3448d8df260aSChinh T Cao
3449fcea6f3dSAnirudh Venkataramanan /* If the capabilities have changed, then set the new config */
3450fcea6f3dSAnirudh Venkataramanan if (cfg.caps != pcaps->caps) {
3451fcea6f3dSAnirudh Venkataramanan int retry_count, retry_max = 10;
3452fcea6f3dSAnirudh Venkataramanan
3453fcea6f3dSAnirudh Venkataramanan /* Auto restart link so settings take effect */
345448cb27f2SChinh Cao if (ena_auto_link_update)
345548cb27f2SChinh Cao cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3456fcea6f3dSAnirudh Venkataramanan
34571a3571b5SPaul Greenwalt status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3458fcea6f3dSAnirudh Venkataramanan if (status) {
3459fcea6f3dSAnirudh Venkataramanan *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
3460fcea6f3dSAnirudh Venkataramanan goto out;
3461fcea6f3dSAnirudh Venkataramanan }
3462fcea6f3dSAnirudh Venkataramanan
3463fcea6f3dSAnirudh Venkataramanan /* Update the link info
3464fcea6f3dSAnirudh Venkataramanan * It sometimes takes a really long time for link to
3465fcea6f3dSAnirudh Venkataramanan * come back from the atomic reset. Thus, we wait a
3466fcea6f3dSAnirudh Venkataramanan * little bit.
3467fcea6f3dSAnirudh Venkataramanan */
3468fcea6f3dSAnirudh Venkataramanan for (retry_count = 0; retry_count < retry_max; retry_count++) {
3469fcea6f3dSAnirudh Venkataramanan status = ice_update_link_info(pi);
3470fcea6f3dSAnirudh Venkataramanan
3471fcea6f3dSAnirudh Venkataramanan if (!status)
3472fcea6f3dSAnirudh Venkataramanan break;
3473fcea6f3dSAnirudh Venkataramanan
3474fcea6f3dSAnirudh Venkataramanan mdelay(100);
3475fcea6f3dSAnirudh Venkataramanan }
3476fcea6f3dSAnirudh Venkataramanan
3477fcea6f3dSAnirudh Venkataramanan if (status)
3478fcea6f3dSAnirudh Venkataramanan *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
3479fcea6f3dSAnirudh Venkataramanan }
3480fcea6f3dSAnirudh Venkataramanan
3481fcea6f3dSAnirudh Venkataramanan out:
3482fcea6f3dSAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), pcaps);
3483fcea6f3dSAnirudh Venkataramanan return status;
3484fcea6f3dSAnirudh Venkataramanan }
3485fcea6f3dSAnirudh Venkataramanan
3486fcea6f3dSAnirudh Venkataramanan /**
34871a3571b5SPaul Greenwalt * ice_phy_caps_equals_cfg
34881a3571b5SPaul Greenwalt * @phy_caps: PHY capabilities
34891a3571b5SPaul Greenwalt * @phy_cfg: PHY configuration
34901a3571b5SPaul Greenwalt *
34911a3571b5SPaul Greenwalt * Helper function to determine if PHY capabilities matches PHY
34921a3571b5SPaul Greenwalt * configuration
34931a3571b5SPaul Greenwalt */
34941a3571b5SPaul Greenwalt bool
ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data * phy_caps,struct ice_aqc_set_phy_cfg_data * phy_cfg)34951a3571b5SPaul Greenwalt ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
34961a3571b5SPaul Greenwalt struct ice_aqc_set_phy_cfg_data *phy_cfg)
34971a3571b5SPaul Greenwalt {
34981a3571b5SPaul Greenwalt u8 caps_mask, cfg_mask;
34991a3571b5SPaul Greenwalt
35001a3571b5SPaul Greenwalt if (!phy_caps || !phy_cfg)
35011a3571b5SPaul Greenwalt return false;
35021a3571b5SPaul Greenwalt
35031a3571b5SPaul Greenwalt /* These bits are not common between capabilities and configuration.
35041a3571b5SPaul Greenwalt * Do not use them to determine equality.
35051a3571b5SPaul Greenwalt */
35061a3571b5SPaul Greenwalt caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
35071a3571b5SPaul Greenwalt ICE_AQC_GET_PHY_EN_MOD_QUAL);
35081a3571b5SPaul Greenwalt cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
35091a3571b5SPaul Greenwalt
35101a3571b5SPaul Greenwalt if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
35111a3571b5SPaul Greenwalt phy_caps->phy_type_high != phy_cfg->phy_type_high ||
35121a3571b5SPaul Greenwalt ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
3513bdeff971SLev Faerman phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
35141a3571b5SPaul Greenwalt phy_caps->eee_cap != phy_cfg->eee_cap ||
35151a3571b5SPaul Greenwalt phy_caps->eeer_value != phy_cfg->eeer_value ||
35161a3571b5SPaul Greenwalt phy_caps->link_fec_options != phy_cfg->link_fec_opt)
35171a3571b5SPaul Greenwalt return false;
35181a3571b5SPaul Greenwalt
35191a3571b5SPaul Greenwalt return true;
35201a3571b5SPaul Greenwalt }
35211a3571b5SPaul Greenwalt
35221a3571b5SPaul Greenwalt /**
3523f776b3acSPaul Greenwalt * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
3524ea78ce4dSPaul Greenwalt * @pi: port information structure
3525f776b3acSPaul Greenwalt * @caps: PHY ability structure to copy date from
3526f776b3acSPaul Greenwalt * @cfg: PHY configuration structure to copy data to
3527f776b3acSPaul Greenwalt *
3528f776b3acSPaul Greenwalt * Helper function to copy AQC PHY get ability data to PHY set configuration
3529f776b3acSPaul Greenwalt * data structure
3530f776b3acSPaul Greenwalt */
3531f776b3acSPaul Greenwalt void
ice_copy_phy_caps_to_cfg(struct ice_port_info * pi,struct ice_aqc_get_phy_caps_data * caps,struct ice_aqc_set_phy_cfg_data * cfg)3532ea78ce4dSPaul Greenwalt ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
3533ea78ce4dSPaul Greenwalt struct ice_aqc_get_phy_caps_data *caps,
3534f776b3acSPaul Greenwalt struct ice_aqc_set_phy_cfg_data *cfg)
3535f776b3acSPaul Greenwalt {
3536ea78ce4dSPaul Greenwalt if (!pi || !caps || !cfg)
3537f776b3acSPaul Greenwalt return;
3538f776b3acSPaul Greenwalt
35392ffb6085SPaul Greenwalt memset(cfg, 0, sizeof(*cfg));
3540f776b3acSPaul Greenwalt cfg->phy_type_low = caps->phy_type_low;
3541f776b3acSPaul Greenwalt cfg->phy_type_high = caps->phy_type_high;
3542f776b3acSPaul Greenwalt cfg->caps = caps->caps;
3543bdeff971SLev Faerman cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
3544f776b3acSPaul Greenwalt cfg->eee_cap = caps->eee_cap;
3545f776b3acSPaul Greenwalt cfg->eeer_value = caps->eeer_value;
3546f776b3acSPaul Greenwalt cfg->link_fec_opt = caps->link_fec_options;
3547ea78ce4dSPaul Greenwalt cfg->module_compliance_enforcement =
3548ea78ce4dSPaul Greenwalt caps->module_compliance_enforcement;
3549f776b3acSPaul Greenwalt }
3550f776b3acSPaul Greenwalt
3551f776b3acSPaul Greenwalt /**
3552f776b3acSPaul Greenwalt * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
355361cf42e7SPaul Greenwalt * @pi: port information structure
3554f776b3acSPaul Greenwalt * @cfg: PHY configuration data to set FEC mode
3555f776b3acSPaul Greenwalt * @fec: FEC mode to configure
3556f776b3acSPaul Greenwalt */
35575e24d598STony Nguyen int
ice_cfg_phy_fec(struct ice_port_info * pi,struct ice_aqc_set_phy_cfg_data * cfg,enum ice_fec_mode fec)355861cf42e7SPaul Greenwalt ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
355961cf42e7SPaul Greenwalt enum ice_fec_mode fec)
3560f776b3acSPaul Greenwalt {
356161cf42e7SPaul Greenwalt struct ice_aqc_get_phy_caps_data *pcaps;
35620a02944fSAnirudh Venkataramanan struct ice_hw *hw;
35635518ac2aSTony Nguyen int status;
356461cf42e7SPaul Greenwalt
356561cf42e7SPaul Greenwalt if (!pi || !cfg)
3566d54699e2STony Nguyen return -EINVAL;
356761cf42e7SPaul Greenwalt
35680a02944fSAnirudh Venkataramanan hw = pi->hw;
35690a02944fSAnirudh Venkataramanan
357061cf42e7SPaul Greenwalt pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
357161cf42e7SPaul Greenwalt if (!pcaps)
3572d54699e2STony Nguyen return -ENOMEM;
357361cf42e7SPaul Greenwalt
35740a02944fSAnirudh Venkataramanan status = ice_aq_get_phy_caps(pi, false,
35750a02944fSAnirudh Venkataramanan (ice_fw_supports_report_dflt_cfg(hw) ?
35760a02944fSAnirudh Venkataramanan ICE_AQC_REPORT_DFLT_CFG :
35770a02944fSAnirudh Venkataramanan ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL);
357861cf42e7SPaul Greenwalt if (status)
357961cf42e7SPaul Greenwalt goto out;
358061cf42e7SPaul Greenwalt
358161cf42e7SPaul Greenwalt cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC;
358261cf42e7SPaul Greenwalt cfg->link_fec_opt = pcaps->link_fec_options;
358361cf42e7SPaul Greenwalt
3584f776b3acSPaul Greenwalt switch (fec) {
3585f776b3acSPaul Greenwalt case ICE_FEC_BASER:
35863747f031SChinh T Cao /* Clear RS bits, and AND BASE-R ability
3587f776b3acSPaul Greenwalt * bits and OR request bits.
3588f776b3acSPaul Greenwalt */
3589f776b3acSPaul Greenwalt cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3590f776b3acSPaul Greenwalt ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
3591f776b3acSPaul Greenwalt cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3592f776b3acSPaul Greenwalt ICE_AQC_PHY_FEC_25G_KR_REQ;
3593f776b3acSPaul Greenwalt break;
3594f776b3acSPaul Greenwalt case ICE_FEC_RS:
35953747f031SChinh T Cao /* Clear BASE-R bits, and AND RS ability
3596f776b3acSPaul Greenwalt * bits and OR request bits.
3597f776b3acSPaul Greenwalt */
3598f776b3acSPaul Greenwalt cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
3599f776b3acSPaul Greenwalt cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3600f776b3acSPaul Greenwalt ICE_AQC_PHY_FEC_25G_RS_544_REQ;
3601f776b3acSPaul Greenwalt break;
3602f776b3acSPaul Greenwalt case ICE_FEC_NONE:
36033747f031SChinh T Cao /* Clear all FEC option bits. */
3604f776b3acSPaul Greenwalt cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
3605f776b3acSPaul Greenwalt break;
3606f776b3acSPaul Greenwalt case ICE_FEC_AUTO:
3607f776b3acSPaul Greenwalt /* AND auto FEC bit, and all caps bits. */
3608f776b3acSPaul Greenwalt cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
360961cf42e7SPaul Greenwalt cfg->link_fec_opt |= pcaps->link_fec_options;
361061cf42e7SPaul Greenwalt break;
361161cf42e7SPaul Greenwalt default:
3612d54699e2STony Nguyen status = -EINVAL;
3613f776b3acSPaul Greenwalt break;
3614f776b3acSPaul Greenwalt }
361561cf42e7SPaul Greenwalt
361675751c80SJeb Cramer if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) &&
361775751c80SJeb Cramer !ice_fw_supports_report_dflt_cfg(hw)) {
36185950bdc8STom Rix struct ice_link_default_override_tlv tlv = { 0 };
3619ea78ce4dSPaul Greenwalt
362021338d58SDan Carpenter status = ice_get_link_default_override(&tlv, pi);
362121338d58SDan Carpenter if (status)
3622ea78ce4dSPaul Greenwalt goto out;
3623ea78ce4dSPaul Greenwalt
3624ea78ce4dSPaul Greenwalt if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
3625ea78ce4dSPaul Greenwalt (tlv.options & ICE_LINK_OVERRIDE_EN))
3626ea78ce4dSPaul Greenwalt cfg->link_fec_opt = tlv.fec_options;
3627ea78ce4dSPaul Greenwalt }
3628ea78ce4dSPaul Greenwalt
362961cf42e7SPaul Greenwalt out:
363061cf42e7SPaul Greenwalt kfree(pcaps);
363161cf42e7SPaul Greenwalt
363261cf42e7SPaul Greenwalt return status;
3633f776b3acSPaul Greenwalt }
3634f776b3acSPaul Greenwalt
3635f776b3acSPaul Greenwalt /**
36360b28b702SAnirudh Venkataramanan * ice_get_link_status - get status of the HW network link
36370b28b702SAnirudh Venkataramanan * @pi: port information structure
36380b28b702SAnirudh Venkataramanan * @link_up: pointer to bool (true/false = linkup/linkdown)
36390b28b702SAnirudh Venkataramanan *
36400b28b702SAnirudh Venkataramanan * Variable link_up is true if link is up, false if link is down.
36410b28b702SAnirudh Venkataramanan * The variable link_up is invalid if status is non zero. As a
36420b28b702SAnirudh Venkataramanan * result of this call, link status reporting becomes enabled
36430b28b702SAnirudh Venkataramanan */
ice_get_link_status(struct ice_port_info * pi,bool * link_up)36445e24d598STony Nguyen int ice_get_link_status(struct ice_port_info *pi, bool *link_up)
36450b28b702SAnirudh Venkataramanan {
36460b28b702SAnirudh Venkataramanan struct ice_phy_info *phy_info;
36475e24d598STony Nguyen int status = 0;
36480b28b702SAnirudh Venkataramanan
3649c7f2c42bSAnirudh Venkataramanan if (!pi || !link_up)
3650d54699e2STony Nguyen return -EINVAL;
36510b28b702SAnirudh Venkataramanan
36520b28b702SAnirudh Venkataramanan phy_info = &pi->phy;
36530b28b702SAnirudh Venkataramanan
36540b28b702SAnirudh Venkataramanan if (phy_info->get_link_info) {
36550b28b702SAnirudh Venkataramanan status = ice_update_link_info(pi);
36560b28b702SAnirudh Venkataramanan
36570b28b702SAnirudh Venkataramanan if (status)
36589228d8b2SJacob Keller ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n",
36590b28b702SAnirudh Venkataramanan status);
36600b28b702SAnirudh Venkataramanan }
36610b28b702SAnirudh Venkataramanan
36620b28b702SAnirudh Venkataramanan *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
36630b28b702SAnirudh Venkataramanan
36640b28b702SAnirudh Venkataramanan return status;
36650b28b702SAnirudh Venkataramanan }
36660b28b702SAnirudh Venkataramanan
36670b28b702SAnirudh Venkataramanan /**
3668fcea6f3dSAnirudh Venkataramanan * ice_aq_set_link_restart_an
3669fcea6f3dSAnirudh Venkataramanan * @pi: pointer to the port information structure
3670fcea6f3dSAnirudh Venkataramanan * @ena_link: if true: enable link, if false: disable link
3671fcea6f3dSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
3672fcea6f3dSAnirudh Venkataramanan *
3673fcea6f3dSAnirudh Venkataramanan * Sets up the link and restarts the Auto-Negotiation over the link.
3674fcea6f3dSAnirudh Venkataramanan */
36755e24d598STony Nguyen int
ice_aq_set_link_restart_an(struct ice_port_info * pi,bool ena_link,struct ice_sq_cd * cd)3676fcea6f3dSAnirudh Venkataramanan ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
3677fcea6f3dSAnirudh Venkataramanan struct ice_sq_cd *cd)
3678fcea6f3dSAnirudh Venkataramanan {
3679fcea6f3dSAnirudh Venkataramanan struct ice_aqc_restart_an *cmd;
3680fcea6f3dSAnirudh Venkataramanan struct ice_aq_desc desc;
3681fcea6f3dSAnirudh Venkataramanan
3682fcea6f3dSAnirudh Venkataramanan cmd = &desc.params.restart_an;
3683fcea6f3dSAnirudh Venkataramanan
3684fcea6f3dSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
3685fcea6f3dSAnirudh Venkataramanan
3686fcea6f3dSAnirudh Venkataramanan cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
3687fcea6f3dSAnirudh Venkataramanan cmd->lport_num = pi->lport;
3688fcea6f3dSAnirudh Venkataramanan if (ena_link)
3689fcea6f3dSAnirudh Venkataramanan cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
3690fcea6f3dSAnirudh Venkataramanan else
3691fcea6f3dSAnirudh Venkataramanan cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
3692fcea6f3dSAnirudh Venkataramanan
3693fcea6f3dSAnirudh Venkataramanan return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
3694fcea6f3dSAnirudh Venkataramanan }
3695fcea6f3dSAnirudh Venkataramanan
3696fcea6f3dSAnirudh Venkataramanan /**
3697250c3b3eSBrett Creeley * ice_aq_set_event_mask
3698250c3b3eSBrett Creeley * @hw: pointer to the HW struct
3699250c3b3eSBrett Creeley * @port_num: port number of the physical function
3700250c3b3eSBrett Creeley * @mask: event mask to be set
3701250c3b3eSBrett Creeley * @cd: pointer to command details structure or NULL
3702250c3b3eSBrett Creeley *
3703250c3b3eSBrett Creeley * Set event mask (0x0613)
3704250c3b3eSBrett Creeley */
37055e24d598STony Nguyen int
ice_aq_set_event_mask(struct ice_hw * hw,u8 port_num,u16 mask,struct ice_sq_cd * cd)3706250c3b3eSBrett Creeley ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3707250c3b3eSBrett Creeley struct ice_sq_cd *cd)
3708250c3b3eSBrett Creeley {
3709250c3b3eSBrett Creeley struct ice_aqc_set_event_mask *cmd;
3710250c3b3eSBrett Creeley struct ice_aq_desc desc;
3711250c3b3eSBrett Creeley
3712250c3b3eSBrett Creeley cmd = &desc.params.set_event_mask;
3713250c3b3eSBrett Creeley
3714250c3b3eSBrett Creeley ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
3715250c3b3eSBrett Creeley
3716250c3b3eSBrett Creeley cmd->lport_num = port_num;
3717250c3b3eSBrett Creeley
3718250c3b3eSBrett Creeley cmd->event_mask = cpu_to_le16(mask);
3719250c3b3eSBrett Creeley return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3720250c3b3eSBrett Creeley }
3721250c3b3eSBrett Creeley
3722250c3b3eSBrett Creeley /**
37230e674aebSAnirudh Venkataramanan * ice_aq_set_mac_loopback
37240e674aebSAnirudh Venkataramanan * @hw: pointer to the HW struct
37250e674aebSAnirudh Venkataramanan * @ena_lpbk: Enable or Disable loopback
37260e674aebSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
37270e674aebSAnirudh Venkataramanan *
37280e674aebSAnirudh Venkataramanan * Enable/disable loopback on a given port
37290e674aebSAnirudh Venkataramanan */
37305e24d598STony Nguyen int
ice_aq_set_mac_loopback(struct ice_hw * hw,bool ena_lpbk,struct ice_sq_cd * cd)37310e674aebSAnirudh Venkataramanan ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
37320e674aebSAnirudh Venkataramanan {
37330e674aebSAnirudh Venkataramanan struct ice_aqc_set_mac_lb *cmd;
37340e674aebSAnirudh Venkataramanan struct ice_aq_desc desc;
37350e674aebSAnirudh Venkataramanan
37360e674aebSAnirudh Venkataramanan cmd = &desc.params.set_mac_lb;
37370e674aebSAnirudh Venkataramanan
37380e674aebSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
37390e674aebSAnirudh Venkataramanan if (ena_lpbk)
37400e674aebSAnirudh Venkataramanan cmd->lb_mode = ICE_AQ_MAC_LB_EN;
37410e674aebSAnirudh Venkataramanan
37420e674aebSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
37430e674aebSAnirudh Venkataramanan }
37440e674aebSAnirudh Venkataramanan
37450e674aebSAnirudh Venkataramanan /**
37468e151d50SAnirudh Venkataramanan * ice_aq_set_port_id_led
37478e151d50SAnirudh Venkataramanan * @pi: pointer to the port information
37488e151d50SAnirudh Venkataramanan * @is_orig_mode: is this LED set to original mode (by the net-list)
37498e151d50SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
37508e151d50SAnirudh Venkataramanan *
37518e151d50SAnirudh Venkataramanan * Set LED value for the given port (0x06e9)
37528e151d50SAnirudh Venkataramanan */
37535e24d598STony Nguyen int
ice_aq_set_port_id_led(struct ice_port_info * pi,bool is_orig_mode,struct ice_sq_cd * cd)37548e151d50SAnirudh Venkataramanan ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
37558e151d50SAnirudh Venkataramanan struct ice_sq_cd *cd)
37568e151d50SAnirudh Venkataramanan {
37578e151d50SAnirudh Venkataramanan struct ice_aqc_set_port_id_led *cmd;
37588e151d50SAnirudh Venkataramanan struct ice_hw *hw = pi->hw;
37598e151d50SAnirudh Venkataramanan struct ice_aq_desc desc;
37608e151d50SAnirudh Venkataramanan
37618e151d50SAnirudh Venkataramanan cmd = &desc.params.set_port_id_led;
37628e151d50SAnirudh Venkataramanan
37638e151d50SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
37648e151d50SAnirudh Venkataramanan
37658e151d50SAnirudh Venkataramanan if (is_orig_mode)
37668e151d50SAnirudh Venkataramanan cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
37678e151d50SAnirudh Venkataramanan else
37688e151d50SAnirudh Venkataramanan cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
37698e151d50SAnirudh Venkataramanan
37708e151d50SAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
37718e151d50SAnirudh Venkataramanan }
37728e151d50SAnirudh Venkataramanan
37738e151d50SAnirudh Venkataramanan /**
3774781f15eaSAnatolii Gerasymenko * ice_aq_get_port_options
3775781f15eaSAnatolii Gerasymenko * @hw: pointer to the HW struct
3776781f15eaSAnatolii Gerasymenko * @options: buffer for the resultant port options
3777781f15eaSAnatolii Gerasymenko * @option_count: input - size of the buffer in port options structures,
3778781f15eaSAnatolii Gerasymenko * output - number of returned port options
3779781f15eaSAnatolii Gerasymenko * @lport: logical port to call the command with (optional)
3780781f15eaSAnatolii Gerasymenko * @lport_valid: when false, FW uses port owned by the PF instead of lport,
3781781f15eaSAnatolii Gerasymenko * when PF owns more than 1 port it must be true
3782781f15eaSAnatolii Gerasymenko * @active_option_idx: index of active port option in returned buffer
3783781f15eaSAnatolii Gerasymenko * @active_option_valid: active option in returned buffer is valid
3784781f15eaSAnatolii Gerasymenko * @pending_option_idx: index of pending port option in returned buffer
3785781f15eaSAnatolii Gerasymenko * @pending_option_valid: pending option in returned buffer is valid
3786781f15eaSAnatolii Gerasymenko *
3787781f15eaSAnatolii Gerasymenko * Calls Get Port Options AQC (0x06ea) and verifies result.
3788781f15eaSAnatolii Gerasymenko */
3789781f15eaSAnatolii Gerasymenko int
ice_aq_get_port_options(struct ice_hw * hw,struct ice_aqc_get_port_options_elem * options,u8 * option_count,u8 lport,bool lport_valid,u8 * active_option_idx,bool * active_option_valid,u8 * pending_option_idx,bool * pending_option_valid)3790781f15eaSAnatolii Gerasymenko ice_aq_get_port_options(struct ice_hw *hw,
3791781f15eaSAnatolii Gerasymenko struct ice_aqc_get_port_options_elem *options,
3792781f15eaSAnatolii Gerasymenko u8 *option_count, u8 lport, bool lport_valid,
3793781f15eaSAnatolii Gerasymenko u8 *active_option_idx, bool *active_option_valid,
3794781f15eaSAnatolii Gerasymenko u8 *pending_option_idx, bool *pending_option_valid)
3795781f15eaSAnatolii Gerasymenko {
3796781f15eaSAnatolii Gerasymenko struct ice_aqc_get_port_options *cmd;
3797781f15eaSAnatolii Gerasymenko struct ice_aq_desc desc;
3798781f15eaSAnatolii Gerasymenko int status;
3799781f15eaSAnatolii Gerasymenko u8 i;
3800781f15eaSAnatolii Gerasymenko
3801781f15eaSAnatolii Gerasymenko /* options buffer shall be able to hold max returned options */
3802781f15eaSAnatolii Gerasymenko if (*option_count < ICE_AQC_PORT_OPT_COUNT_M)
3803781f15eaSAnatolii Gerasymenko return -EINVAL;
3804781f15eaSAnatolii Gerasymenko
3805781f15eaSAnatolii Gerasymenko cmd = &desc.params.get_port_options;
3806781f15eaSAnatolii Gerasymenko ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options);
3807781f15eaSAnatolii Gerasymenko
3808781f15eaSAnatolii Gerasymenko if (lport_valid)
3809781f15eaSAnatolii Gerasymenko cmd->lport_num = lport;
3810781f15eaSAnatolii Gerasymenko cmd->lport_num_valid = lport_valid;
3811781f15eaSAnatolii Gerasymenko
3812781f15eaSAnatolii Gerasymenko status = ice_aq_send_cmd(hw, &desc, options,
3813781f15eaSAnatolii Gerasymenko *option_count * sizeof(*options), NULL);
3814781f15eaSAnatolii Gerasymenko if (status)
3815781f15eaSAnatolii Gerasymenko return status;
3816781f15eaSAnatolii Gerasymenko
3817781f15eaSAnatolii Gerasymenko /* verify direct FW response & set output parameters */
3818781f15eaSAnatolii Gerasymenko *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M,
3819781f15eaSAnatolii Gerasymenko cmd->port_options_count);
3820781f15eaSAnatolii Gerasymenko ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count);
3821781f15eaSAnatolii Gerasymenko *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID,
3822781f15eaSAnatolii Gerasymenko cmd->port_options);
3823781f15eaSAnatolii Gerasymenko if (*active_option_valid) {
3824781f15eaSAnatolii Gerasymenko *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M,
3825781f15eaSAnatolii Gerasymenko cmd->port_options);
3826781f15eaSAnatolii Gerasymenko if (*active_option_idx > (*option_count - 1))
3827781f15eaSAnatolii Gerasymenko return -EIO;
3828781f15eaSAnatolii Gerasymenko ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n",
3829781f15eaSAnatolii Gerasymenko *active_option_idx);
3830781f15eaSAnatolii Gerasymenko }
3831781f15eaSAnatolii Gerasymenko
3832781f15eaSAnatolii Gerasymenko *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID,
3833781f15eaSAnatolii Gerasymenko cmd->pending_port_option_status);
3834781f15eaSAnatolii Gerasymenko if (*pending_option_valid) {
3835781f15eaSAnatolii Gerasymenko *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M,
3836781f15eaSAnatolii Gerasymenko cmd->pending_port_option_status);
3837781f15eaSAnatolii Gerasymenko if (*pending_option_idx > (*option_count - 1))
3838781f15eaSAnatolii Gerasymenko return -EIO;
3839781f15eaSAnatolii Gerasymenko ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n",
3840781f15eaSAnatolii Gerasymenko *pending_option_idx);
3841781f15eaSAnatolii Gerasymenko }
3842781f15eaSAnatolii Gerasymenko
3843781f15eaSAnatolii Gerasymenko /* mask output options fields */
3844781f15eaSAnatolii Gerasymenko for (i = 0; i < *option_count; i++) {
3845781f15eaSAnatolii Gerasymenko options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M,
3846781f15eaSAnatolii Gerasymenko options[i].pmd);
3847781f15eaSAnatolii Gerasymenko options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M,
3848781f15eaSAnatolii Gerasymenko options[i].max_lane_speed);
3849781f15eaSAnatolii Gerasymenko ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n",
3850781f15eaSAnatolii Gerasymenko options[i].pmd, options[i].max_lane_speed);
3851781f15eaSAnatolii Gerasymenko }
3852781f15eaSAnatolii Gerasymenko
3853781f15eaSAnatolii Gerasymenko return 0;
3854781f15eaSAnatolii Gerasymenko }
3855781f15eaSAnatolii Gerasymenko
3856781f15eaSAnatolii Gerasymenko /**
3857781f15eaSAnatolii Gerasymenko * ice_aq_set_port_option
3858781f15eaSAnatolii Gerasymenko * @hw: pointer to the HW struct
3859781f15eaSAnatolii Gerasymenko * @lport: logical port to call the command with
3860781f15eaSAnatolii Gerasymenko * @lport_valid: when false, FW uses port owned by the PF instead of lport,
3861781f15eaSAnatolii Gerasymenko * when PF owns more than 1 port it must be true
3862781f15eaSAnatolii Gerasymenko * @new_option: new port option to be written
3863781f15eaSAnatolii Gerasymenko *
3864781f15eaSAnatolii Gerasymenko * Calls Set Port Options AQC (0x06eb).
3865781f15eaSAnatolii Gerasymenko */
3866781f15eaSAnatolii Gerasymenko int
ice_aq_set_port_option(struct ice_hw * hw,u8 lport,u8 lport_valid,u8 new_option)3867781f15eaSAnatolii Gerasymenko ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
3868781f15eaSAnatolii Gerasymenko u8 new_option)
3869781f15eaSAnatolii Gerasymenko {
3870781f15eaSAnatolii Gerasymenko struct ice_aqc_set_port_option *cmd;
3871781f15eaSAnatolii Gerasymenko struct ice_aq_desc desc;
3872781f15eaSAnatolii Gerasymenko
3873781f15eaSAnatolii Gerasymenko if (new_option > ICE_AQC_PORT_OPT_COUNT_M)
3874781f15eaSAnatolii Gerasymenko return -EINVAL;
3875781f15eaSAnatolii Gerasymenko
3876781f15eaSAnatolii Gerasymenko cmd = &desc.params.set_port_option;
3877781f15eaSAnatolii Gerasymenko ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option);
3878781f15eaSAnatolii Gerasymenko
3879781f15eaSAnatolii Gerasymenko if (lport_valid)
3880781f15eaSAnatolii Gerasymenko cmd->lport_num = lport;
3881781f15eaSAnatolii Gerasymenko
3882781f15eaSAnatolii Gerasymenko cmd->lport_num_valid = lport_valid;
3883781f15eaSAnatolii Gerasymenko cmd->selected_port_option = new_option;
3884781f15eaSAnatolii Gerasymenko
3885781f15eaSAnatolii Gerasymenko return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
3886781f15eaSAnatolii Gerasymenko }
3887781f15eaSAnatolii Gerasymenko
3888781f15eaSAnatolii Gerasymenko /**
3889a012dca9SScott W Taylor * ice_aq_sff_eeprom
3890a012dca9SScott W Taylor * @hw: pointer to the HW struct
3891a012dca9SScott W Taylor * @lport: bits [7:0] = logical port, bit [8] = logical port valid
3892a012dca9SScott W Taylor * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
3893a012dca9SScott W Taylor * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3894a012dca9SScott W Taylor * @page: QSFP page
3895a012dca9SScott W Taylor * @set_page: set or ignore the page
3896a012dca9SScott W Taylor * @data: pointer to data buffer to be read/written to the I2C device.
3897a012dca9SScott W Taylor * @length: 1-16 for read, 1 for write.
3898a012dca9SScott W Taylor * @write: 0 read, 1 for write.
3899a012dca9SScott W Taylor * @cd: pointer to command details structure or NULL
3900a012dca9SScott W Taylor *
3901a012dca9SScott W Taylor * Read/Write SFF EEPROM (0x06EE)
3902a012dca9SScott W Taylor */
39035e24d598STony Nguyen int
ice_aq_sff_eeprom(struct ice_hw * hw,u16 lport,u8 bus_addr,u16 mem_addr,u8 page,u8 set_page,u8 * data,u8 length,bool write,struct ice_sq_cd * cd)3904a012dca9SScott W Taylor ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3905a012dca9SScott W Taylor u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3906a012dca9SScott W Taylor bool write, struct ice_sq_cd *cd)
3907a012dca9SScott W Taylor {
3908a012dca9SScott W Taylor struct ice_aqc_sff_eeprom *cmd;
3909a012dca9SScott W Taylor struct ice_aq_desc desc;
39105e24d598STony Nguyen int status;
3911a012dca9SScott W Taylor
3912a012dca9SScott W Taylor if (!data || (mem_addr & 0xff00))
3913d54699e2STony Nguyen return -EINVAL;
3914a012dca9SScott W Taylor
3915a012dca9SScott W Taylor ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3916a012dca9SScott W Taylor cmd = &desc.params.read_write_sff_param;
3917800c1443SBruce Allan desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD);
3918a012dca9SScott W Taylor cmd->lport_num = (u8)(lport & 0xff);
3919a012dca9SScott W Taylor cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3920a012dca9SScott W Taylor cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) &
3921a012dca9SScott W Taylor ICE_AQC_SFF_I2CBUS_7BIT_M) |
3922a012dca9SScott W Taylor ((set_page <<
3923a012dca9SScott W Taylor ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3924a012dca9SScott W Taylor ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3925a012dca9SScott W Taylor cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff);
3926a012dca9SScott W Taylor cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3927a012dca9SScott W Taylor if (write)
3928a012dca9SScott W Taylor cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE);
3929a012dca9SScott W Taylor
3930a012dca9SScott W Taylor status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3931a012dca9SScott W Taylor return status;
3932a012dca9SScott W Taylor }
3933a012dca9SScott W Taylor
ice_lut_type_to_size(enum ice_lut_type type)3934b6143c9bSPrzemek Kitszel static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type)
3935b6143c9bSPrzemek Kitszel {
3936b6143c9bSPrzemek Kitszel switch (type) {
3937b6143c9bSPrzemek Kitszel case ICE_LUT_VSI:
3938b6143c9bSPrzemek Kitszel return ICE_LUT_VSI_SIZE;
3939b6143c9bSPrzemek Kitszel case ICE_LUT_GLOBAL:
3940b6143c9bSPrzemek Kitszel return ICE_LUT_GLOBAL_SIZE;
3941b6143c9bSPrzemek Kitszel case ICE_LUT_PF:
3942b6143c9bSPrzemek Kitszel return ICE_LUT_PF_SIZE;
3943b6143c9bSPrzemek Kitszel }
3944b6143c9bSPrzemek Kitszel WARN_ONCE(1, "incorrect type passed");
3945b6143c9bSPrzemek Kitszel return ICE_LUT_VSI_SIZE;
3946b6143c9bSPrzemek Kitszel }
3947b6143c9bSPrzemek Kitszel
ice_lut_size_to_flag(enum ice_lut_size size)3948b6143c9bSPrzemek Kitszel static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size)
3949b6143c9bSPrzemek Kitszel {
3950b6143c9bSPrzemek Kitszel switch (size) {
3951b6143c9bSPrzemek Kitszel case ICE_LUT_VSI_SIZE:
3952b6143c9bSPrzemek Kitszel return ICE_AQC_LUT_SIZE_SMALL;
3953b6143c9bSPrzemek Kitszel case ICE_LUT_GLOBAL_SIZE:
3954b6143c9bSPrzemek Kitszel return ICE_AQC_LUT_SIZE_512;
3955b6143c9bSPrzemek Kitszel case ICE_LUT_PF_SIZE:
3956b6143c9bSPrzemek Kitszel return ICE_AQC_LUT_SIZE_2K;
3957b6143c9bSPrzemek Kitszel }
3958b6143c9bSPrzemek Kitszel WARN_ONCE(1, "incorrect size passed");
3959b6143c9bSPrzemek Kitszel return 0;
3960b6143c9bSPrzemek Kitszel }
3961b6143c9bSPrzemek Kitszel
3962a012dca9SScott W Taylor /**
3963d76a60baSAnirudh Venkataramanan * __ice_aq_get_set_rss_lut
3964d76a60baSAnirudh Venkataramanan * @hw: pointer to the hardware structure
3965e3c53928SBrett Creeley * @params: RSS LUT parameters
3966d76a60baSAnirudh Venkataramanan * @set: set true to set the table, false to get the table
3967d76a60baSAnirudh Venkataramanan *
3968d76a60baSAnirudh Venkataramanan * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3969d76a60baSAnirudh Venkataramanan */
39705e24d598STony Nguyen static int
__ice_aq_get_set_rss_lut(struct ice_hw * hw,struct ice_aq_get_set_rss_lut_params * params,bool set)3971b6143c9bSPrzemek Kitszel __ice_aq_get_set_rss_lut(struct ice_hw *hw,
3972b6143c9bSPrzemek Kitszel struct ice_aq_get_set_rss_lut_params *params, bool set)
3973d76a60baSAnirudh Venkataramanan {
3974b6143c9bSPrzemek Kitszel u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0;
3975b6143c9bSPrzemek Kitszel enum ice_lut_type lut_type = params->lut_type;
3976b6143c9bSPrzemek Kitszel struct ice_aqc_get_set_rss_lut *desc_params;
3977b6143c9bSPrzemek Kitszel enum ice_aqc_lut_flags flags;
3978b6143c9bSPrzemek Kitszel enum ice_lut_size lut_size;
3979d76a60baSAnirudh Venkataramanan struct ice_aq_desc desc;
3980b6143c9bSPrzemek Kitszel u8 *lut = params->lut;
3981e3c53928SBrett Creeley
3982b6143c9bSPrzemek Kitszel
3983b6143c9bSPrzemek Kitszel if (!lut || !ice_is_vsi_valid(hw, vsi_handle))
3984d54699e2STony Nguyen return -EINVAL;
3985e3c53928SBrett Creeley
3986b6143c9bSPrzemek Kitszel lut_size = ice_lut_type_to_size(lut_type);
3987b6143c9bSPrzemek Kitszel if (lut_size > params->lut_size)
3988b6143c9bSPrzemek Kitszel return -EINVAL;
3989b6143c9bSPrzemek Kitszel else if (set && lut_size != params->lut_size)
3990d54699e2STony Nguyen return -EINVAL;
3991e3c53928SBrett Creeley
3992b6143c9bSPrzemek Kitszel opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut;
3993b6143c9bSPrzemek Kitszel ice_fill_dflt_direct_cmd_desc(&desc, opcode);
3994b6143c9bSPrzemek Kitszel if (set)
3995d76a60baSAnirudh Venkataramanan desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3996d76a60baSAnirudh Venkataramanan
3997b6143c9bSPrzemek Kitszel desc_params = &desc.params.get_set_rss_lut;
3998b6143c9bSPrzemek Kitszel vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
3999b6143c9bSPrzemek Kitszel desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID);
4000d76a60baSAnirudh Venkataramanan
4001b6143c9bSPrzemek Kitszel if (lut_type == ICE_LUT_GLOBAL)
4002b6143c9bSPrzemek Kitszel glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX,
4003b6143c9bSPrzemek Kitszel params->global_lut_id);
4004d76a60baSAnirudh Venkataramanan
4005b6143c9bSPrzemek Kitszel flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size);
4006b6143c9bSPrzemek Kitszel desc_params->flags = cpu_to_le16(flags);
4007d76a60baSAnirudh Venkataramanan
4008b6143c9bSPrzemek Kitszel return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
4009d76a60baSAnirudh Venkataramanan }
4010d76a60baSAnirudh Venkataramanan
4011d76a60baSAnirudh Venkataramanan /**
4012d76a60baSAnirudh Venkataramanan * ice_aq_get_rss_lut
4013d76a60baSAnirudh Venkataramanan * @hw: pointer to the hardware structure
4014e3c53928SBrett Creeley * @get_params: RSS LUT parameters used to specify which RSS LUT to get
4015d76a60baSAnirudh Venkataramanan *
4016d76a60baSAnirudh Venkataramanan * get the RSS lookup table, PF or VSI type
4017d76a60baSAnirudh Venkataramanan */
40185e24d598STony Nguyen int
ice_aq_get_rss_lut(struct ice_hw * hw,struct ice_aq_get_set_rss_lut_params * get_params)4019e3c53928SBrett Creeley ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params)
4020d76a60baSAnirudh Venkataramanan {
4021e3c53928SBrett Creeley return __ice_aq_get_set_rss_lut(hw, get_params, false);
4022d76a60baSAnirudh Venkataramanan }
4023d76a60baSAnirudh Venkataramanan
4024d76a60baSAnirudh Venkataramanan /**
4025d76a60baSAnirudh Venkataramanan * ice_aq_set_rss_lut
4026d76a60baSAnirudh Venkataramanan * @hw: pointer to the hardware structure
4027e3c53928SBrett Creeley * @set_params: RSS LUT parameters used to specify how to set the RSS LUT
4028d76a60baSAnirudh Venkataramanan *
4029d76a60baSAnirudh Venkataramanan * set the RSS lookup table, PF or VSI type
4030d76a60baSAnirudh Venkataramanan */
40315e24d598STony Nguyen int
ice_aq_set_rss_lut(struct ice_hw * hw,struct ice_aq_get_set_rss_lut_params * set_params)4032e3c53928SBrett Creeley ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params)
4033d76a60baSAnirudh Venkataramanan {
4034e3c53928SBrett Creeley return __ice_aq_get_set_rss_lut(hw, set_params, true);
4035d76a60baSAnirudh Venkataramanan }
4036d76a60baSAnirudh Venkataramanan
4037d76a60baSAnirudh Venkataramanan /**
4038d76a60baSAnirudh Venkataramanan * __ice_aq_get_set_rss_key
4039f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
4040d76a60baSAnirudh Venkataramanan * @vsi_id: VSI FW index
4041d76a60baSAnirudh Venkataramanan * @key: pointer to key info struct
4042d76a60baSAnirudh Venkataramanan * @set: set true to set the key, false to get the key
4043d76a60baSAnirudh Venkataramanan *
4044d76a60baSAnirudh Venkataramanan * get (0x0B04) or set (0x0B02) the RSS key per VSI
4045d76a60baSAnirudh Venkataramanan */
40465518ac2aSTony Nguyen static int
__ice_aq_get_set_rss_key(struct ice_hw * hw,u16 vsi_id,struct ice_aqc_get_set_rss_keys * key,bool set)40475518ac2aSTony Nguyen __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
40485518ac2aSTony Nguyen struct ice_aqc_get_set_rss_keys *key, bool set)
4049d76a60baSAnirudh Venkataramanan {
4050b6143c9bSPrzemek Kitszel struct ice_aqc_get_set_rss_key *desc_params;
4051d76a60baSAnirudh Venkataramanan u16 key_size = sizeof(*key);
4052d76a60baSAnirudh Venkataramanan struct ice_aq_desc desc;
4053d76a60baSAnirudh Venkataramanan
4054d76a60baSAnirudh Venkataramanan if (set) {
4055d76a60baSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
4056d76a60baSAnirudh Venkataramanan desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4057d76a60baSAnirudh Venkataramanan } else {
4058d76a60baSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
4059d76a60baSAnirudh Venkataramanan }
4060d76a60baSAnirudh Venkataramanan
4061b6143c9bSPrzemek Kitszel desc_params = &desc.params.get_set_rss_key;
4062b6143c9bSPrzemek Kitszel desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID);
4063d76a60baSAnirudh Venkataramanan
4064d76a60baSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
4065d76a60baSAnirudh Venkataramanan }
4066d76a60baSAnirudh Venkataramanan
4067d76a60baSAnirudh Venkataramanan /**
4068d76a60baSAnirudh Venkataramanan * ice_aq_get_rss_key
4069f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
40704fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle
4071d76a60baSAnirudh Venkataramanan * @key: pointer to key info struct
4072d76a60baSAnirudh Venkataramanan *
4073d76a60baSAnirudh Venkataramanan * get the RSS key per VSI
4074d76a60baSAnirudh Venkataramanan */
40755e24d598STony Nguyen int
ice_aq_get_rss_key(struct ice_hw * hw,u16 vsi_handle,struct ice_aqc_get_set_rss_keys * key)40764fb33f31SAnirudh Venkataramanan ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
4077d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_keys *key)
4078d76a60baSAnirudh Venkataramanan {
40794fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
4080d54699e2STony Nguyen return -EINVAL;
40814fb33f31SAnirudh Venkataramanan
40824fb33f31SAnirudh Venkataramanan return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
40834fb33f31SAnirudh Venkataramanan key, false);
4084d76a60baSAnirudh Venkataramanan }
4085d76a60baSAnirudh Venkataramanan
4086d76a60baSAnirudh Venkataramanan /**
4087d76a60baSAnirudh Venkataramanan * ice_aq_set_rss_key
4088f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
40894fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle
4090d76a60baSAnirudh Venkataramanan * @keys: pointer to key info struct
4091d76a60baSAnirudh Venkataramanan *
4092d76a60baSAnirudh Venkataramanan * set the RSS key per VSI
4093d76a60baSAnirudh Venkataramanan */
40945e24d598STony Nguyen int
ice_aq_set_rss_key(struct ice_hw * hw,u16 vsi_handle,struct ice_aqc_get_set_rss_keys * keys)40954fb33f31SAnirudh Venkataramanan ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
4096d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_keys *keys)
4097d76a60baSAnirudh Venkataramanan {
40984fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
4099d54699e2STony Nguyen return -EINVAL;
41004fb33f31SAnirudh Venkataramanan
41014fb33f31SAnirudh Venkataramanan return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
41024fb33f31SAnirudh Venkataramanan keys, true);
4103d76a60baSAnirudh Venkataramanan }
4104d76a60baSAnirudh Venkataramanan
4105d76a60baSAnirudh Venkataramanan /**
4106cdedef59SAnirudh Venkataramanan * ice_aq_add_lan_txq
4107cdedef59SAnirudh Venkataramanan * @hw: pointer to the hardware structure
4108cdedef59SAnirudh Venkataramanan * @num_qgrps: Number of added queue groups
4109cdedef59SAnirudh Venkataramanan * @qg_list: list of queue groups to be added
4110cdedef59SAnirudh Venkataramanan * @buf_size: size of buffer for indirect command
4111cdedef59SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
4112cdedef59SAnirudh Venkataramanan *
4113cdedef59SAnirudh Venkataramanan * Add Tx LAN queue (0x0C30)
4114cdedef59SAnirudh Venkataramanan *
4115cdedef59SAnirudh Venkataramanan * NOTE:
4116cdedef59SAnirudh Venkataramanan * Prior to calling add Tx LAN queue:
4117cdedef59SAnirudh Venkataramanan * Initialize the following as part of the Tx queue context:
4118cdedef59SAnirudh Venkataramanan * Completion queue ID if the queue uses Completion queue, Quanta profile,
4119cdedef59SAnirudh Venkataramanan * Cache profile and Packet shaper profile.
4120cdedef59SAnirudh Venkataramanan *
4121cdedef59SAnirudh Venkataramanan * After add Tx LAN queue AQ command is completed:
4122cdedef59SAnirudh Venkataramanan * Interrupts should be associated with specific queues,
4123cdedef59SAnirudh Venkataramanan * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
4124cdedef59SAnirudh Venkataramanan * flow.
4125cdedef59SAnirudh Venkataramanan */
41265e24d598STony Nguyen static int
ice_aq_add_lan_txq(struct ice_hw * hw,u8 num_qgrps,struct ice_aqc_add_tx_qgrp * qg_list,u16 buf_size,struct ice_sq_cd * cd)4127cdedef59SAnirudh Venkataramanan ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4128cdedef59SAnirudh Venkataramanan struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
4129cdedef59SAnirudh Venkataramanan struct ice_sq_cd *cd)
4130cdedef59SAnirudh Venkataramanan {
4131cdedef59SAnirudh Venkataramanan struct ice_aqc_add_tx_qgrp *list;
4132cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs *cmd;
4133cdedef59SAnirudh Venkataramanan struct ice_aq_desc desc;
413466486d89SBruce Allan u16 i, sum_size = 0;
4135cdedef59SAnirudh Venkataramanan
4136cdedef59SAnirudh Venkataramanan cmd = &desc.params.add_txqs;
4137cdedef59SAnirudh Venkataramanan
4138cdedef59SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
4139cdedef59SAnirudh Venkataramanan
4140cdedef59SAnirudh Venkataramanan if (!qg_list)
4141d54699e2STony Nguyen return -EINVAL;
4142cdedef59SAnirudh Venkataramanan
4143cdedef59SAnirudh Venkataramanan if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4144d54699e2STony Nguyen return -EINVAL;
4145cdedef59SAnirudh Venkataramanan
414666486d89SBruce Allan for (i = 0, list = qg_list; i < num_qgrps; i++) {
414766486d89SBruce Allan sum_size += struct_size(list, txqs, list->num_txqs);
414866486d89SBruce Allan list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
414966486d89SBruce Allan list->num_txqs);
4150cdedef59SAnirudh Venkataramanan }
4151cdedef59SAnirudh Venkataramanan
415266486d89SBruce Allan if (buf_size != sum_size)
4153d54699e2STony Nguyen return -EINVAL;
4154cdedef59SAnirudh Venkataramanan
4155cdedef59SAnirudh Venkataramanan desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4156cdedef59SAnirudh Venkataramanan
4157cdedef59SAnirudh Venkataramanan cmd->num_qgrps = num_qgrps;
4158cdedef59SAnirudh Venkataramanan
4159cdedef59SAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
4160cdedef59SAnirudh Venkataramanan }
4161cdedef59SAnirudh Venkataramanan
4162cdedef59SAnirudh Venkataramanan /**
4163cdedef59SAnirudh Venkataramanan * ice_aq_dis_lan_txq
4164cdedef59SAnirudh Venkataramanan * @hw: pointer to the hardware structure
4165cdedef59SAnirudh Venkataramanan * @num_qgrps: number of groups in the list
4166cdedef59SAnirudh Venkataramanan * @qg_list: the list of groups to disable
4167cdedef59SAnirudh Venkataramanan * @buf_size: the total size of the qg_list buffer in bytes
416894c4441bSAnirudh Venkataramanan * @rst_src: if called due to reset, specifies the reset source
4169ddf30f7fSAnirudh Venkataramanan * @vmvf_num: the relative VM or VF number that is undergoing the reset
4170cdedef59SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
4171cdedef59SAnirudh Venkataramanan *
4172cdedef59SAnirudh Venkataramanan * Disable LAN Tx queue (0x0C31)
4173cdedef59SAnirudh Venkataramanan */
41745e24d598STony Nguyen static int
ice_aq_dis_lan_txq(struct ice_hw * hw,u8 num_qgrps,struct ice_aqc_dis_txq_item * qg_list,u16 buf_size,enum ice_disq_rst_src rst_src,u16 vmvf_num,struct ice_sq_cd * cd)4175cdedef59SAnirudh Venkataramanan ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4176cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
4177ddf30f7fSAnirudh Venkataramanan enum ice_disq_rst_src rst_src, u16 vmvf_num,
4178cdedef59SAnirudh Venkataramanan struct ice_sq_cd *cd)
4179cdedef59SAnirudh Venkataramanan {
418066486d89SBruce Allan struct ice_aqc_dis_txq_item *item;
4181cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txqs *cmd;
4182cdedef59SAnirudh Venkataramanan struct ice_aq_desc desc;
4183cdedef59SAnirudh Venkataramanan u16 i, sz = 0;
41845518ac2aSTony Nguyen int status;
4185cdedef59SAnirudh Venkataramanan
4186cdedef59SAnirudh Venkataramanan cmd = &desc.params.dis_txqs;
4187cdedef59SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
4188cdedef59SAnirudh Venkataramanan
4189ddf30f7fSAnirudh Venkataramanan /* qg_list can be NULL only in VM/VF reset flow */
4190ddf30f7fSAnirudh Venkataramanan if (!qg_list && !rst_src)
4191d54699e2STony Nguyen return -EINVAL;
4192cdedef59SAnirudh Venkataramanan
4193cdedef59SAnirudh Venkataramanan if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4194d54699e2STony Nguyen return -EINVAL;
4195ddf30f7fSAnirudh Venkataramanan
4196cdedef59SAnirudh Venkataramanan cmd->num_entries = num_qgrps;
4197cdedef59SAnirudh Venkataramanan
4198ddf30f7fSAnirudh Venkataramanan cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
4199ddf30f7fSAnirudh Venkataramanan ICE_AQC_Q_DIS_TIMEOUT_M);
4200ddf30f7fSAnirudh Venkataramanan
4201ddf30f7fSAnirudh Venkataramanan switch (rst_src) {
4202ddf30f7fSAnirudh Venkataramanan case ICE_VM_RESET:
4203ddf30f7fSAnirudh Venkataramanan cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
4204ddf30f7fSAnirudh Venkataramanan cmd->vmvf_and_timeout |=
4205ddf30f7fSAnirudh Venkataramanan cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
4206ddf30f7fSAnirudh Venkataramanan break;
4207ddf30f7fSAnirudh Venkataramanan case ICE_VF_RESET:
4208ddf30f7fSAnirudh Venkataramanan cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;
4209f9867df6SAnirudh Venkataramanan /* In this case, FW expects vmvf_num to be absolute VF ID */
4210ddf30f7fSAnirudh Venkataramanan cmd->vmvf_and_timeout |=
4211ddf30f7fSAnirudh Venkataramanan cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) &
4212ddf30f7fSAnirudh Venkataramanan ICE_AQC_Q_DIS_VMVF_NUM_M);
4213ddf30f7fSAnirudh Venkataramanan break;
4214ddf30f7fSAnirudh Venkataramanan case ICE_NO_RESET:
4215ddf30f7fSAnirudh Venkataramanan default:
4216ddf30f7fSAnirudh Venkataramanan break;
4217ddf30f7fSAnirudh Venkataramanan }
4218ddf30f7fSAnirudh Venkataramanan
42196e9650d5SVictor Raj /* flush pipe on time out */
42206e9650d5SVictor Raj cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
4221ddf30f7fSAnirudh Venkataramanan /* If no queue group info, we are in a reset flow. Issue the AQ */
4222ddf30f7fSAnirudh Venkataramanan if (!qg_list)
4223ddf30f7fSAnirudh Venkataramanan goto do_aq;
4224ddf30f7fSAnirudh Venkataramanan
4225ddf30f7fSAnirudh Venkataramanan /* set RD bit to indicate that command buffer is provided by the driver
4226ddf30f7fSAnirudh Venkataramanan * and it needs to be read by the firmware
4227ddf30f7fSAnirudh Venkataramanan */
4228ddf30f7fSAnirudh Venkataramanan desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4229ddf30f7fSAnirudh Venkataramanan
423066486d89SBruce Allan for (i = 0, item = qg_list; i < num_qgrps; i++) {
423166486d89SBruce Allan u16 item_size = struct_size(item, q_id, item->num_qs);
4232cdedef59SAnirudh Venkataramanan
4233cdedef59SAnirudh Venkataramanan /* If the num of queues is even, add 2 bytes of padding */
423466486d89SBruce Allan if ((item->num_qs % 2) == 0)
423566486d89SBruce Allan item_size += 2;
423666486d89SBruce Allan
423766486d89SBruce Allan sz += item_size;
423866486d89SBruce Allan
423966486d89SBruce Allan item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size);
4240cdedef59SAnirudh Venkataramanan }
4241cdedef59SAnirudh Venkataramanan
4242cdedef59SAnirudh Venkataramanan if (buf_size != sz)
4243d54699e2STony Nguyen return -EINVAL;
4244cdedef59SAnirudh Venkataramanan
4245ddf30f7fSAnirudh Venkataramanan do_aq:
42466e9650d5SVictor Raj status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
42476e9650d5SVictor Raj if (status) {
42486e9650d5SVictor Raj if (!qg_list)
42496e9650d5SVictor Raj ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
42506e9650d5SVictor Raj vmvf_num, hw->adminq.sq_last_status);
42516e9650d5SVictor Raj else
42522f2da36eSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
42536e9650d5SVictor Raj le16_to_cpu(qg_list[0].q_id[0]),
42546e9650d5SVictor Raj hw->adminq.sq_last_status);
42556e9650d5SVictor Raj }
42566e9650d5SVictor Raj return status;
4257cdedef59SAnirudh Venkataramanan }
4258cdedef59SAnirudh Venkataramanan
4259348048e7SDave Ertman /**
426023ccae5cSDave Ertman * ice_aq_cfg_lan_txq
426123ccae5cSDave Ertman * @hw: pointer to the hardware structure
426223ccae5cSDave Ertman * @buf: buffer for command
426323ccae5cSDave Ertman * @buf_size: size of buffer in bytes
426423ccae5cSDave Ertman * @num_qs: number of queues being configured
426523ccae5cSDave Ertman * @oldport: origination lport
426623ccae5cSDave Ertman * @newport: destination lport
426723ccae5cSDave Ertman * @cd: pointer to command details structure or NULL
426823ccae5cSDave Ertman *
426923ccae5cSDave Ertman * Move/Configure LAN Tx queue (0x0C32)
427023ccae5cSDave Ertman *
427123ccae5cSDave Ertman * There is a better AQ command to use for moving nodes, so only coding
427223ccae5cSDave Ertman * this one for configuring the node.
427323ccae5cSDave Ertman */
427423ccae5cSDave Ertman int
ice_aq_cfg_lan_txq(struct ice_hw * hw,struct ice_aqc_cfg_txqs_buf * buf,u16 buf_size,u16 num_qs,u8 oldport,u8 newport,struct ice_sq_cd * cd)427523ccae5cSDave Ertman ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf,
427623ccae5cSDave Ertman u16 buf_size, u16 num_qs, u8 oldport, u8 newport,
427723ccae5cSDave Ertman struct ice_sq_cd *cd)
427823ccae5cSDave Ertman {
427923ccae5cSDave Ertman struct ice_aqc_cfg_txqs *cmd;
428023ccae5cSDave Ertman struct ice_aq_desc desc;
428123ccae5cSDave Ertman int status;
428223ccae5cSDave Ertman
428323ccae5cSDave Ertman cmd = &desc.params.cfg_txqs;
428423ccae5cSDave Ertman ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs);
428523ccae5cSDave Ertman desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
428623ccae5cSDave Ertman
428723ccae5cSDave Ertman if (!buf)
428823ccae5cSDave Ertman return -EINVAL;
428923ccae5cSDave Ertman
429023ccae5cSDave Ertman cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG;
429123ccae5cSDave Ertman cmd->num_qs = num_qs;
429223ccae5cSDave Ertman cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M);
429323ccae5cSDave Ertman cmd->port_num_chng |= (newport << ICE_AQC_Q_CFG_DST_PRT_S) &
429423ccae5cSDave Ertman ICE_AQC_Q_CFG_DST_PRT_M;
429523ccae5cSDave Ertman cmd->time_out = (5 << ICE_AQC_Q_CFG_TIMEOUT_S) &
429623ccae5cSDave Ertman ICE_AQC_Q_CFG_TIMEOUT_M;
429723ccae5cSDave Ertman cmd->blocked_cgds = 0;
429823ccae5cSDave Ertman
429923ccae5cSDave Ertman status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
430023ccae5cSDave Ertman if (status)
430123ccae5cSDave Ertman ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n",
430223ccae5cSDave Ertman hw->adminq.sq_last_status);
430323ccae5cSDave Ertman return status;
430423ccae5cSDave Ertman }
430523ccae5cSDave Ertman
430623ccae5cSDave Ertman /**
4307348048e7SDave Ertman * ice_aq_add_rdma_qsets
4308348048e7SDave Ertman * @hw: pointer to the hardware structure
4309348048e7SDave Ertman * @num_qset_grps: Number of RDMA Qset groups
4310348048e7SDave Ertman * @qset_list: list of Qset groups to be added
4311348048e7SDave Ertman * @buf_size: size of buffer for indirect command
4312348048e7SDave Ertman * @cd: pointer to command details structure or NULL
4313348048e7SDave Ertman *
4314348048e7SDave Ertman * Add Tx RDMA Qsets (0x0C33)
4315348048e7SDave Ertman */
4316348048e7SDave Ertman static int
ice_aq_add_rdma_qsets(struct ice_hw * hw,u8 num_qset_grps,struct ice_aqc_add_rdma_qset_data * qset_list,u16 buf_size,struct ice_sq_cd * cd)4317348048e7SDave Ertman ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps,
4318348048e7SDave Ertman struct ice_aqc_add_rdma_qset_data *qset_list,
4319348048e7SDave Ertman u16 buf_size, struct ice_sq_cd *cd)
4320348048e7SDave Ertman {
4321348048e7SDave Ertman struct ice_aqc_add_rdma_qset_data *list;
4322348048e7SDave Ertman struct ice_aqc_add_rdma_qset *cmd;
4323348048e7SDave Ertman struct ice_aq_desc desc;
4324348048e7SDave Ertman u16 i, sum_size = 0;
4325348048e7SDave Ertman
4326348048e7SDave Ertman cmd = &desc.params.add_rdma_qset;
4327348048e7SDave Ertman
4328348048e7SDave Ertman ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset);
4329348048e7SDave Ertman
4330348048e7SDave Ertman if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS)
4331348048e7SDave Ertman return -EINVAL;
4332348048e7SDave Ertman
4333348048e7SDave Ertman for (i = 0, list = qset_list; i < num_qset_grps; i++) {
4334348048e7SDave Ertman u16 num_qsets = le16_to_cpu(list->num_qsets);
4335348048e7SDave Ertman
4336348048e7SDave Ertman sum_size += struct_size(list, rdma_qsets, num_qsets);
4337348048e7SDave Ertman list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets +
4338348048e7SDave Ertman num_qsets);
4339348048e7SDave Ertman }
4340348048e7SDave Ertman
4341348048e7SDave Ertman if (buf_size != sum_size)
4342348048e7SDave Ertman return -EINVAL;
4343348048e7SDave Ertman
4344348048e7SDave Ertman desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4345348048e7SDave Ertman
4346348048e7SDave Ertman cmd->num_qset_grps = num_qset_grps;
4347348048e7SDave Ertman
4348d54699e2STony Nguyen return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd);
4349348048e7SDave Ertman }
4350348048e7SDave Ertman
4351cdedef59SAnirudh Venkataramanan /* End of FW Admin Queue command wrappers */
4352cdedef59SAnirudh Venkataramanan
4353cdedef59SAnirudh Venkataramanan /**
4354cdedef59SAnirudh Venkataramanan * ice_write_byte - write a byte to a packed context structure
4355cdedef59SAnirudh Venkataramanan * @src_ctx: the context structure to read from
4356cdedef59SAnirudh Venkataramanan * @dest_ctx: the context to be written to
4357cdedef59SAnirudh Venkataramanan * @ce_info: a description of the struct to be filled
4358cdedef59SAnirudh Venkataramanan */
4359c8b7abddSBruce Allan static void
ice_write_byte(u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)4360c8b7abddSBruce Allan ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4361cdedef59SAnirudh Venkataramanan {
4362cdedef59SAnirudh Venkataramanan u8 src_byte, dest_byte, mask;
4363cdedef59SAnirudh Venkataramanan u8 *from, *dest;
4364cdedef59SAnirudh Venkataramanan u16 shift_width;
4365cdedef59SAnirudh Venkataramanan
4366cdedef59SAnirudh Venkataramanan /* copy from the next struct field */
4367cdedef59SAnirudh Venkataramanan from = src_ctx + ce_info->offset;
4368cdedef59SAnirudh Venkataramanan
4369cdedef59SAnirudh Venkataramanan /* prepare the bits and mask */
4370cdedef59SAnirudh Venkataramanan shift_width = ce_info->lsb % 8;
4371cdedef59SAnirudh Venkataramanan mask = (u8)(BIT(ce_info->width) - 1);
4372cdedef59SAnirudh Venkataramanan
4373cdedef59SAnirudh Venkataramanan src_byte = *from;
4374cdedef59SAnirudh Venkataramanan src_byte &= mask;
4375cdedef59SAnirudh Venkataramanan
4376cdedef59SAnirudh Venkataramanan /* shift to correct alignment */
4377cdedef59SAnirudh Venkataramanan mask <<= shift_width;
4378cdedef59SAnirudh Venkataramanan src_byte <<= shift_width;
4379cdedef59SAnirudh Venkataramanan
4380cdedef59SAnirudh Venkataramanan /* get the current bits from the target bit string */
4381cdedef59SAnirudh Venkataramanan dest = dest_ctx + (ce_info->lsb / 8);
4382cdedef59SAnirudh Venkataramanan
4383cdedef59SAnirudh Venkataramanan memcpy(&dest_byte, dest, sizeof(dest_byte));
4384cdedef59SAnirudh Venkataramanan
4385cdedef59SAnirudh Venkataramanan dest_byte &= ~mask; /* get the bits not changing */
4386cdedef59SAnirudh Venkataramanan dest_byte |= src_byte; /* add in the new bits */
4387cdedef59SAnirudh Venkataramanan
4388cdedef59SAnirudh Venkataramanan /* put it all back */
4389cdedef59SAnirudh Venkataramanan memcpy(dest, &dest_byte, sizeof(dest_byte));
4390cdedef59SAnirudh Venkataramanan }
4391cdedef59SAnirudh Venkataramanan
4392cdedef59SAnirudh Venkataramanan /**
4393cdedef59SAnirudh Venkataramanan * ice_write_word - write a word to a packed context structure
4394cdedef59SAnirudh Venkataramanan * @src_ctx: the context structure to read from
4395cdedef59SAnirudh Venkataramanan * @dest_ctx: the context to be written to
4396cdedef59SAnirudh Venkataramanan * @ce_info: a description of the struct to be filled
4397cdedef59SAnirudh Venkataramanan */
4398c8b7abddSBruce Allan static void
ice_write_word(u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)4399c8b7abddSBruce Allan ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4400cdedef59SAnirudh Venkataramanan {
4401cdedef59SAnirudh Venkataramanan u16 src_word, mask;
4402cdedef59SAnirudh Venkataramanan __le16 dest_word;
4403cdedef59SAnirudh Venkataramanan u8 *from, *dest;
4404cdedef59SAnirudh Venkataramanan u16 shift_width;
4405cdedef59SAnirudh Venkataramanan
4406cdedef59SAnirudh Venkataramanan /* copy from the next struct field */
4407cdedef59SAnirudh Venkataramanan from = src_ctx + ce_info->offset;
4408cdedef59SAnirudh Venkataramanan
4409cdedef59SAnirudh Venkataramanan /* prepare the bits and mask */
4410cdedef59SAnirudh Venkataramanan shift_width = ce_info->lsb % 8;
4411cdedef59SAnirudh Venkataramanan mask = BIT(ce_info->width) - 1;
4412cdedef59SAnirudh Venkataramanan
4413cdedef59SAnirudh Venkataramanan /* don't swizzle the bits until after the mask because the mask bits
4414cdedef59SAnirudh Venkataramanan * will be in a different bit position on big endian machines
4415cdedef59SAnirudh Venkataramanan */
4416cdedef59SAnirudh Venkataramanan src_word = *(u16 *)from;
4417cdedef59SAnirudh Venkataramanan src_word &= mask;
4418cdedef59SAnirudh Venkataramanan
4419cdedef59SAnirudh Venkataramanan /* shift to correct alignment */
4420cdedef59SAnirudh Venkataramanan mask <<= shift_width;
4421cdedef59SAnirudh Venkataramanan src_word <<= shift_width;
4422cdedef59SAnirudh Venkataramanan
4423cdedef59SAnirudh Venkataramanan /* get the current bits from the target bit string */
4424cdedef59SAnirudh Venkataramanan dest = dest_ctx + (ce_info->lsb / 8);
4425cdedef59SAnirudh Venkataramanan
4426cdedef59SAnirudh Venkataramanan memcpy(&dest_word, dest, sizeof(dest_word));
4427cdedef59SAnirudh Venkataramanan
4428cdedef59SAnirudh Venkataramanan dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */
4429cdedef59SAnirudh Venkataramanan dest_word |= cpu_to_le16(src_word); /* add in the new bits */
4430cdedef59SAnirudh Venkataramanan
4431cdedef59SAnirudh Venkataramanan /* put it all back */
4432cdedef59SAnirudh Venkataramanan memcpy(dest, &dest_word, sizeof(dest_word));
4433cdedef59SAnirudh Venkataramanan }
4434cdedef59SAnirudh Venkataramanan
4435cdedef59SAnirudh Venkataramanan /**
4436cdedef59SAnirudh Venkataramanan * ice_write_dword - write a dword to a packed context structure
4437cdedef59SAnirudh Venkataramanan * @src_ctx: the context structure to read from
4438cdedef59SAnirudh Venkataramanan * @dest_ctx: the context to be written to
4439cdedef59SAnirudh Venkataramanan * @ce_info: a description of the struct to be filled
4440cdedef59SAnirudh Venkataramanan */
4441c8b7abddSBruce Allan static void
ice_write_dword(u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)4442c8b7abddSBruce Allan ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4443cdedef59SAnirudh Venkataramanan {
4444cdedef59SAnirudh Venkataramanan u32 src_dword, mask;
4445cdedef59SAnirudh Venkataramanan __le32 dest_dword;
4446cdedef59SAnirudh Venkataramanan u8 *from, *dest;
4447cdedef59SAnirudh Venkataramanan u16 shift_width;
4448cdedef59SAnirudh Venkataramanan
4449cdedef59SAnirudh Venkataramanan /* copy from the next struct field */
4450cdedef59SAnirudh Venkataramanan from = src_ctx + ce_info->offset;
4451cdedef59SAnirudh Venkataramanan
4452cdedef59SAnirudh Venkataramanan /* prepare the bits and mask */
4453cdedef59SAnirudh Venkataramanan shift_width = ce_info->lsb % 8;
4454cdedef59SAnirudh Venkataramanan
4455cdedef59SAnirudh Venkataramanan /* if the field width is exactly 32 on an x86 machine, then the shift
4456cdedef59SAnirudh Venkataramanan * operation will not work because the SHL instructions count is masked
4457cdedef59SAnirudh Venkataramanan * to 5 bits so the shift will do nothing
4458cdedef59SAnirudh Venkataramanan */
4459cdedef59SAnirudh Venkataramanan if (ce_info->width < 32)
4460cdedef59SAnirudh Venkataramanan mask = BIT(ce_info->width) - 1;
4461cdedef59SAnirudh Venkataramanan else
4462cdedef59SAnirudh Venkataramanan mask = (u32)~0;
4463cdedef59SAnirudh Venkataramanan
4464cdedef59SAnirudh Venkataramanan /* don't swizzle the bits until after the mask because the mask bits
4465cdedef59SAnirudh Venkataramanan * will be in a different bit position on big endian machines
4466cdedef59SAnirudh Venkataramanan */
4467cdedef59SAnirudh Venkataramanan src_dword = *(u32 *)from;
4468cdedef59SAnirudh Venkataramanan src_dword &= mask;
4469cdedef59SAnirudh Venkataramanan
4470cdedef59SAnirudh Venkataramanan /* shift to correct alignment */
4471cdedef59SAnirudh Venkataramanan mask <<= shift_width;
4472cdedef59SAnirudh Venkataramanan src_dword <<= shift_width;
4473cdedef59SAnirudh Venkataramanan
4474cdedef59SAnirudh Venkataramanan /* get the current bits from the target bit string */
4475cdedef59SAnirudh Venkataramanan dest = dest_ctx + (ce_info->lsb / 8);
4476cdedef59SAnirudh Venkataramanan
4477cdedef59SAnirudh Venkataramanan memcpy(&dest_dword, dest, sizeof(dest_dword));
4478cdedef59SAnirudh Venkataramanan
4479cdedef59SAnirudh Venkataramanan dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */
4480cdedef59SAnirudh Venkataramanan dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */
4481cdedef59SAnirudh Venkataramanan
4482cdedef59SAnirudh Venkataramanan /* put it all back */
4483cdedef59SAnirudh Venkataramanan memcpy(dest, &dest_dword, sizeof(dest_dword));
4484cdedef59SAnirudh Venkataramanan }
4485cdedef59SAnirudh Venkataramanan
4486cdedef59SAnirudh Venkataramanan /**
4487cdedef59SAnirudh Venkataramanan * ice_write_qword - write a qword to a packed context structure
4488cdedef59SAnirudh Venkataramanan * @src_ctx: the context structure to read from
4489cdedef59SAnirudh Venkataramanan * @dest_ctx: the context to be written to
4490cdedef59SAnirudh Venkataramanan * @ce_info: a description of the struct to be filled
4491cdedef59SAnirudh Venkataramanan */
4492c8b7abddSBruce Allan static void
ice_write_qword(u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)4493c8b7abddSBruce Allan ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
4494cdedef59SAnirudh Venkataramanan {
4495cdedef59SAnirudh Venkataramanan u64 src_qword, mask;
4496cdedef59SAnirudh Venkataramanan __le64 dest_qword;
4497cdedef59SAnirudh Venkataramanan u8 *from, *dest;
4498cdedef59SAnirudh Venkataramanan u16 shift_width;
4499cdedef59SAnirudh Venkataramanan
4500cdedef59SAnirudh Venkataramanan /* copy from the next struct field */
4501cdedef59SAnirudh Venkataramanan from = src_ctx + ce_info->offset;
4502cdedef59SAnirudh Venkataramanan
4503cdedef59SAnirudh Venkataramanan /* prepare the bits and mask */
4504cdedef59SAnirudh Venkataramanan shift_width = ce_info->lsb % 8;
4505cdedef59SAnirudh Venkataramanan
4506cdedef59SAnirudh Venkataramanan /* if the field width is exactly 64 on an x86 machine, then the shift
4507cdedef59SAnirudh Venkataramanan * operation will not work because the SHL instructions count is masked
4508cdedef59SAnirudh Venkataramanan * to 6 bits so the shift will do nothing
4509cdedef59SAnirudh Venkataramanan */
4510cdedef59SAnirudh Venkataramanan if (ce_info->width < 64)
4511cdedef59SAnirudh Venkataramanan mask = BIT_ULL(ce_info->width) - 1;
4512cdedef59SAnirudh Venkataramanan else
4513cdedef59SAnirudh Venkataramanan mask = (u64)~0;
4514cdedef59SAnirudh Venkataramanan
4515cdedef59SAnirudh Venkataramanan /* don't swizzle the bits until after the mask because the mask bits
4516cdedef59SAnirudh Venkataramanan * will be in a different bit position on big endian machines
4517cdedef59SAnirudh Venkataramanan */
4518cdedef59SAnirudh Venkataramanan src_qword = *(u64 *)from;
4519cdedef59SAnirudh Venkataramanan src_qword &= mask;
4520cdedef59SAnirudh Venkataramanan
4521cdedef59SAnirudh Venkataramanan /* shift to correct alignment */
4522cdedef59SAnirudh Venkataramanan mask <<= shift_width;
4523cdedef59SAnirudh Venkataramanan src_qword <<= shift_width;
4524cdedef59SAnirudh Venkataramanan
4525cdedef59SAnirudh Venkataramanan /* get the current bits from the target bit string */
4526cdedef59SAnirudh Venkataramanan dest = dest_ctx + (ce_info->lsb / 8);
4527cdedef59SAnirudh Venkataramanan
4528cdedef59SAnirudh Venkataramanan memcpy(&dest_qword, dest, sizeof(dest_qword));
4529cdedef59SAnirudh Venkataramanan
4530cdedef59SAnirudh Venkataramanan dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */
4531cdedef59SAnirudh Venkataramanan dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */
4532cdedef59SAnirudh Venkataramanan
4533cdedef59SAnirudh Venkataramanan /* put it all back */
4534cdedef59SAnirudh Venkataramanan memcpy(dest, &dest_qword, sizeof(dest_qword));
4535cdedef59SAnirudh Venkataramanan }
4536cdedef59SAnirudh Venkataramanan
4537cdedef59SAnirudh Venkataramanan /**
4538cdedef59SAnirudh Venkataramanan * ice_set_ctx - set context bits in packed structure
45397e34786aSBruce Allan * @hw: pointer to the hardware structure
4540cdedef59SAnirudh Venkataramanan * @src_ctx: pointer to a generic non-packed context structure
4541cdedef59SAnirudh Venkataramanan * @dest_ctx: pointer to memory for the packed structure
4542cdedef59SAnirudh Venkataramanan * @ce_info: a description of the structure to be transformed
4543cdedef59SAnirudh Venkataramanan */
45445e24d598STony Nguyen int
ice_set_ctx(struct ice_hw * hw,u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)45457e34786aSBruce Allan ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
45467e34786aSBruce Allan const struct ice_ctx_ele *ce_info)
4547cdedef59SAnirudh Venkataramanan {
4548cdedef59SAnirudh Venkataramanan int f;
4549cdedef59SAnirudh Venkataramanan
4550cdedef59SAnirudh Venkataramanan for (f = 0; ce_info[f].width; f++) {
4551cdedef59SAnirudh Venkataramanan /* We have to deal with each element of the FW response
4552cdedef59SAnirudh Venkataramanan * using the correct size so that we are correct regardless
4553cdedef59SAnirudh Venkataramanan * of the endianness of the machine.
4554cdedef59SAnirudh Venkataramanan */
45557e34786aSBruce Allan if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
45569228d8b2SJacob Keller ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
45577e34786aSBruce Allan f, ce_info[f].width, ce_info[f].size_of);
45587e34786aSBruce Allan continue;
45597e34786aSBruce Allan }
4560cdedef59SAnirudh Venkataramanan switch (ce_info[f].size_of) {
4561cdedef59SAnirudh Venkataramanan case sizeof(u8):
4562cdedef59SAnirudh Venkataramanan ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
4563cdedef59SAnirudh Venkataramanan break;
4564cdedef59SAnirudh Venkataramanan case sizeof(u16):
4565cdedef59SAnirudh Venkataramanan ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
4566cdedef59SAnirudh Venkataramanan break;
4567cdedef59SAnirudh Venkataramanan case sizeof(u32):
4568cdedef59SAnirudh Venkataramanan ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
4569cdedef59SAnirudh Venkataramanan break;
4570cdedef59SAnirudh Venkataramanan case sizeof(u64):
4571cdedef59SAnirudh Venkataramanan ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
4572cdedef59SAnirudh Venkataramanan break;
4573cdedef59SAnirudh Venkataramanan default:
4574d54699e2STony Nguyen return -EINVAL;
4575cdedef59SAnirudh Venkataramanan }
4576cdedef59SAnirudh Venkataramanan }
4577cdedef59SAnirudh Venkataramanan
4578cdedef59SAnirudh Venkataramanan return 0;
4579cdedef59SAnirudh Venkataramanan }
4580cdedef59SAnirudh Venkataramanan
4581cdedef59SAnirudh Venkataramanan /**
4582bb87ee0eSAnirudh Venkataramanan * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
4583bb87ee0eSAnirudh Venkataramanan * @hw: pointer to the HW struct
4584bb87ee0eSAnirudh Venkataramanan * @vsi_handle: software VSI handle
4585bb87ee0eSAnirudh Venkataramanan * @tc: TC number
4586bb87ee0eSAnirudh Venkataramanan * @q_handle: software queue handle
4587bb87ee0eSAnirudh Venkataramanan */
45881ddef455SUsha Ketineni struct ice_q_ctx *
ice_get_lan_q_ctx(struct ice_hw * hw,u16 vsi_handle,u8 tc,u16 q_handle)4589bb87ee0eSAnirudh Venkataramanan ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
4590bb87ee0eSAnirudh Venkataramanan {
4591bb87ee0eSAnirudh Venkataramanan struct ice_vsi_ctx *vsi;
4592bb87ee0eSAnirudh Venkataramanan struct ice_q_ctx *q_ctx;
4593bb87ee0eSAnirudh Venkataramanan
4594bb87ee0eSAnirudh Venkataramanan vsi = ice_get_vsi_ctx(hw, vsi_handle);
4595bb87ee0eSAnirudh Venkataramanan if (!vsi)
4596bb87ee0eSAnirudh Venkataramanan return NULL;
4597bb87ee0eSAnirudh Venkataramanan if (q_handle >= vsi->num_lan_q_entries[tc])
4598bb87ee0eSAnirudh Venkataramanan return NULL;
4599bb87ee0eSAnirudh Venkataramanan if (!vsi->lan_q_ctx[tc])
4600bb87ee0eSAnirudh Venkataramanan return NULL;
4601bb87ee0eSAnirudh Venkataramanan q_ctx = vsi->lan_q_ctx[tc];
4602bb87ee0eSAnirudh Venkataramanan return &q_ctx[q_handle];
4603bb87ee0eSAnirudh Venkataramanan }
4604bb87ee0eSAnirudh Venkataramanan
4605bb87ee0eSAnirudh Venkataramanan /**
4606cdedef59SAnirudh Venkataramanan * ice_ena_vsi_txq
4607cdedef59SAnirudh Venkataramanan * @pi: port information structure
46084fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle
4609f9867df6SAnirudh Venkataramanan * @tc: TC number
4610bb87ee0eSAnirudh Venkataramanan * @q_handle: software queue handle
4611cdedef59SAnirudh Venkataramanan * @num_qgrps: Number of added queue groups
4612cdedef59SAnirudh Venkataramanan * @buf: list of queue groups to be added
4613cdedef59SAnirudh Venkataramanan * @buf_size: size of buffer for indirect command
4614cdedef59SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
4615cdedef59SAnirudh Venkataramanan *
4616f9867df6SAnirudh Venkataramanan * This function adds one LAN queue
4617cdedef59SAnirudh Venkataramanan */
46185e24d598STony Nguyen int
ice_ena_vsi_txq(struct ice_port_info * pi,u16 vsi_handle,u8 tc,u16 q_handle,u8 num_qgrps,struct ice_aqc_add_tx_qgrp * buf,u16 buf_size,struct ice_sq_cd * cd)4619bb87ee0eSAnirudh Venkataramanan ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
4620bb87ee0eSAnirudh Venkataramanan u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
4621cdedef59SAnirudh Venkataramanan struct ice_sq_cd *cd)
4622cdedef59SAnirudh Venkataramanan {
4623cdedef59SAnirudh Venkataramanan struct ice_aqc_txsched_elem_data node = { 0 };
4624cdedef59SAnirudh Venkataramanan struct ice_sched_node *parent;
4625bb87ee0eSAnirudh Venkataramanan struct ice_q_ctx *q_ctx;
4626cdedef59SAnirudh Venkataramanan struct ice_hw *hw;
46275518ac2aSTony Nguyen int status;
4628cdedef59SAnirudh Venkataramanan
4629cdedef59SAnirudh Venkataramanan if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4630d54699e2STony Nguyen return -EIO;
4631cdedef59SAnirudh Venkataramanan
4632cdedef59SAnirudh Venkataramanan if (num_qgrps > 1 || buf->num_txqs > 1)
4633d54699e2STony Nguyen return -ENOSPC;
4634cdedef59SAnirudh Venkataramanan
4635cdedef59SAnirudh Venkataramanan hw = pi->hw;
4636cdedef59SAnirudh Venkataramanan
46374fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle))
4638d54699e2STony Nguyen return -EINVAL;
46394fb33f31SAnirudh Venkataramanan
4640cdedef59SAnirudh Venkataramanan mutex_lock(&pi->sched_lock);
4641cdedef59SAnirudh Venkataramanan
4642bb87ee0eSAnirudh Venkataramanan q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
4643bb87ee0eSAnirudh Venkataramanan if (!q_ctx) {
4644bb87ee0eSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
4645bb87ee0eSAnirudh Venkataramanan q_handle);
4646d54699e2STony Nguyen status = -EINVAL;
4647bb87ee0eSAnirudh Venkataramanan goto ena_txq_exit;
4648bb87ee0eSAnirudh Venkataramanan }
4649bb87ee0eSAnirudh Venkataramanan
4650cdedef59SAnirudh Venkataramanan /* find a parent node */
46514fb33f31SAnirudh Venkataramanan parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4652cdedef59SAnirudh Venkataramanan ICE_SCHED_NODE_OWNER_LAN);
4653cdedef59SAnirudh Venkataramanan if (!parent) {
4654d54699e2STony Nguyen status = -EINVAL;
4655cdedef59SAnirudh Venkataramanan goto ena_txq_exit;
4656cdedef59SAnirudh Venkataramanan }
46574fb33f31SAnirudh Venkataramanan
4658cdedef59SAnirudh Venkataramanan buf->parent_teid = parent->info.node_teid;
4659cdedef59SAnirudh Venkataramanan node.parent_teid = parent->info.node_teid;
4660cdedef59SAnirudh Venkataramanan /* Mark that the values in the "generic" section as valid. The default
4661cdedef59SAnirudh Venkataramanan * value in the "generic" section is zero. This means that :
4662cdedef59SAnirudh Venkataramanan * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4663cdedef59SAnirudh Venkataramanan * - 0 priority among siblings, indicated by Bit 1-3.
4664cdedef59SAnirudh Venkataramanan * - WFQ, indicated by Bit 4.
4665cdedef59SAnirudh Venkataramanan * - 0 Adjustment value is used in PSM credit update flow, indicated by
4666cdedef59SAnirudh Venkataramanan * Bit 5-6.
4667cdedef59SAnirudh Venkataramanan * - Bit 7 is reserved.
4668cdedef59SAnirudh Venkataramanan * Without setting the generic section as valid in valid_sections, the
4669f9867df6SAnirudh Venkataramanan * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4670cdedef59SAnirudh Venkataramanan */
4671984824a2STarun Singh buf->txqs[0].info.valid_sections =
4672984824a2STarun Singh ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4673984824a2STarun Singh ICE_AQC_ELEM_VALID_EIR;
4674984824a2STarun Singh buf->txqs[0].info.generic = 0;
4675984824a2STarun Singh buf->txqs[0].info.cir_bw.bw_profile_idx =
4676984824a2STarun Singh cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4677984824a2STarun Singh buf->txqs[0].info.cir_bw.bw_alloc =
4678984824a2STarun Singh cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4679984824a2STarun Singh buf->txqs[0].info.eir_bw.bw_profile_idx =
4680984824a2STarun Singh cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4681984824a2STarun Singh buf->txqs[0].info.eir_bw.bw_alloc =
4682984824a2STarun Singh cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4683cdedef59SAnirudh Venkataramanan
4684f9867df6SAnirudh Venkataramanan /* add the LAN queue */
4685cdedef59SAnirudh Venkataramanan status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
46866e9650d5SVictor Raj if (status) {
4687bb87ee0eSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
46886e9650d5SVictor Raj le16_to_cpu(buf->txqs[0].txq_id),
46896e9650d5SVictor Raj hw->adminq.sq_last_status);
4690cdedef59SAnirudh Venkataramanan goto ena_txq_exit;
46916e9650d5SVictor Raj }
4692cdedef59SAnirudh Venkataramanan
4693cdedef59SAnirudh Venkataramanan node.node_teid = buf->txqs[0].q_teid;
4694cdedef59SAnirudh Venkataramanan node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4695bb87ee0eSAnirudh Venkataramanan q_ctx->q_handle = q_handle;
46961ddef455SUsha Ketineni q_ctx->q_teid = le32_to_cpu(node.node_teid);
4697cdedef59SAnirudh Venkataramanan
46981ddef455SUsha Ketineni /* add a leaf node into scheduler tree queue layer */
4699bdf96d96SMichal Wilczynski status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL);
47001ddef455SUsha Ketineni if (!status)
47011ddef455SUsha Ketineni status = ice_sched_replay_q_bw(pi, q_ctx);
4702cdedef59SAnirudh Venkataramanan
4703cdedef59SAnirudh Venkataramanan ena_txq_exit:
4704cdedef59SAnirudh Venkataramanan mutex_unlock(&pi->sched_lock);
4705cdedef59SAnirudh Venkataramanan return status;
4706cdedef59SAnirudh Venkataramanan }
4707cdedef59SAnirudh Venkataramanan
4708cdedef59SAnirudh Venkataramanan /**
4709cdedef59SAnirudh Venkataramanan * ice_dis_vsi_txq
4710cdedef59SAnirudh Venkataramanan * @pi: port information structure
4711bb87ee0eSAnirudh Venkataramanan * @vsi_handle: software VSI handle
4712bb87ee0eSAnirudh Venkataramanan * @tc: TC number
4713cdedef59SAnirudh Venkataramanan * @num_queues: number of queues
4714bb87ee0eSAnirudh Venkataramanan * @q_handles: pointer to software queue handle array
4715cdedef59SAnirudh Venkataramanan * @q_ids: pointer to the q_id array
4716cdedef59SAnirudh Venkataramanan * @q_teids: pointer to queue node teids
471794c4441bSAnirudh Venkataramanan * @rst_src: if called due to reset, specifies the reset source
4718ddf30f7fSAnirudh Venkataramanan * @vmvf_num: the relative VM or VF number that is undergoing the reset
4719cdedef59SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL
4720cdedef59SAnirudh Venkataramanan *
4721cdedef59SAnirudh Venkataramanan * This function removes queues and their corresponding nodes in SW DB
4722cdedef59SAnirudh Venkataramanan */
47235e24d598STony Nguyen int
ice_dis_vsi_txq(struct ice_port_info * pi,u16 vsi_handle,u8 tc,u8 num_queues,u16 * q_handles,u16 * q_ids,u32 * q_teids,enum ice_disq_rst_src rst_src,u16 vmvf_num,struct ice_sq_cd * cd)4724bb87ee0eSAnirudh Venkataramanan ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4725bb87ee0eSAnirudh Venkataramanan u16 *q_handles, u16 *q_ids, u32 *q_teids,
4726bb87ee0eSAnirudh Venkataramanan enum ice_disq_rst_src rst_src, u16 vmvf_num,
4727ddf30f7fSAnirudh Venkataramanan struct ice_sq_cd *cd)
4728cdedef59SAnirudh Venkataramanan {
472966486d89SBruce Allan struct ice_aqc_dis_txq_item *qg_list;
4730bb87ee0eSAnirudh Venkataramanan struct ice_q_ctx *q_ctx;
47315518ac2aSTony Nguyen int status = -ENOENT;
473266486d89SBruce Allan struct ice_hw *hw;
473366486d89SBruce Allan u16 i, buf_size;
4734cdedef59SAnirudh Venkataramanan
4735cdedef59SAnirudh Venkataramanan if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4736d54699e2STony Nguyen return -EIO;
4737cdedef59SAnirudh Venkataramanan
473866486d89SBruce Allan hw = pi->hw;
473966486d89SBruce Allan
474085796d6eSAkeem G Abodunrin if (!num_queues) {
474185796d6eSAkeem G Abodunrin /* if queue is disabled already yet the disable queue command
474285796d6eSAkeem G Abodunrin * has to be sent to complete the VF reset, then call
474385796d6eSAkeem G Abodunrin * ice_aq_dis_lan_txq without any queue information
474485796d6eSAkeem G Abodunrin */
474585796d6eSAkeem G Abodunrin if (rst_src)
474666486d89SBruce Allan return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src,
474785796d6eSAkeem G Abodunrin vmvf_num, NULL);
4748d54699e2STony Nguyen return -EIO;
474985796d6eSAkeem G Abodunrin }
4750ddf30f7fSAnirudh Venkataramanan
475166486d89SBruce Allan buf_size = struct_size(qg_list, q_id, 1);
475266486d89SBruce Allan qg_list = kzalloc(buf_size, GFP_KERNEL);
475366486d89SBruce Allan if (!qg_list)
4754d54699e2STony Nguyen return -ENOMEM;
475566486d89SBruce Allan
4756cdedef59SAnirudh Venkataramanan mutex_lock(&pi->sched_lock);
4757cdedef59SAnirudh Venkataramanan
4758cdedef59SAnirudh Venkataramanan for (i = 0; i < num_queues; i++) {
4759cdedef59SAnirudh Venkataramanan struct ice_sched_node *node;
4760cdedef59SAnirudh Venkataramanan
4761cdedef59SAnirudh Venkataramanan node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4762cdedef59SAnirudh Venkataramanan if (!node)
4763cdedef59SAnirudh Venkataramanan continue;
476466486d89SBruce Allan q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]);
4765bb87ee0eSAnirudh Venkataramanan if (!q_ctx) {
476666486d89SBruce Allan ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4767bb87ee0eSAnirudh Venkataramanan q_handles[i]);
4768bb87ee0eSAnirudh Venkataramanan continue;
4769bb87ee0eSAnirudh Venkataramanan }
4770bb87ee0eSAnirudh Venkataramanan if (q_ctx->q_handle != q_handles[i]) {
477166486d89SBruce Allan ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4772bb87ee0eSAnirudh Venkataramanan q_ctx->q_handle, q_handles[i]);
4773bb87ee0eSAnirudh Venkataramanan continue;
4774bb87ee0eSAnirudh Venkataramanan }
477566486d89SBruce Allan qg_list->parent_teid = node->info.parent_teid;
477666486d89SBruce Allan qg_list->num_qs = 1;
477766486d89SBruce Allan qg_list->q_id[0] = cpu_to_le16(q_ids[i]);
477866486d89SBruce Allan status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src,
477966486d89SBruce Allan vmvf_num, cd);
4780cdedef59SAnirudh Venkataramanan
4781cdedef59SAnirudh Venkataramanan if (status)
4782cdedef59SAnirudh Venkataramanan break;
4783cdedef59SAnirudh Venkataramanan ice_free_sched_node(pi, node);
4784bb87ee0eSAnirudh Venkataramanan q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4785f3fbda33SJacob Keller q_ctx->q_teid = ICE_INVAL_TEID;
4786cdedef59SAnirudh Venkataramanan }
4787cdedef59SAnirudh Venkataramanan mutex_unlock(&pi->sched_lock);
478866486d89SBruce Allan kfree(qg_list);
4789cdedef59SAnirudh Venkataramanan return status;
4790cdedef59SAnirudh Venkataramanan }
47915513b920SAnirudh Venkataramanan
47925513b920SAnirudh Venkataramanan /**
479394c4441bSAnirudh Venkataramanan * ice_cfg_vsi_qs - configure the new/existing VSI queues
47945513b920SAnirudh Venkataramanan * @pi: port information structure
47954fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle
47965513b920SAnirudh Venkataramanan * @tc_bitmap: TC bitmap
47975513b920SAnirudh Venkataramanan * @maxqs: max queues array per TC
4798f9867df6SAnirudh Venkataramanan * @owner: LAN or RDMA
47995513b920SAnirudh Venkataramanan *
48005513b920SAnirudh Venkataramanan * This function adds/updates the VSI queues per TC.
48015513b920SAnirudh Venkataramanan */
48025e24d598STony Nguyen static int
ice_cfg_vsi_qs(struct ice_port_info * pi,u16 vsi_handle,u8 tc_bitmap,u16 * maxqs,u8 owner)48034fb33f31SAnirudh Venkataramanan ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
48045513b920SAnirudh Venkataramanan u16 *maxqs, u8 owner)
48055513b920SAnirudh Venkataramanan {
48065e24d598STony Nguyen int status = 0;
48075513b920SAnirudh Venkataramanan u8 i;
48085513b920SAnirudh Venkataramanan
48095513b920SAnirudh Venkataramanan if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4810d54699e2STony Nguyen return -EIO;
48115513b920SAnirudh Venkataramanan
48124fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4813d54699e2STony Nguyen return -EINVAL;
48144fb33f31SAnirudh Venkataramanan
48155513b920SAnirudh Venkataramanan mutex_lock(&pi->sched_lock);
48165513b920SAnirudh Venkataramanan
48172bdc97beSBruce Allan ice_for_each_traffic_class(i) {
48185513b920SAnirudh Venkataramanan /* configuration is possible only if TC node is present */
48195513b920SAnirudh Venkataramanan if (!ice_sched_get_tc_node(pi, i))
48205513b920SAnirudh Venkataramanan continue;
48215513b920SAnirudh Venkataramanan
48224fb33f31SAnirudh Venkataramanan status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
48235513b920SAnirudh Venkataramanan ice_is_tc_ena(tc_bitmap, i));
48245513b920SAnirudh Venkataramanan if (status)
48255513b920SAnirudh Venkataramanan break;
48265513b920SAnirudh Venkataramanan }
48275513b920SAnirudh Venkataramanan
48285513b920SAnirudh Venkataramanan mutex_unlock(&pi->sched_lock);
48295513b920SAnirudh Venkataramanan return status;
48305513b920SAnirudh Venkataramanan }
48315513b920SAnirudh Venkataramanan
48325513b920SAnirudh Venkataramanan /**
4833f9867df6SAnirudh Venkataramanan * ice_cfg_vsi_lan - configure VSI LAN queues
48345513b920SAnirudh Venkataramanan * @pi: port information structure
48354fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle
48365513b920SAnirudh Venkataramanan * @tc_bitmap: TC bitmap
4837f9867df6SAnirudh Venkataramanan * @max_lanqs: max LAN queues array per TC
48385513b920SAnirudh Venkataramanan *
4839f9867df6SAnirudh Venkataramanan * This function adds/updates the VSI LAN queues per TC.
48405513b920SAnirudh Venkataramanan */
48415e24d598STony Nguyen int
ice_cfg_vsi_lan(struct ice_port_info * pi,u16 vsi_handle,u8 tc_bitmap,u16 * max_lanqs)48424fb33f31SAnirudh Venkataramanan ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
48435513b920SAnirudh Venkataramanan u16 *max_lanqs)
48445513b920SAnirudh Venkataramanan {
48454fb33f31SAnirudh Venkataramanan return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
48465513b920SAnirudh Venkataramanan ICE_SCHED_NODE_OWNER_LAN);
48475513b920SAnirudh Venkataramanan }
484845d3d428SAnirudh Venkataramanan
484945d3d428SAnirudh Venkataramanan /**
4850348048e7SDave Ertman * ice_cfg_vsi_rdma - configure the VSI RDMA queues
4851348048e7SDave Ertman * @pi: port information structure
4852348048e7SDave Ertman * @vsi_handle: software VSI handle
4853348048e7SDave Ertman * @tc_bitmap: TC bitmap
4854348048e7SDave Ertman * @max_rdmaqs: max RDMA queues array per TC
4855348048e7SDave Ertman *
4856348048e7SDave Ertman * This function adds/updates the VSI RDMA queues per TC.
4857348048e7SDave Ertman */
4858348048e7SDave Ertman int
ice_cfg_vsi_rdma(struct ice_port_info * pi,u16 vsi_handle,u16 tc_bitmap,u16 * max_rdmaqs)4859348048e7SDave Ertman ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
4860348048e7SDave Ertman u16 *max_rdmaqs)
4861348048e7SDave Ertman {
4862d54699e2STony Nguyen return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs,
4863d54699e2STony Nguyen ICE_SCHED_NODE_OWNER_RDMA);
4864348048e7SDave Ertman }
4865348048e7SDave Ertman
4866348048e7SDave Ertman /**
4867348048e7SDave Ertman * ice_ena_vsi_rdma_qset
4868348048e7SDave Ertman * @pi: port information structure
4869348048e7SDave Ertman * @vsi_handle: software VSI handle
4870348048e7SDave Ertman * @tc: TC number
4871348048e7SDave Ertman * @rdma_qset: pointer to RDMA Qset
4872348048e7SDave Ertman * @num_qsets: number of RDMA Qsets
4873348048e7SDave Ertman * @qset_teid: pointer to Qset node TEIDs
4874348048e7SDave Ertman *
4875348048e7SDave Ertman * This function adds RDMA Qset
4876348048e7SDave Ertman */
4877348048e7SDave Ertman int
ice_ena_vsi_rdma_qset(struct ice_port_info * pi,u16 vsi_handle,u8 tc,u16 * rdma_qset,u16 num_qsets,u32 * qset_teid)4878348048e7SDave Ertman ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
4879348048e7SDave Ertman u16 *rdma_qset, u16 num_qsets, u32 *qset_teid)
4880348048e7SDave Ertman {
4881348048e7SDave Ertman struct ice_aqc_txsched_elem_data node = { 0 };
4882348048e7SDave Ertman struct ice_aqc_add_rdma_qset_data *buf;
4883348048e7SDave Ertman struct ice_sched_node *parent;
4884348048e7SDave Ertman struct ice_hw *hw;
4885348048e7SDave Ertman u16 i, buf_size;
4886348048e7SDave Ertman int ret;
4887348048e7SDave Ertman
4888348048e7SDave Ertman if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4889348048e7SDave Ertman return -EIO;
4890348048e7SDave Ertman hw = pi->hw;
4891348048e7SDave Ertman
4892348048e7SDave Ertman if (!ice_is_vsi_valid(hw, vsi_handle))
4893348048e7SDave Ertman return -EINVAL;
4894348048e7SDave Ertman
4895348048e7SDave Ertman buf_size = struct_size(buf, rdma_qsets, num_qsets);
4896348048e7SDave Ertman buf = kzalloc(buf_size, GFP_KERNEL);
4897348048e7SDave Ertman if (!buf)
4898348048e7SDave Ertman return -ENOMEM;
4899348048e7SDave Ertman mutex_lock(&pi->sched_lock);
4900348048e7SDave Ertman
4901348048e7SDave Ertman parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4902348048e7SDave Ertman ICE_SCHED_NODE_OWNER_RDMA);
4903348048e7SDave Ertman if (!parent) {
4904348048e7SDave Ertman ret = -EINVAL;
4905348048e7SDave Ertman goto rdma_error_exit;
4906348048e7SDave Ertman }
4907348048e7SDave Ertman buf->parent_teid = parent->info.node_teid;
4908348048e7SDave Ertman node.parent_teid = parent->info.node_teid;
4909348048e7SDave Ertman
4910348048e7SDave Ertman buf->num_qsets = cpu_to_le16(num_qsets);
4911348048e7SDave Ertman for (i = 0; i < num_qsets; i++) {
4912348048e7SDave Ertman buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]);
4913348048e7SDave Ertman buf->rdma_qsets[i].info.valid_sections =
4914348048e7SDave Ertman ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4915348048e7SDave Ertman ICE_AQC_ELEM_VALID_EIR;
4916348048e7SDave Ertman buf->rdma_qsets[i].info.generic = 0;
4917348048e7SDave Ertman buf->rdma_qsets[i].info.cir_bw.bw_profile_idx =
4918348048e7SDave Ertman cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4919348048e7SDave Ertman buf->rdma_qsets[i].info.cir_bw.bw_alloc =
4920348048e7SDave Ertman cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4921348048e7SDave Ertman buf->rdma_qsets[i].info.eir_bw.bw_profile_idx =
4922348048e7SDave Ertman cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4923348048e7SDave Ertman buf->rdma_qsets[i].info.eir_bw.bw_alloc =
4924348048e7SDave Ertman cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4925348048e7SDave Ertman }
4926348048e7SDave Ertman ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL);
4927348048e7SDave Ertman if (ret) {
4928348048e7SDave Ertman ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n");
4929348048e7SDave Ertman goto rdma_error_exit;
4930348048e7SDave Ertman }
4931348048e7SDave Ertman node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4932348048e7SDave Ertman for (i = 0; i < num_qsets; i++) {
4933348048e7SDave Ertman node.node_teid = buf->rdma_qsets[i].qset_teid;
49342ccc1c1cSTony Nguyen ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1,
4935bdf96d96SMichal Wilczynski &node, NULL);
49362ccc1c1cSTony Nguyen if (ret)
4937348048e7SDave Ertman break;
4938348048e7SDave Ertman qset_teid[i] = le32_to_cpu(node.node_teid);
4939348048e7SDave Ertman }
4940348048e7SDave Ertman rdma_error_exit:
4941348048e7SDave Ertman mutex_unlock(&pi->sched_lock);
4942348048e7SDave Ertman kfree(buf);
4943348048e7SDave Ertman return ret;
4944348048e7SDave Ertman }
4945348048e7SDave Ertman
4946348048e7SDave Ertman /**
4947348048e7SDave Ertman * ice_dis_vsi_rdma_qset - free RDMA resources
4948348048e7SDave Ertman * @pi: port_info struct
4949348048e7SDave Ertman * @count: number of RDMA Qsets to free
4950348048e7SDave Ertman * @qset_teid: TEID of Qset node
4951348048e7SDave Ertman * @q_id: list of queue IDs being disabled
4952348048e7SDave Ertman */
4953348048e7SDave Ertman int
ice_dis_vsi_rdma_qset(struct ice_port_info * pi,u16 count,u32 * qset_teid,u16 * q_id)4954348048e7SDave Ertman ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid,
4955348048e7SDave Ertman u16 *q_id)
4956348048e7SDave Ertman {
4957348048e7SDave Ertman struct ice_aqc_dis_txq_item *qg_list;
4958348048e7SDave Ertman struct ice_hw *hw;
49595518ac2aSTony Nguyen int status = 0;
4960348048e7SDave Ertman u16 qg_size;
4961348048e7SDave Ertman int i;
4962348048e7SDave Ertman
4963348048e7SDave Ertman if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4964348048e7SDave Ertman return -EIO;
4965348048e7SDave Ertman
4966348048e7SDave Ertman hw = pi->hw;
4967348048e7SDave Ertman
4968348048e7SDave Ertman qg_size = struct_size(qg_list, q_id, 1);
4969348048e7SDave Ertman qg_list = kzalloc(qg_size, GFP_KERNEL);
4970348048e7SDave Ertman if (!qg_list)
4971348048e7SDave Ertman return -ENOMEM;
4972348048e7SDave Ertman
4973348048e7SDave Ertman mutex_lock(&pi->sched_lock);
4974348048e7SDave Ertman
4975348048e7SDave Ertman for (i = 0; i < count; i++) {
4976348048e7SDave Ertman struct ice_sched_node *node;
4977348048e7SDave Ertman
4978348048e7SDave Ertman node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]);
4979348048e7SDave Ertman if (!node)
4980348048e7SDave Ertman continue;
4981348048e7SDave Ertman
4982348048e7SDave Ertman qg_list->parent_teid = node->info.parent_teid;
4983348048e7SDave Ertman qg_list->num_qs = 1;
4984348048e7SDave Ertman qg_list->q_id[0] =
4985348048e7SDave Ertman cpu_to_le16(q_id[i] |
4986348048e7SDave Ertman ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET);
4987348048e7SDave Ertman
4988348048e7SDave Ertman status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size,
4989348048e7SDave Ertman ICE_NO_RESET, 0, NULL);
4990348048e7SDave Ertman if (status)
4991348048e7SDave Ertman break;
4992348048e7SDave Ertman
4993348048e7SDave Ertman ice_free_sched_node(pi, node);
4994348048e7SDave Ertman }
4995348048e7SDave Ertman
4996348048e7SDave Ertman mutex_unlock(&pi->sched_lock);
4997348048e7SDave Ertman kfree(qg_list);
4998d54699e2STony Nguyen return status;
4999348048e7SDave Ertman }
5000348048e7SDave Ertman
5001348048e7SDave Ertman /**
5002334cb062SAnirudh Venkataramanan * ice_replay_pre_init - replay pre initialization
5003f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
5004334cb062SAnirudh Venkataramanan *
5005334cb062SAnirudh Venkataramanan * Initializes required config data for VSI, FD, ACL, and RSS before replay.
5006334cb062SAnirudh Venkataramanan */
ice_replay_pre_init(struct ice_hw * hw)50075e24d598STony Nguyen static int ice_replay_pre_init(struct ice_hw *hw)
5008334cb062SAnirudh Venkataramanan {
5009334cb062SAnirudh Venkataramanan struct ice_switch_info *sw = hw->switch_info;
5010334cb062SAnirudh Venkataramanan u8 i;
5011334cb062SAnirudh Venkataramanan
5012334cb062SAnirudh Venkataramanan /* Delete old entries from replay filter list head if there is any */
5013334cb062SAnirudh Venkataramanan ice_rm_all_sw_replay_rule_info(hw);
5014334cb062SAnirudh Venkataramanan /* In start of replay, move entries into replay_rules list, it
5015334cb062SAnirudh Venkataramanan * will allow adding rules entries back to filt_rules list,
5016334cb062SAnirudh Venkataramanan * which is operational list.
5017334cb062SAnirudh Venkataramanan */
5018c36a2b97SVictor Raj for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
5019334cb062SAnirudh Venkataramanan list_replace_init(&sw->recp_list[i].filt_rules,
5020334cb062SAnirudh Venkataramanan &sw->recp_list[i].filt_replay_rules);
5021b126bd6bSKiran Patil ice_sched_replay_agg_vsi_preinit(hw);
5022334cb062SAnirudh Venkataramanan
5023334cb062SAnirudh Venkataramanan return 0;
5024334cb062SAnirudh Venkataramanan }
5025334cb062SAnirudh Venkataramanan
5026334cb062SAnirudh Venkataramanan /**
5027334cb062SAnirudh Venkataramanan * ice_replay_vsi - replay VSI configuration
5028f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
5029334cb062SAnirudh Venkataramanan * @vsi_handle: driver VSI handle
5030334cb062SAnirudh Venkataramanan *
5031334cb062SAnirudh Venkataramanan * Restore all VSI configuration after reset. It is required to call this
5032334cb062SAnirudh Venkataramanan * function with main VSI first.
5033334cb062SAnirudh Venkataramanan */
ice_replay_vsi(struct ice_hw * hw,u16 vsi_handle)50345e24d598STony Nguyen int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
5035334cb062SAnirudh Venkataramanan {
50365e24d598STony Nguyen int status;
5037334cb062SAnirudh Venkataramanan
5038334cb062SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle))
5039d54699e2STony Nguyen return -EINVAL;
5040334cb062SAnirudh Venkataramanan
5041334cb062SAnirudh Venkataramanan /* Replay pre-initialization if there is any */
5042334cb062SAnirudh Venkataramanan if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
5043334cb062SAnirudh Venkataramanan status = ice_replay_pre_init(hw);
5044334cb062SAnirudh Venkataramanan if (status)
5045334cb062SAnirudh Venkataramanan return status;
5046334cb062SAnirudh Venkataramanan }
5047c90ed40cSTony Nguyen /* Replay per VSI all RSS configurations */
5048c90ed40cSTony Nguyen status = ice_replay_rss_cfg(hw, vsi_handle);
5049c90ed40cSTony Nguyen if (status)
5050c90ed40cSTony Nguyen return status;
5051334cb062SAnirudh Venkataramanan /* Replay per VSI all filters */
5052334cb062SAnirudh Venkataramanan status = ice_replay_vsi_all_fltr(hw, vsi_handle);
5053b126bd6bSKiran Patil if (!status)
5054b126bd6bSKiran Patil status = ice_replay_vsi_agg(hw, vsi_handle);
5055334cb062SAnirudh Venkataramanan return status;
5056334cb062SAnirudh Venkataramanan }
5057334cb062SAnirudh Venkataramanan
5058334cb062SAnirudh Venkataramanan /**
5059334cb062SAnirudh Venkataramanan * ice_replay_post - post replay configuration cleanup
5060f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct
5061334cb062SAnirudh Venkataramanan *
5062334cb062SAnirudh Venkataramanan * Post replay cleanup.
5063334cb062SAnirudh Venkataramanan */
ice_replay_post(struct ice_hw * hw)5064334cb062SAnirudh Venkataramanan void ice_replay_post(struct ice_hw *hw)
5065334cb062SAnirudh Venkataramanan {
5066334cb062SAnirudh Venkataramanan /* Delete old entries from replay filter list head */
5067334cb062SAnirudh Venkataramanan ice_rm_all_sw_replay_rule_info(hw);
5068b126bd6bSKiran Patil ice_sched_replay_agg(hw);
5069334cb062SAnirudh Venkataramanan }
5070334cb062SAnirudh Venkataramanan
5071334cb062SAnirudh Venkataramanan /**
507245d3d428SAnirudh Venkataramanan * ice_stat_update40 - read 40 bit stat from the chip and update stat values
507345d3d428SAnirudh Venkataramanan * @hw: ptr to the hardware info
507436517fd3SJacob Keller * @reg: offset of 64 bit HW register to read from
507545d3d428SAnirudh Venkataramanan * @prev_stat_loaded: bool to specify if previous stats are loaded
507645d3d428SAnirudh Venkataramanan * @prev_stat: ptr to previous loaded stat value
507745d3d428SAnirudh Venkataramanan * @cur_stat: ptr to current stat value
507845d3d428SAnirudh Venkataramanan */
5079c8b7abddSBruce Allan void
ice_stat_update40(struct ice_hw * hw,u32 reg,bool prev_stat_loaded,u64 * prev_stat,u64 * cur_stat)508036517fd3SJacob Keller ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
508136517fd3SJacob Keller u64 *prev_stat, u64 *cur_stat)
508245d3d428SAnirudh Venkataramanan {
508336517fd3SJacob Keller u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
508445d3d428SAnirudh Venkataramanan
508545d3d428SAnirudh Venkataramanan /* device stats are not reset at PFR, they likely will not be zeroed
508636517fd3SJacob Keller * when the driver starts. Thus, save the value from the first read
508736517fd3SJacob Keller * without adding to the statistic value so that we report stats which
508836517fd3SJacob Keller * count up from zero.
508945d3d428SAnirudh Venkataramanan */
509036517fd3SJacob Keller if (!prev_stat_loaded) {
509145d3d428SAnirudh Venkataramanan *prev_stat = new_data;
509236517fd3SJacob Keller return;
509336517fd3SJacob Keller }
509436517fd3SJacob Keller
509536517fd3SJacob Keller /* Calculate the difference between the new and old values, and then
509636517fd3SJacob Keller * add it to the software stat value.
509736517fd3SJacob Keller */
509845d3d428SAnirudh Venkataramanan if (new_data >= *prev_stat)
509936517fd3SJacob Keller *cur_stat += new_data - *prev_stat;
510045d3d428SAnirudh Venkataramanan else
510145d3d428SAnirudh Venkataramanan /* to manage the potential roll-over */
510236517fd3SJacob Keller *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
510336517fd3SJacob Keller
510436517fd3SJacob Keller /* Update the previously stored value to prepare for next read */
510536517fd3SJacob Keller *prev_stat = new_data;
510645d3d428SAnirudh Venkataramanan }
510745d3d428SAnirudh Venkataramanan
510845d3d428SAnirudh Venkataramanan /**
510945d3d428SAnirudh Venkataramanan * ice_stat_update32 - read 32 bit stat from the chip and update stat values
511045d3d428SAnirudh Venkataramanan * @hw: ptr to the hardware info
511136517fd3SJacob Keller * @reg: offset of HW register to read from
511245d3d428SAnirudh Venkataramanan * @prev_stat_loaded: bool to specify if previous stats are loaded
511345d3d428SAnirudh Venkataramanan * @prev_stat: ptr to previous loaded stat value
511445d3d428SAnirudh Venkataramanan * @cur_stat: ptr to current stat value
511545d3d428SAnirudh Venkataramanan */
5116c8b7abddSBruce Allan void
ice_stat_update32(struct ice_hw * hw,u32 reg,bool prev_stat_loaded,u64 * prev_stat,u64 * cur_stat)5117c8b7abddSBruce Allan ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
511845d3d428SAnirudh Venkataramanan u64 *prev_stat, u64 *cur_stat)
511945d3d428SAnirudh Venkataramanan {
512045d3d428SAnirudh Venkataramanan u32 new_data;
512145d3d428SAnirudh Venkataramanan
512245d3d428SAnirudh Venkataramanan new_data = rd32(hw, reg);
512345d3d428SAnirudh Venkataramanan
512445d3d428SAnirudh Venkataramanan /* device stats are not reset at PFR, they likely will not be zeroed
512536517fd3SJacob Keller * when the driver starts. Thus, save the value from the first read
512636517fd3SJacob Keller * without adding to the statistic value so that we report stats which
512736517fd3SJacob Keller * count up from zero.
512845d3d428SAnirudh Venkataramanan */
512936517fd3SJacob Keller if (!prev_stat_loaded) {
513045d3d428SAnirudh Venkataramanan *prev_stat = new_data;
513136517fd3SJacob Keller return;
513236517fd3SJacob Keller }
513336517fd3SJacob Keller
513436517fd3SJacob Keller /* Calculate the difference between the new and old values, and then
513536517fd3SJacob Keller * add it to the software stat value.
513636517fd3SJacob Keller */
513745d3d428SAnirudh Venkataramanan if (new_data >= *prev_stat)
513836517fd3SJacob Keller *cur_stat += new_data - *prev_stat;
513945d3d428SAnirudh Venkataramanan else
514045d3d428SAnirudh Venkataramanan /* to manage the potential roll-over */
514136517fd3SJacob Keller *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
514236517fd3SJacob Keller
514336517fd3SJacob Keller /* Update the previously stored value to prepare for next read */
514436517fd3SJacob Keller *prev_stat = new_data;
514545d3d428SAnirudh Venkataramanan }
51467b9ffc76SAnirudh Venkataramanan
51477b9ffc76SAnirudh Venkataramanan /**
51487b9ffc76SAnirudh Venkataramanan * ice_sched_query_elem - query element information from HW
51497b9ffc76SAnirudh Venkataramanan * @hw: pointer to the HW struct
51507b9ffc76SAnirudh Venkataramanan * @node_teid: node TEID to be queried
51517b9ffc76SAnirudh Venkataramanan * @buf: buffer to element information
51527b9ffc76SAnirudh Venkataramanan *
51537b9ffc76SAnirudh Venkataramanan * This function queries HW element information
51547b9ffc76SAnirudh Venkataramanan */
51555e24d598STony Nguyen int
ice_sched_query_elem(struct ice_hw * hw,u32 node_teid,struct ice_aqc_txsched_elem_data * buf)51567b9ffc76SAnirudh Venkataramanan ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
5157b3c38904SBruce Allan struct ice_aqc_txsched_elem_data *buf)
51587b9ffc76SAnirudh Venkataramanan {
51597b9ffc76SAnirudh Venkataramanan u16 buf_size, num_elem_ret = 0;
51605e24d598STony Nguyen int status;
51617b9ffc76SAnirudh Venkataramanan
51627b9ffc76SAnirudh Venkataramanan buf_size = sizeof(*buf);
51637b9ffc76SAnirudh Venkataramanan memset(buf, 0, buf_size);
5164b3c38904SBruce Allan buf->node_teid = cpu_to_le32(node_teid);
51657b9ffc76SAnirudh Venkataramanan status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
51667b9ffc76SAnirudh Venkataramanan NULL);
51677b9ffc76SAnirudh Venkataramanan if (status || num_elem_ret != 1)
51687b9ffc76SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
51697b9ffc76SAnirudh Venkataramanan return status;
51707b9ffc76SAnirudh Venkataramanan }
5171ea78ce4dSPaul Greenwalt
5172ea78ce4dSPaul Greenwalt /**
517343113ff7SKarol Kolacinski * ice_aq_read_i2c
517443113ff7SKarol Kolacinski * @hw: pointer to the hw struct
517543113ff7SKarol Kolacinski * @topo_addr: topology address for a device to communicate with
517643113ff7SKarol Kolacinski * @bus_addr: 7-bit I2C bus address
517743113ff7SKarol Kolacinski * @addr: I2C memory address (I2C offset) with up to 16 bits
517843113ff7SKarol Kolacinski * @params: I2C parameters: bit [7] - Repeated start,
517943113ff7SKarol Kolacinski * bits [6:5] data offset size,
518043113ff7SKarol Kolacinski * bit [4] - I2C address type,
518143113ff7SKarol Kolacinski * bits [3:0] - data size to read (0-16 bytes)
518243113ff7SKarol Kolacinski * @data: pointer to data (0 to 16 bytes) to be read from the I2C device
518343113ff7SKarol Kolacinski * @cd: pointer to command details structure or NULL
518443113ff7SKarol Kolacinski *
518543113ff7SKarol Kolacinski * Read I2C (0x06E2)
518643113ff7SKarol Kolacinski */
518743113ff7SKarol Kolacinski int
ice_aq_read_i2c(struct ice_hw * hw,struct ice_aqc_link_topo_addr topo_addr,u16 bus_addr,__le16 addr,u8 params,u8 * data,struct ice_sq_cd * cd)518843113ff7SKarol Kolacinski ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
518943113ff7SKarol Kolacinski u16 bus_addr, __le16 addr, u8 params, u8 *data,
519043113ff7SKarol Kolacinski struct ice_sq_cd *cd)
519143113ff7SKarol Kolacinski {
519243113ff7SKarol Kolacinski struct ice_aq_desc desc = { 0 };
519343113ff7SKarol Kolacinski struct ice_aqc_i2c *cmd;
519443113ff7SKarol Kolacinski u8 data_size;
519543113ff7SKarol Kolacinski int status;
519643113ff7SKarol Kolacinski
519743113ff7SKarol Kolacinski ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c);
5198fcf9b695SKarol Kolacinski cmd = &desc.params.read_write_i2c;
519943113ff7SKarol Kolacinski
520043113ff7SKarol Kolacinski if (!data)
520143113ff7SKarol Kolacinski return -EINVAL;
520243113ff7SKarol Kolacinski
520343113ff7SKarol Kolacinski data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params);
520443113ff7SKarol Kolacinski
520543113ff7SKarol Kolacinski cmd->i2c_bus_addr = cpu_to_le16(bus_addr);
520643113ff7SKarol Kolacinski cmd->topo_addr = topo_addr;
520743113ff7SKarol Kolacinski cmd->i2c_params = params;
520843113ff7SKarol Kolacinski cmd->i2c_addr = addr;
520943113ff7SKarol Kolacinski
521043113ff7SKarol Kolacinski status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
521143113ff7SKarol Kolacinski if (!status) {
521243113ff7SKarol Kolacinski struct ice_aqc_read_i2c_resp *resp;
521343113ff7SKarol Kolacinski u8 i;
521443113ff7SKarol Kolacinski
521543113ff7SKarol Kolacinski resp = &desc.params.read_i2c_resp;
521643113ff7SKarol Kolacinski for (i = 0; i < data_size; i++) {
521743113ff7SKarol Kolacinski *data = resp->i2c_data[i];
521843113ff7SKarol Kolacinski data++;
521943113ff7SKarol Kolacinski }
522043113ff7SKarol Kolacinski }
522143113ff7SKarol Kolacinski
522243113ff7SKarol Kolacinski return status;
522343113ff7SKarol Kolacinski }
522443113ff7SKarol Kolacinski
522543113ff7SKarol Kolacinski /**
5226fcf9b695SKarol Kolacinski * ice_aq_write_i2c
5227fcf9b695SKarol Kolacinski * @hw: pointer to the hw struct
5228fcf9b695SKarol Kolacinski * @topo_addr: topology address for a device to communicate with
5229fcf9b695SKarol Kolacinski * @bus_addr: 7-bit I2C bus address
5230fcf9b695SKarol Kolacinski * @addr: I2C memory address (I2C offset) with up to 16 bits
5231fcf9b695SKarol Kolacinski * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes)
5232fcf9b695SKarol Kolacinski * @data: pointer to data (0 to 4 bytes) to be written to the I2C device
5233fcf9b695SKarol Kolacinski * @cd: pointer to command details structure or NULL
5234fcf9b695SKarol Kolacinski *
5235fcf9b695SKarol Kolacinski * Write I2C (0x06E3)
5236fcf9b695SKarol Kolacinski *
5237fcf9b695SKarol Kolacinski * * Return:
5238fcf9b695SKarol Kolacinski * * 0 - Successful write to the i2c device
5239fcf9b695SKarol Kolacinski * * -EINVAL - Data size greater than 4 bytes
5240fcf9b695SKarol Kolacinski * * -EIO - FW error
5241fcf9b695SKarol Kolacinski */
5242fcf9b695SKarol Kolacinski int
ice_aq_write_i2c(struct ice_hw * hw,struct ice_aqc_link_topo_addr topo_addr,u16 bus_addr,__le16 addr,u8 params,const u8 * data,struct ice_sq_cd * cd)5243fcf9b695SKarol Kolacinski ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5244bf15bb38SMichal Schmidt u16 bus_addr, __le16 addr, u8 params, const u8 *data,
5245fcf9b695SKarol Kolacinski struct ice_sq_cd *cd)
5246fcf9b695SKarol Kolacinski {
5247fcf9b695SKarol Kolacinski struct ice_aq_desc desc = { 0 };
5248fcf9b695SKarol Kolacinski struct ice_aqc_i2c *cmd;
5249fcf9b695SKarol Kolacinski u8 data_size;
5250fcf9b695SKarol Kolacinski
5251fcf9b695SKarol Kolacinski ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c);
5252fcf9b695SKarol Kolacinski cmd = &desc.params.read_write_i2c;
5253fcf9b695SKarol Kolacinski
5254fcf9b695SKarol Kolacinski data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params);
5255fcf9b695SKarol Kolacinski
5256fcf9b695SKarol Kolacinski /* data_size limited to 4 */
5257fcf9b695SKarol Kolacinski if (data_size > 4)
5258fcf9b695SKarol Kolacinski return -EINVAL;
5259fcf9b695SKarol Kolacinski
5260fcf9b695SKarol Kolacinski cmd->i2c_bus_addr = cpu_to_le16(bus_addr);
5261fcf9b695SKarol Kolacinski cmd->topo_addr = topo_addr;
5262fcf9b695SKarol Kolacinski cmd->i2c_params = params;
5263fcf9b695SKarol Kolacinski cmd->i2c_addr = addr;
5264fcf9b695SKarol Kolacinski
5265fcf9b695SKarol Kolacinski memcpy(cmd->i2c_data, data, data_size);
5266fcf9b695SKarol Kolacinski
5267fcf9b695SKarol Kolacinski return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5268fcf9b695SKarol Kolacinski }
5269fcf9b695SKarol Kolacinski
5270fcf9b695SKarol Kolacinski /**
52717f9ab54dSJacob Keller * ice_aq_set_driver_param - Set driver parameter to share via firmware
52727f9ab54dSJacob Keller * @hw: pointer to the HW struct
52737f9ab54dSJacob Keller * @idx: parameter index to set
52747f9ab54dSJacob Keller * @value: the value to set the parameter to
52757f9ab54dSJacob Keller * @cd: pointer to command details structure or NULL
52767f9ab54dSJacob Keller *
52777f9ab54dSJacob Keller * Set the value of one of the software defined parameters. All PFs connected
52787f9ab54dSJacob Keller * to this device can read the value using ice_aq_get_driver_param.
52797f9ab54dSJacob Keller *
52807f9ab54dSJacob Keller * Note that firmware provides no synchronization or locking, and will not
52817f9ab54dSJacob Keller * save the parameter value during a device reset. It is expected that
52827f9ab54dSJacob Keller * a single PF will write the parameter value, while all other PFs will only
52837f9ab54dSJacob Keller * read it.
52847f9ab54dSJacob Keller */
52857f9ab54dSJacob Keller int
ice_aq_set_driver_param(struct ice_hw * hw,enum ice_aqc_driver_params idx,u32 value,struct ice_sq_cd * cd)52867f9ab54dSJacob Keller ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
52877f9ab54dSJacob Keller u32 value, struct ice_sq_cd *cd)
52887f9ab54dSJacob Keller {
52897f9ab54dSJacob Keller struct ice_aqc_driver_shared_params *cmd;
52907f9ab54dSJacob Keller struct ice_aq_desc desc;
52917f9ab54dSJacob Keller
52927f9ab54dSJacob Keller if (idx >= ICE_AQC_DRIVER_PARAM_MAX)
52937f9ab54dSJacob Keller return -EIO;
52947f9ab54dSJacob Keller
52957f9ab54dSJacob Keller cmd = &desc.params.drv_shared_params;
52967f9ab54dSJacob Keller
52977f9ab54dSJacob Keller ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params);
52987f9ab54dSJacob Keller
52997f9ab54dSJacob Keller cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_SET;
53007f9ab54dSJacob Keller cmd->param_indx = idx;
53017f9ab54dSJacob Keller cmd->param_val = cpu_to_le32(value);
53027f9ab54dSJacob Keller
5303d54699e2STony Nguyen return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
53047f9ab54dSJacob Keller }
53057f9ab54dSJacob Keller
53067f9ab54dSJacob Keller /**
53077f9ab54dSJacob Keller * ice_aq_get_driver_param - Get driver parameter shared via firmware
53087f9ab54dSJacob Keller * @hw: pointer to the HW struct
53097f9ab54dSJacob Keller * @idx: parameter index to set
53107f9ab54dSJacob Keller * @value: storage to return the shared parameter
53117f9ab54dSJacob Keller * @cd: pointer to command details structure or NULL
53127f9ab54dSJacob Keller *
53137f9ab54dSJacob Keller * Get the value of one of the software defined parameters.
53147f9ab54dSJacob Keller *
53157f9ab54dSJacob Keller * Note that firmware provides no synchronization or locking. It is expected
53167f9ab54dSJacob Keller * that only a single PF will write a given parameter.
53177f9ab54dSJacob Keller */
53187f9ab54dSJacob Keller int
ice_aq_get_driver_param(struct ice_hw * hw,enum ice_aqc_driver_params idx,u32 * value,struct ice_sq_cd * cd)53197f9ab54dSJacob Keller ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,
53207f9ab54dSJacob Keller u32 *value, struct ice_sq_cd *cd)
53217f9ab54dSJacob Keller {
53227f9ab54dSJacob Keller struct ice_aqc_driver_shared_params *cmd;
53237f9ab54dSJacob Keller struct ice_aq_desc desc;
53245e24d598STony Nguyen int status;
53257f9ab54dSJacob Keller
53267f9ab54dSJacob Keller if (idx >= ICE_AQC_DRIVER_PARAM_MAX)
53277f9ab54dSJacob Keller return -EIO;
53287f9ab54dSJacob Keller
53297f9ab54dSJacob Keller cmd = &desc.params.drv_shared_params;
53307f9ab54dSJacob Keller
53317f9ab54dSJacob Keller ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params);
53327f9ab54dSJacob Keller
53337f9ab54dSJacob Keller cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_GET;
53347f9ab54dSJacob Keller cmd->param_indx = idx;
53357f9ab54dSJacob Keller
53367f9ab54dSJacob Keller status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
53377f9ab54dSJacob Keller if (status)
5338d54699e2STony Nguyen return status;
53397f9ab54dSJacob Keller
53407f9ab54dSJacob Keller *value = le32_to_cpu(cmd->param_val);
53417f9ab54dSJacob Keller
53427f9ab54dSJacob Keller return 0;
53437f9ab54dSJacob Keller }
53447f9ab54dSJacob Keller
53457f9ab54dSJacob Keller /**
53463bb6324bSMaciej Machnikowski * ice_aq_set_gpio
53473bb6324bSMaciej Machnikowski * @hw: pointer to the hw struct
53483bb6324bSMaciej Machnikowski * @gpio_ctrl_handle: GPIO controller node handle
53493bb6324bSMaciej Machnikowski * @pin_idx: IO Number of the GPIO that needs to be set
53503bb6324bSMaciej Machnikowski * @value: SW provide IO value to set in the LSB
53513bb6324bSMaciej Machnikowski * @cd: pointer to command details structure or NULL
53523bb6324bSMaciej Machnikowski *
53533bb6324bSMaciej Machnikowski * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology
53543bb6324bSMaciej Machnikowski */
53553bb6324bSMaciej Machnikowski int
ice_aq_set_gpio(struct ice_hw * hw,u16 gpio_ctrl_handle,u8 pin_idx,bool value,struct ice_sq_cd * cd)53563bb6324bSMaciej Machnikowski ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
53573bb6324bSMaciej Machnikowski struct ice_sq_cd *cd)
53583bb6324bSMaciej Machnikowski {
53593bb6324bSMaciej Machnikowski struct ice_aqc_gpio *cmd;
53603bb6324bSMaciej Machnikowski struct ice_aq_desc desc;
53613bb6324bSMaciej Machnikowski
53623bb6324bSMaciej Machnikowski ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio);
53633bb6324bSMaciej Machnikowski cmd = &desc.params.read_write_gpio;
53643bb6324bSMaciej Machnikowski cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle);
53653bb6324bSMaciej Machnikowski cmd->gpio_num = pin_idx;
53663bb6324bSMaciej Machnikowski cmd->gpio_val = value ? 1 : 0;
53673bb6324bSMaciej Machnikowski
5368d54699e2STony Nguyen return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
53693bb6324bSMaciej Machnikowski }
53703bb6324bSMaciej Machnikowski
53713bb6324bSMaciej Machnikowski /**
53723bb6324bSMaciej Machnikowski * ice_aq_get_gpio
53733bb6324bSMaciej Machnikowski * @hw: pointer to the hw struct
53743bb6324bSMaciej Machnikowski * @gpio_ctrl_handle: GPIO controller node handle
53753bb6324bSMaciej Machnikowski * @pin_idx: IO Number of the GPIO that needs to be set
53763bb6324bSMaciej Machnikowski * @value: IO value read
53773bb6324bSMaciej Machnikowski * @cd: pointer to command details structure or NULL
53783bb6324bSMaciej Machnikowski *
53793bb6324bSMaciej Machnikowski * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of
53803bb6324bSMaciej Machnikowski * the topology
53813bb6324bSMaciej Machnikowski */
53823bb6324bSMaciej Machnikowski int
ice_aq_get_gpio(struct ice_hw * hw,u16 gpio_ctrl_handle,u8 pin_idx,bool * value,struct ice_sq_cd * cd)53833bb6324bSMaciej Machnikowski ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
53843bb6324bSMaciej Machnikowski bool *value, struct ice_sq_cd *cd)
53853bb6324bSMaciej Machnikowski {
53863bb6324bSMaciej Machnikowski struct ice_aqc_gpio *cmd;
53873bb6324bSMaciej Machnikowski struct ice_aq_desc desc;
53885e24d598STony Nguyen int status;
53893bb6324bSMaciej Machnikowski
53903bb6324bSMaciej Machnikowski ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio);
53913bb6324bSMaciej Machnikowski cmd = &desc.params.read_write_gpio;
53923bb6324bSMaciej Machnikowski cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle);
53933bb6324bSMaciej Machnikowski cmd->gpio_num = pin_idx;
53943bb6324bSMaciej Machnikowski
53953bb6324bSMaciej Machnikowski status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
53963bb6324bSMaciej Machnikowski if (status)
5397d54699e2STony Nguyen return status;
53983bb6324bSMaciej Machnikowski
53993bb6324bSMaciej Machnikowski *value = !!cmd->gpio_val;
54003bb6324bSMaciej Machnikowski return 0;
54013bb6324bSMaciej Machnikowski }
54023bb6324bSMaciej Machnikowski
54033bb6324bSMaciej Machnikowski /**
54041bd50f2dSPaul Greenwalt * ice_is_fw_api_min_ver
54051bd50f2dSPaul Greenwalt * @hw: pointer to the hardware structure
54061bd50f2dSPaul Greenwalt * @maj: major version
54071bd50f2dSPaul Greenwalt * @min: minor version
54081bd50f2dSPaul Greenwalt * @patch: patch version
54091bd50f2dSPaul Greenwalt *
54101bd50f2dSPaul Greenwalt * Checks if the firmware API is minimum version
54111bd50f2dSPaul Greenwalt */
ice_is_fw_api_min_ver(struct ice_hw * hw,u8 maj,u8 min,u8 patch)54121bd50f2dSPaul Greenwalt static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch)
54131bd50f2dSPaul Greenwalt {
54141bd50f2dSPaul Greenwalt if (hw->api_maj_ver == maj) {
54151bd50f2dSPaul Greenwalt if (hw->api_min_ver > min)
54161bd50f2dSPaul Greenwalt return true;
54171bd50f2dSPaul Greenwalt if (hw->api_min_ver == min && hw->api_patch >= patch)
54181bd50f2dSPaul Greenwalt return true;
54191bd50f2dSPaul Greenwalt } else if (hw->api_maj_ver > maj) {
54201bd50f2dSPaul Greenwalt return true;
54211bd50f2dSPaul Greenwalt }
54221bd50f2dSPaul Greenwalt
54231bd50f2dSPaul Greenwalt return false;
54241bd50f2dSPaul Greenwalt }
54251bd50f2dSPaul Greenwalt
54261bd50f2dSPaul Greenwalt /**
5427ea78ce4dSPaul Greenwalt * ice_fw_supports_link_override
5428ea78ce4dSPaul Greenwalt * @hw: pointer to the hardware structure
5429ea78ce4dSPaul Greenwalt *
5430ea78ce4dSPaul Greenwalt * Checks if the firmware supports link override
5431ea78ce4dSPaul Greenwalt */
ice_fw_supports_link_override(struct ice_hw * hw)5432ea78ce4dSPaul Greenwalt bool ice_fw_supports_link_override(struct ice_hw *hw)
5433ea78ce4dSPaul Greenwalt {
54341bd50f2dSPaul Greenwalt return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ,
54351bd50f2dSPaul Greenwalt ICE_FW_API_LINK_OVERRIDE_MIN,
54361bd50f2dSPaul Greenwalt ICE_FW_API_LINK_OVERRIDE_PATCH);
5437ea78ce4dSPaul Greenwalt }
5438ea78ce4dSPaul Greenwalt
5439ea78ce4dSPaul Greenwalt /**
5440ea78ce4dSPaul Greenwalt * ice_get_link_default_override
5441ea78ce4dSPaul Greenwalt * @ldo: pointer to the link default override struct
5442ea78ce4dSPaul Greenwalt * @pi: pointer to the port info struct
5443ea78ce4dSPaul Greenwalt *
5444ea78ce4dSPaul Greenwalt * Gets the link default override for a port
5445ea78ce4dSPaul Greenwalt */
54465e24d598STony Nguyen int
ice_get_link_default_override(struct ice_link_default_override_tlv * ldo,struct ice_port_info * pi)5447ea78ce4dSPaul Greenwalt ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
5448ea78ce4dSPaul Greenwalt struct ice_port_info *pi)
5449ea78ce4dSPaul Greenwalt {
5450ea78ce4dSPaul Greenwalt u16 i, tlv, tlv_len, tlv_start, buf, offset;
5451ea78ce4dSPaul Greenwalt struct ice_hw *hw = pi->hw;
54525e24d598STony Nguyen int status;
5453ea78ce4dSPaul Greenwalt
5454ea78ce4dSPaul Greenwalt status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
5455ea78ce4dSPaul Greenwalt ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
5456ea78ce4dSPaul Greenwalt if (status) {
54579228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n");
5458ea78ce4dSPaul Greenwalt return status;
5459ea78ce4dSPaul Greenwalt }
5460ea78ce4dSPaul Greenwalt
5461ea78ce4dSPaul Greenwalt /* Each port has its own config; calculate for our port */
5462ea78ce4dSPaul Greenwalt tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
5463ea78ce4dSPaul Greenwalt ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
5464ea78ce4dSPaul Greenwalt
5465ea78ce4dSPaul Greenwalt /* link options first */
5466ea78ce4dSPaul Greenwalt status = ice_read_sr_word(hw, tlv_start, &buf);
5467ea78ce4dSPaul Greenwalt if (status) {
54689228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5469ea78ce4dSPaul Greenwalt return status;
5470ea78ce4dSPaul Greenwalt }
5471ea78ce4dSPaul Greenwalt ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
5472ea78ce4dSPaul Greenwalt ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
5473ea78ce4dSPaul Greenwalt ICE_LINK_OVERRIDE_PHY_CFG_S;
5474ea78ce4dSPaul Greenwalt
5475ea78ce4dSPaul Greenwalt /* link PHY config */
5476ea78ce4dSPaul Greenwalt offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
5477ea78ce4dSPaul Greenwalt status = ice_read_sr_word(hw, offset, &buf);
5478ea78ce4dSPaul Greenwalt if (status) {
54799228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n");
5480ea78ce4dSPaul Greenwalt return status;
5481ea78ce4dSPaul Greenwalt }
5482ea78ce4dSPaul Greenwalt ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
5483ea78ce4dSPaul Greenwalt
5484ea78ce4dSPaul Greenwalt /* PHY types low */
5485ea78ce4dSPaul Greenwalt offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
5486ea78ce4dSPaul Greenwalt for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
5487ea78ce4dSPaul Greenwalt status = ice_read_sr_word(hw, (offset + i), &buf);
5488ea78ce4dSPaul Greenwalt if (status) {
54899228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5490ea78ce4dSPaul Greenwalt return status;
5491ea78ce4dSPaul Greenwalt }
5492ea78ce4dSPaul Greenwalt /* shift 16 bits at a time to fill 64 bits */
5493ea78ce4dSPaul Greenwalt ldo->phy_type_low |= ((u64)buf << (i * 16));
5494ea78ce4dSPaul Greenwalt }
5495ea78ce4dSPaul Greenwalt
5496ea78ce4dSPaul Greenwalt /* PHY types high */
5497ea78ce4dSPaul Greenwalt offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
5498ea78ce4dSPaul Greenwalt ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
5499ea78ce4dSPaul Greenwalt for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
5500ea78ce4dSPaul Greenwalt status = ice_read_sr_word(hw, (offset + i), &buf);
5501ea78ce4dSPaul Greenwalt if (status) {
55029228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
5503ea78ce4dSPaul Greenwalt return status;
5504ea78ce4dSPaul Greenwalt }
5505ea78ce4dSPaul Greenwalt /* shift 16 bits at a time to fill 64 bits */
5506ea78ce4dSPaul Greenwalt ldo->phy_type_high |= ((u64)buf << (i * 16));
5507ea78ce4dSPaul Greenwalt }
5508ea78ce4dSPaul Greenwalt
5509ea78ce4dSPaul Greenwalt return status;
5510ea78ce4dSPaul Greenwalt }
55115ee30564SPaul Greenwalt
55125ee30564SPaul Greenwalt /**
55135ee30564SPaul Greenwalt * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
55145ee30564SPaul Greenwalt * @caps: get PHY capability data
55155ee30564SPaul Greenwalt */
ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data * caps)55165ee30564SPaul Greenwalt bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
55175ee30564SPaul Greenwalt {
55185ee30564SPaul Greenwalt if (caps->caps & ICE_AQC_PHY_AN_MODE ||
5519bdeff971SLev Faerman caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
55205ee30564SPaul Greenwalt ICE_AQC_PHY_AN_EN_CLAUSE73 |
55215ee30564SPaul Greenwalt ICE_AQC_PHY_AN_EN_CLAUSE37))
55225ee30564SPaul Greenwalt return true;
55235ee30564SPaul Greenwalt
55245ee30564SPaul Greenwalt return false;
55255ee30564SPaul Greenwalt }
55267d9c9b79SDave Ertman
55277d9c9b79SDave Ertman /**
55287d9c9b79SDave Ertman * ice_aq_set_lldp_mib - Set the LLDP MIB
55297d9c9b79SDave Ertman * @hw: pointer to the HW struct
55307d9c9b79SDave Ertman * @mib_type: Local, Remote or both Local and Remote MIBs
55317d9c9b79SDave Ertman * @buf: pointer to the caller-supplied buffer to store the MIB block
55327d9c9b79SDave Ertman * @buf_size: size of the buffer (in bytes)
55337d9c9b79SDave Ertman * @cd: pointer to command details structure or NULL
55347d9c9b79SDave Ertman *
55357d9c9b79SDave Ertman * Set the LLDP MIB. (0x0A08)
55367d9c9b79SDave Ertman */
55375e24d598STony Nguyen int
ice_aq_set_lldp_mib(struct ice_hw * hw,u8 mib_type,void * buf,u16 buf_size,struct ice_sq_cd * cd)55387d9c9b79SDave Ertman ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
55397d9c9b79SDave Ertman struct ice_sq_cd *cd)
55407d9c9b79SDave Ertman {
55417d9c9b79SDave Ertman struct ice_aqc_lldp_set_local_mib *cmd;
55427d9c9b79SDave Ertman struct ice_aq_desc desc;
55437d9c9b79SDave Ertman
55447d9c9b79SDave Ertman cmd = &desc.params.lldp_set_mib;
55457d9c9b79SDave Ertman
55467d9c9b79SDave Ertman if (buf_size == 0 || !buf)
5547d54699e2STony Nguyen return -EINVAL;
55487d9c9b79SDave Ertman
55497d9c9b79SDave Ertman ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
55507d9c9b79SDave Ertman
55517d9c9b79SDave Ertman desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD);
55527d9c9b79SDave Ertman desc.datalen = cpu_to_le16(buf_size);
55537d9c9b79SDave Ertman
55547d9c9b79SDave Ertman cmd->type = mib_type;
55557d9c9b79SDave Ertman cmd->length = cpu_to_le16(buf_size);
55567d9c9b79SDave Ertman
55577d9c9b79SDave Ertman return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
55587d9c9b79SDave Ertman }
555934295a36SDave Ertman
556034295a36SDave Ertman /**
5561ef860480STony Nguyen * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl
556234295a36SDave Ertman * @hw: pointer to HW struct
556334295a36SDave Ertman */
ice_fw_supports_lldp_fltr_ctrl(struct ice_hw * hw)556434295a36SDave Ertman bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw)
556534295a36SDave Ertman {
556634295a36SDave Ertman if (hw->mac_type != ICE_MAC_E810)
556734295a36SDave Ertman return false;
556834295a36SDave Ertman
55691bd50f2dSPaul Greenwalt return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ,
55701bd50f2dSPaul Greenwalt ICE_FW_API_LLDP_FLTR_MIN,
55711bd50f2dSPaul Greenwalt ICE_FW_API_LLDP_FLTR_PATCH);
557234295a36SDave Ertman }
557334295a36SDave Ertman
557434295a36SDave Ertman /**
557534295a36SDave Ertman * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter
557634295a36SDave Ertman * @hw: pointer to HW struct
557734295a36SDave Ertman * @vsi_num: absolute HW index for VSI
557834295a36SDave Ertman * @add: boolean for if adding or removing a filter
557934295a36SDave Ertman */
55805e24d598STony Nguyen int
ice_lldp_fltr_add_remove(struct ice_hw * hw,u16 vsi_num,bool add)558134295a36SDave Ertman ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add)
558234295a36SDave Ertman {
558334295a36SDave Ertman struct ice_aqc_lldp_filter_ctrl *cmd;
558434295a36SDave Ertman struct ice_aq_desc desc;
558534295a36SDave Ertman
558634295a36SDave Ertman cmd = &desc.params.lldp_filter_ctrl;
558734295a36SDave Ertman
558834295a36SDave Ertman ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl);
558934295a36SDave Ertman
559034295a36SDave Ertman if (add)
559134295a36SDave Ertman cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD;
559234295a36SDave Ertman else
559334295a36SDave Ertman cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE;
559434295a36SDave Ertman
559534295a36SDave Ertman cmd->vsi_num = cpu_to_le16(vsi_num);
559634295a36SDave Ertman
559734295a36SDave Ertman return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
559834295a36SDave Ertman }
55990a02944fSAnirudh Venkataramanan
56000a02944fSAnirudh Venkataramanan /**
5601a4f68f37STsotne Chakhvadze * ice_lldp_execute_pending_mib - execute LLDP pending MIB request
5602a4f68f37STsotne Chakhvadze * @hw: pointer to HW struct
5603a4f68f37STsotne Chakhvadze */
ice_lldp_execute_pending_mib(struct ice_hw * hw)5604a4f68f37STsotne Chakhvadze int ice_lldp_execute_pending_mib(struct ice_hw *hw)
5605a4f68f37STsotne Chakhvadze {
5606a4f68f37STsotne Chakhvadze struct ice_aq_desc desc;
5607a4f68f37STsotne Chakhvadze
5608a4f68f37STsotne Chakhvadze ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib);
5609a4f68f37STsotne Chakhvadze
5610a4f68f37STsotne Chakhvadze return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5611a4f68f37STsotne Chakhvadze }
5612a4f68f37STsotne Chakhvadze
5613a4f68f37STsotne Chakhvadze /**
56140a02944fSAnirudh Venkataramanan * ice_fw_supports_report_dflt_cfg
56150a02944fSAnirudh Venkataramanan * @hw: pointer to the hardware structure
56160a02944fSAnirudh Venkataramanan *
56170a02944fSAnirudh Venkataramanan * Checks if the firmware supports report default configuration
56180a02944fSAnirudh Venkataramanan */
ice_fw_supports_report_dflt_cfg(struct ice_hw * hw)56190a02944fSAnirudh Venkataramanan bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw)
56200a02944fSAnirudh Venkataramanan {
56211bd50f2dSPaul Greenwalt return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ,
56221bd50f2dSPaul Greenwalt ICE_FW_API_REPORT_DFLT_CFG_MIN,
56231bd50f2dSPaul Greenwalt ICE_FW_API_REPORT_DFLT_CFG_PATCH);
56240a02944fSAnirudh Venkataramanan }
56251d0e28a9SBrett Creeley
56261d0e28a9SBrett Creeley /* each of the indexes into the following array match the speed of a return
56271d0e28a9SBrett Creeley * value from the list of AQ returned speeds like the range:
56281d0e28a9SBrett Creeley * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding
56291d0e28a9SBrett Creeley * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this
56301d0e28a9SBrett Creeley * array. The array is defined as 15 elements long because the link_speed
56311d0e28a9SBrett Creeley * returned by the firmware is a 16 bit * value, but is indexed
56321d0e28a9SBrett Creeley * by [fls(speed) - 1]
56331d0e28a9SBrett Creeley */
5634b2dbde3aSMichal Swiatkowski static const u32 ice_aq_to_link_speed[] = {
56351d0e28a9SBrett Creeley SPEED_10, /* BIT(0) */
56361d0e28a9SBrett Creeley SPEED_100,
56371d0e28a9SBrett Creeley SPEED_1000,
56381d0e28a9SBrett Creeley SPEED_2500,
56391d0e28a9SBrett Creeley SPEED_5000,
56401d0e28a9SBrett Creeley SPEED_10000,
56411d0e28a9SBrett Creeley SPEED_20000,
56421d0e28a9SBrett Creeley SPEED_25000,
56431d0e28a9SBrett Creeley SPEED_40000,
56441d0e28a9SBrett Creeley SPEED_50000,
56451d0e28a9SBrett Creeley SPEED_100000, /* BIT(10) */
56461d0e28a9SBrett Creeley };
56471d0e28a9SBrett Creeley
56481d0e28a9SBrett Creeley /**
56491d0e28a9SBrett Creeley * ice_get_link_speed - get integer speed from table
56501d0e28a9SBrett Creeley * @index: array index from fls(aq speed) - 1
56511d0e28a9SBrett Creeley *
56521d0e28a9SBrett Creeley * Returns: u32 value containing integer speed
56531d0e28a9SBrett Creeley */
ice_get_link_speed(u16 index)56541d0e28a9SBrett Creeley u32 ice_get_link_speed(u16 index)
56551d0e28a9SBrett Creeley {
5656b2dbde3aSMichal Swiatkowski if (index >= ARRAY_SIZE(ice_aq_to_link_speed))
5657b2dbde3aSMichal Swiatkowski return 0;
5658b2dbde3aSMichal Swiatkowski
56591d0e28a9SBrett Creeley return ice_aq_to_link_speed[index];
56601d0e28a9SBrett Creeley }
5661