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/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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/openbmc/linux/Documentation/virt/kvm/x86/
H A Dhypercalls.rst1 .. SPDX-License-Identifier: GPL-2.0
8 KVM Hypercalls have a three-byte sequence of either the vmcall or the vmmcall
18 R2-R7 are used for parameters 1-6. In addition, R1 is used for hypercall
25 refer to Documentation/virt/kvm/s390/s390-diag.rst.
28 It uses R3-R10 and hypercall number in R11. R4-R11 are used as output registers.
31 KVM hypercalls uses 4 byte opcode, that are patched with 'hypercall-instructions'
33 For more information refer to Documentation/virt/kvm/ppc-pv.rst
37 number in $2 (v0). Up to four arguments may be placed in $4-$7 (a0-a3) and
50 ------------------------
58 ----------------
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/openbmc/linux/arch/x86/kernel/fpu/
H A Dxstate.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 xsave->header.xcomp_bv = mask | XCOMP_BV_COMPACTED_FORMAT; in xstate_init_xcomp_bv()
25 struct fpu *fpu = &current->group_leader->thread.fpu; in xstate_get_group_perm()
29 perm = guest ? &fpu->guest_perm : &fpu->perm; in xstate_get_group_perm()
30 return READ_ONCE(perm->__state_perm); in xstate_get_group_perm()
49 enum xstate_copy_mode mode);
102 * If XSAVES is enabled, it replaces XSAVEC because it supports supervisor
160 u64 xfd = fpstate->xfd; in xfd_update_state()
174 return -EPERM; in __xfd_enable_feature()
186 u64 mask = fpstate->xfeatures; in os_xsave()
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/openbmc/linux/Documentation/userspace-api/
H A Dseccomp_filter.rst25 to time-of-check-time-of-use (TOCTOU) attacks that are common in system
46 An additional seccomp mode is added and is enabled using the same
65 call will return -1 and set errno to ``EINVAL``.
73 true, ``-EACCES`` will be returned. This requirement ensures that filter
82 The above call returns 0 on success and non-zero on error.
106 task without executing the system call. ``siginfo->si_call_addr``
108 ``siginfo->si_syscall`` and ``siginfo->si_arch`` will indicate which
111 instruction). The return value register will contain an arch-
112 dependent value -- if resuming execution, set it to something
114 it with ``-ENOSYS`` could overwrite some useful information.)
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/openbmc/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv22 1, 0, ECX, 2, dtes64, DS area uses 64-bit layout
26 1, 0, ECX, 6, smx, Safer Mode Extension supported
30 …, 10, l1_ctx_id, L1 data cache could be set to either adaptive mode or shared mode (check IA32…
33 1, 0, ECX, 13, cmpxchg16b, 'CMPXCHG16B - Compare and Exchange Bytes' supported
36 1, 0, ECX, 17, pcid, Process-Context Identifiers feature present
43 …1, 0, ECX, 24, tsc_deadline_timer, LAPIC supports one-shot operation using a TSC deadline …
48 1, 0, ECX, 29, f16c, 16-bit floating-point conversion instruction supported
52 1, 0, EDX, 1, vme, Virtual-8086 Mode Enhancement
67 1, 0, EDX, 17, pse36, 36-Bit Page Size Extension
103 4, 0, ECX, 31:0, cache_sets, Number of Sets - 1
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/openbmc/linux/arch/powerpc/include/asm/
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * number used in the Programming Environments Manual For 32-Bit
17 #include <asm/asm-const.h>
18 #include <asm/feature-fixups.h>
31 #define MSR_SF_LG 63 /* Enable 64 bit mode */
49 #define MSR_FE0_LG 11 /* Floating Exception mode 0 */
53 #define MSR_FE1_LG 8 /* Floating Exception mode 1 */
58 #define MSR_PX_LG 2 /* Protection Exclusive Mode */
70 #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
74 /* so tests for these bits fail on 32-bit */
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/openbmc/linux/Documentation/virt/kvm/
H A Dppc-pv.rst1 .. SPDX-License-Identifier: GPL-2.0
35 'hypercall-instructions'. This property contains at most 4 opcodes that make
43 r0 - volatile
53 r12 - volatile
74 page that contains parts of supervisor visible register state. The guest can
79 MMU is enabled. The second parameter indicates the address in real mode, if
80 applicable to the target. For now, we always map the page to -4096. This way we
84 ld rX, -4096(0)
133 - MSR_EE
134 - MSR_RI
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H A Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
13 - System ioctls: These query and set global attributes which affect the
17 - VM ioctls: These query and set attributes that affect an entire virtual
24 - vcpu ioctls: These query and set attributes that control the operation
32 - device ioctls: These query and set attributes that control the operation
80 facility that allows backward-compatible extensions to the API to be
104 the ioctl returns -ENOTTY.
122 -----------------------
139 -----------------
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/openbmc/linux/arch/m68k/ifpsp060/src/
H A Disp.S3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
98 mov.l %d0,-(%sp)
99 mov.l (_060ISP_TABLE-0x80+_off_chk,%pc),%d0
100 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
106 mov.l %d0,-(%sp)
107 mov.l (_060ISP_TABLE-0x80+_off_divbyzero,%pc),%d0
108 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
114 mov.l %d0,-(%sp)
115 mov.l (_060ISP_TABLE-0x80+_off_trace,%pc),%d0
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/openbmc/qemu/target/riscv/
H A Dcpu_helper.c2 * RISC-V CPU helpers for qemu.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
22 #include "qemu/main-loop.h"
26 #include "exec/exec-all.h"
27 #include "exec/page-protection.h"
29 #include "tcg/tcg-op.h"
31 #include "semihosting/common-semi.h"
32 #include "sysemu/cpu-timers.h"
35 #include "tcg/oversized-guest.h"
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/openbmc/linux/tools/arch/x86/include/asm/
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS 21 /* N 32-bit words worth of info */
17 #define NBUGINTS 2 /* N 32-bit bug flags */
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
30 #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
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/openbmc/linux/arch/x86/include/asm/
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS 22 /* N 32-bit words worth of info */
17 #define NBUGINTS 2 /* N 32-bit bug flags */
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
30 #define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
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/openbmc/linux/arch/x86/kvm/mmu/
H A Dmmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
64 int __read_mostly nx_huge_pages = -1;
100 * When setting this variable to true it enables Two-Dimensional-Paging
102 * 1. the guest-virtual to guest-physical
103 * 2. while doing 1. it walks guest-physical to host-physical
204 return !!(regs->reg & flag); \
226 return !!(mmu->cpu_role. base_or_ext . reg##_##name); \
239 return mmu->cpu_role.base.level > 0; in is_cr0_pg()
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/openbmc/linux/arch/powerpc/kernel/
H A Dprocess.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
57 #include <asm/code-patching.h>
61 #include <asm/asm-prototypes.h>
79 * Are we running in "Suspend disabled" mode? If so we have to block any
93 if (tsk == current && tsk->thread.regs && in check_if_tm_restore_required()
94 MSR_TM_ACTIVE(tsk->thread.regs->msr) && in check_if_tm_restore_required()
96 regs_set_return_msr(&tsk->thread.ckpt_regs, in check_if_tm_restore_required()
97 tsk->thread.regs->msr); in check_if_tm_restore_required()
158 msr = tsk->thread.regs->msr; in __giveup_fpu()
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/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_hv_uvmem.c1 // SPDX-License-Identifier: GPL-2.0
10 * A pseries guest can be run as secure guest on Ultravisor-enabled
15 * The page-in or page-out requests from UV will come to HV as hcalls and
31 * kvm->arch.uvmem_lock is a per-guest lock that prevents concurrent
32 * page-in and page-out requests for the same GPA. Concurrent accesses
37 * migrate_vma routines and page-in/out routines.
39 * Per-guest mutex comes with a cost though. Mainly it serializes the
40 * fault path as page-out can occur when HV faults on accessing secure
41 * guest pages. Currently UV issues page-in requests for all the guest
43 * not a cause for concern. Also currently the number of page-outs caused
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H A Dbooke.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
94 printk("pc: %08lx msr: %08llx\n", vcpu->arch.regs.nip, in kvmppc_dump_vcpu()
95 vcpu->arch.shared->msr); in kvmppc_dump_vcpu()
96 printk("lr: %08lx ctr: %08lx\n", vcpu->arch.regs.link, in kvmppc_dump_vcpu()
97 vcpu->arch.regs.ctr); in kvmppc_dump_vcpu()
98 printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0, in kvmppc_dump_vcpu()
99 vcpu->arch.shared->srr1); in kvmppc_dump_vcpu()
101 printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions); in kvmppc_dump_vcpu()
119 vcpu->arch.shadow_msr &= ~MSR_SPE; in kvmppc_vcpu_disable_spe()
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/openbmc/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt5 force -- enable ACPI if default was off
6 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
7 off -- disable ACPI if default was on
8 noirq -- do not use ACPI for IRQ routing
9 strict -- Be less tolerant of platforms that are not
11 rsdt -- prefer RSDT over (default) XSDT
12 copy_dsdt -- copy DSDT to memory
26 If set to vendor, prefer vendor-specific driver
30 If set to native, use the device's native backlight mode.
58 Documentation/firmware-guide/acpi/debug.rst for more information about
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/openbmc/qemu/target/arm/tcg/
H A Dtranslate.c5 * Copyright (c) 2005-2007 CodeSourcery
24 #include "translate-a32.h"
29 #include "exec/helper-proto.h"
32 #include "exec/helper-info.c.inc"
87 /* no-op */ in asimd_imm_const()
155 if (!s->condjmp) { in arm_gen_condlabel()
156 s->condlabel = gen_disas_label(s); in arm_gen_condlabel()
157 s->condjmp = 1; in arm_gen_condlabel()
229 switch (s->mmu_idx) { in get_a32_user_mem_index()
259 return diff + (s->thumb ? 4 : 8); in jmp_diff()
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/openbmc/qemu/target/ppc/
H A Dcpu_init.c5 * Copyright (c) 2003-2007 Jocelyn Mayer
23 #include "disas/dis-asm.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
33 #include "qemu/qemu-print.h"
37 #include "hw/qdev-properties.h"
39 #include "mmu-book3s-v3.h"
47 #include "power8-pmu.h"
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/openbmc/qemu/target/i386/
H A Dcpu.c23 #include "qemu/qemu-print.h"
24 #include "qemu/hw-version.h"
26 #include "tcg/helper-tcg.h"
28 #include "hvf/hvf-i386.h"
32 #include "qemu/error-report.h"
33 #include "qapi/qapi-visit-machine.h"
34 #include "standard-headers/asm-x86/kvm_para.h"
35 #include "hw/qdev-properties.h"
39 #include "qapi/qapi-commands-machine-target.h"
40 #include "exec/address-spaces.h"
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