include/asm/cpufeatures.h

1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS			22	   /* N 32-bit words worth of info */
17 #define NBUGINTS			2	   /* N 32-bit bug flags */
25  * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
30 #define X86_FEATURE_VME			( 0*32+ 1) /* Virtual Mode Extensions */
34 #define X86_FEATURE_MSR			( 0*32+ 5) /* Model-Specific Registers */
45 #define X86_FEATURE_PSE36		( 0*32+17) /* 36-bit PSEs */
55 #define X86_FEATURE_HT			( 0*32+28) /* Hyper-Threading */
57 #define X86_FEATURE_IA64		( 0*32+30) /* IA-64 processor */
60 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
69 #define X86_FEATURE_LM			( 1*32+29) /* Long Mode (x86-64, 64-bit support) */
73 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
74 #define X86_FEATURE_RECOVERY		( 2*32+ 0) /* CPU in recovery mode */
78 /* Other features, Linux-defined mapping, word 3 */
94 #define X86_FEATURE_PEBS		( 3*32+12) /* Precise-Event Based Sampling */
103 #define X86_FEATURE_ALWAYS		( 3*32+21) /* "" Always-present feature */
109 #define X86_FEATURE_AMD_DCM		( 3*32+27) /* AMD multi-node processor */
110 #define X86_FEATURE_APERFMPERF		( 3*32+28) /* P-State hardware coordination feedback capability (AP…
115 /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */
116 #define X86_FEATURE_XMM3		( 4*32+ 0) /* "pni" SSE-3 */
118 #define X86_FEATURE_DTES64		( 4*32+ 2) /* 64-bit Debug Store */
120 #define X86_FEATURE_DSCPL		( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */
122 #define X86_FEATURE_SMX			( 4*32+ 6) /* Safer Mode eXtensions */
125 #define X86_FEATURE_SSSE3		( 4*32+ 9) /* Supplemental SSE-3 */
128 #define X86_FEATURE_FMA			( 4*32+12) /* Fused multiply-add */
134 #define X86_FEATURE_XMM4_1		( 4*32+19) /* "sse4_1" SSE-4.1 */
135 #define X86_FEATURE_XMM4_2		( 4*32+20) /* "sse4_2" SSE-4.2 */
144 #define X86_FEATURE_F16C		( 4*32+29) /* 16-bit FP conversions */
148 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
151 #define X86_FEATURE_XCRYPT		( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
152 #define X86_FEATURE_XCRYPT_EN		( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
161 #define X86_FEATURE_LAHF_LM		( 6*32+ 0) /* LAHF/SAHF in long mode */
165 #define X86_FEATURE_CR8_LEGACY		( 6*32+ 4) /* CR8 in 32-bit mode */
167 #define X86_FEATURE_SSE4A		( 6*32+ 6) /* SSE-4A */
168 #define X86_FEATURE_MISALIGNSSE		( 6*32+ 7) /* Misaligned SSE mode */
170 #define X86_FEATURE_OSVW		( 6*32+ 9) /* OS Visible Workaround */
184 #define X86_FEATURE_PTSC		( 6*32+27) /* Performance time-stamp counter */
189  * Auxiliary flags: Linux defined - For features scattered in various
201 #define X86_FEATURE_HW_PSTATE		( 7*32+ 8) /* AMD HW-PState */
206 #define X86_FEATURE_RSB_VMEXIT		( 7*32+13) /* "" Fill RSB on VM-Exit */
234 #define X86_FEATURE_EPT_AD		( 8*32+17) /* Intel Extended Page Table access-dirty bit */
241 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
249 #define X86_FEATURE_SMEP		( 9*32+ 7) /* Supervisor Mode Execution Protection */
258 #define X86_FEATURE_AVX512F		( 9*32+16) /* AVX-512 Foundation */
259 #define X86_FEATURE_AVX512DQ		( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
262 #define X86_FEATURE_SMAP		( 9*32+20) /* Supervisor Mode Access Prevention */
263 #define X86_FEATURE_AVX512IFMA		( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
267 #define X86_FEATURE_AVX512PF		( 9*32+26) /* AVX-512 Prefetch */
268 #define X86_FEATURE_AVX512ER		( 9*32+27) /* AVX-512 Exponential and Reciprocal */
269 #define X86_FEATURE_AVX512CD		( 9*32+28) /* AVX-512 Conflict Detection */
271 #define X86_FEATURE_AVX512BW		( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */
272 #define X86_FEATURE_AVX512VL		( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */
282  * Extended auxiliary flags: Linux defined - for features scattered in various
294 #define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
310 #define X86_FEATURE_USER_SHSTK		(11*32+23) /* Shadow stack support for user mode applications */
320 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
325 #define X86_FEATURE_FZRM		(12*32+10) /* "" Fast zero-length REP MOVSB */
333 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
342 …MD_STIBP_ALWAYS_ON	(13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
359 #define X86_FEATURE_HWP			(14*32+ 7) /* Intel Hardware P-states */
373 #define X86_FEATURE_FLUSHBYASID		(15*32+ 6) /* flush-by-ASID support */
385 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
387 #define X86_FEATURE_UMIP		(16*32+ 2) /* User Mode Instruction Protection */
395 #define X86_FEATURE_VPCLMULQDQ		(16*32+10) /* Carry-Less Multiplication Double Quadword */
397 #define X86_FEATURE_AVX512_BITALG	(16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instruct…
400 #define X86_FEATURE_LA57		(16*32+16) /* 5-level page tables */
409 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
414 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
415 #define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */
416 #define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
418 #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
440 /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
444 #define X86_FEATURE_SEV_ES		(19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
446 #define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */
447 #define X86_FEATURE_DEBUG_SWAP		(19*32+14) /* AMD SEV-ES full debug state swap support */
449 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
461  * Extended auxiliary flags: Linux defined - for features scattered in various
488  * 64-bit kernels don't use X86_BUG_ESPFIX.  Make the define conditional
491 #define X86_BUG_ESPFIX			X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */
512 #define X86_BUG_SMT_RSB			X86_BUG(29) /* CPU is vulnerable to Cross-Thread Return Address Predictio…