Lines Matching +full:supervisor +full:- +full:mode +full:- +full:visible
23 #include "qemu/qemu-print.h"
24 #include "qemu/hw-version.h"
26 #include "tcg/helper-tcg.h"
28 #include "hvf/hvf-i386.h"
32 #include "qemu/error-report.h"
33 #include "qapi/qapi-visit-machine.h"
34 #include "standard-headers/asm-x86/kvm_para.h"
35 #include "hw/qdev-properties.h"
39 #include "qapi/qapi-commands-machine-target.h"
40 #include "exec/address-spaces.h"
42 #include "hw/i386/sgx-epc.h"
46 #include "cpu-internal.h"
202 assert(cache->size > 0); in cpuid2_cache_descriptor()
203 assert(cache->level > 0); in cpuid2_cache_descriptor()
204 assert(cache->line_size > 0); in cpuid2_cache_descriptor()
205 assert(cache->associativity > 0); in cpuid2_cache_descriptor()
208 if (d->level == cache->level && d->type == cache->type && in cpuid2_cache_descriptor()
209 d->size == cache->size && d->line_size == cache->line_size && in cpuid2_cache_descriptor()
210 d->associativity == cache->associativity) { in cpuid2_cache_descriptor()
263 return num_ids - 1; in max_thread_ids_for_cache()
268 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - in max_core_ids_in_package()
270 return num_cores - 1; in max_core_ids_in_package()
279 assert(cache->size == cache->line_size * cache->associativity * in encode_cache_cpuid4()
280 cache->partitions * cache->sets); in encode_cache_cpuid4()
282 *eax = CACHE_TYPE(cache->type) | in encode_cache_cpuid4()
283 CACHE_LEVEL(cache->level) | in encode_cache_cpuid4()
284 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | in encode_cache_cpuid4()
286 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); in encode_cache_cpuid4()
288 assert(cache->line_size > 0); in encode_cache_cpuid4()
289 assert(cache->partitions > 0); in encode_cache_cpuid4()
290 assert(cache->associativity > 0); in encode_cache_cpuid4()
291 /* We don't implement fully-associative caches */ in encode_cache_cpuid4()
292 assert(cache->associativity < cache->sets); in encode_cache_cpuid4()
293 *ebx = (cache->line_size - 1) | in encode_cache_cpuid4()
294 ((cache->partitions - 1) << 12) | in encode_cache_cpuid4()
295 ((cache->associativity - 1) << 22); in encode_cache_cpuid4()
297 assert(cache->sets > 0); in encode_cache_cpuid4()
298 *ecx = cache->sets - 1; in encode_cache_cpuid4()
300 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | in encode_cache_cpuid4()
301 (cache->inclusive ? CACHE_INCLUSIVE : 0) | in encode_cache_cpuid4()
302 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); in encode_cache_cpuid4()
312 return topo_info->threads_per_core; in num_threads_by_topo_level()
314 return topo_info->threads_per_core * topo_info->cores_per_module; in num_threads_by_topo_level()
316 return topo_info->threads_per_core * topo_info->cores_per_module * in num_threads_by_topo_level()
317 topo_info->modules_per_die; in num_threads_by_topo_level()
319 return topo_info->threads_per_core * topo_info->cores_per_module * in num_threads_by_topo_level()
320 topo_info->modules_per_die * topo_info->dies_per_pkg; in num_threads_by_topo_level()
385 level = find_next_bit(env->avail_cpu_topo, in encode_topo_cpuid1f()
406 next_level = find_next_bit(env->avail_cpu_topo, in encode_topo_cpuid1f()
416 /* The count (bits 15-00) doesn't need to be reliable. */ in encode_topo_cpuid1f()
419 *edx = cpu->apic_id; in encode_topo_cpuid1f()
427 assert(cache->size % 1024 == 0); in encode_cache_cpuid80000005()
428 assert(cache->lines_per_tag > 0); in encode_cache_cpuid80000005()
429 assert(cache->associativity > 0); in encode_cache_cpuid80000005()
430 assert(cache->line_size > 0); in encode_cache_cpuid80000005()
431 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | in encode_cache_cpuid80000005()
432 (cache->lines_per_tag << 8) | (cache->line_size); in encode_cache_cpuid80000005()
459 assert(l2->size % 1024 == 0); in encode_cache_cpuid80000006()
460 assert(l2->associativity > 0); in encode_cache_cpuid80000006()
461 assert(l2->lines_per_tag > 0); in encode_cache_cpuid80000006()
462 assert(l2->line_size > 0); in encode_cache_cpuid80000006()
463 *ecx = ((l2->size / 1024) << 16) | in encode_cache_cpuid80000006()
464 (AMD_ENC_ASSOC(l2->associativity) << 12) | in encode_cache_cpuid80000006()
465 (l2->lines_per_tag << 8) | (l2->line_size); in encode_cache_cpuid80000006()
468 assert(l3->size % (512 * 1024) == 0); in encode_cache_cpuid80000006()
469 assert(l3->associativity > 0); in encode_cache_cpuid80000006()
470 assert(l3->lines_per_tag > 0); in encode_cache_cpuid80000006()
471 assert(l3->line_size > 0); in encode_cache_cpuid80000006()
472 *edx = ((l3->size / (512 * 1024)) << 18) | in encode_cache_cpuid80000006()
473 (AMD_ENC_ASSOC(l3->associativity) << 12) | in encode_cache_cpuid80000006()
474 (l3->lines_per_tag << 8) | (l3->line_size); in encode_cache_cpuid80000006()
486 assert(cache->size == cache->line_size * cache->associativity * in encode_cache_cpuid8000001d()
487 cache->partitions * cache->sets); in encode_cache_cpuid8000001d()
489 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | in encode_cache_cpuid8000001d()
490 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); in encode_cache_cpuid8000001d()
491 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; in encode_cache_cpuid8000001d()
493 assert(cache->line_size > 0); in encode_cache_cpuid8000001d()
494 assert(cache->partitions > 0); in encode_cache_cpuid8000001d()
495 assert(cache->associativity > 0); in encode_cache_cpuid8000001d()
496 /* We don't implement fully-associative caches */ in encode_cache_cpuid8000001d()
497 assert(cache->associativity < cache->sets); in encode_cache_cpuid8000001d()
498 *ebx = (cache->line_size - 1) | in encode_cache_cpuid8000001d()
499 ((cache->partitions - 1) << 12) | in encode_cache_cpuid8000001d()
500 ((cache->associativity - 1) << 22); in encode_cache_cpuid8000001d()
502 assert(cache->sets > 0); in encode_cache_cpuid8000001d()
503 *ecx = cache->sets - 1; in encode_cache_cpuid8000001d()
505 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | in encode_cache_cpuid8000001d()
506 (cache->inclusive ? CACHE_INCLUSIVE : 0) | in encode_cache_cpuid8000001d()
507 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); in encode_cache_cpuid8000001d()
517 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); in encode_topo_cpuid8000001e()
519 *eax = cpu->apic_id; in encode_topo_cpuid8000001e()
523 * Read-only. Reset: 0000_XXXXh. in encode_topo_cpuid8000001e()
528 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. in encode_topo_cpuid8000001e()
530 * 7:0 CoreId: core ID. Read-only. Reset: XXh. in encode_topo_cpuid8000001e()
535 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); in encode_topo_cpuid8000001e()
539 * Read-only. Reset: 0000_0XXXh. in encode_topo_cpuid8000001e()
543 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. in encode_topo_cpuid8000001e()
547 * 7h-1h Reserved. in encode_topo_cpuid8000001e()
548 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. in encode_topo_cpuid8000001e()
556 if (cpu->legacy_multi_node) { in encode_topo_cpuid8000001e()
557 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | in encode_topo_cpuid8000001e()
558 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); in encode_topo_cpuid8000001e()
560 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; in encode_topo_cpuid8000001e()
711 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
714 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
724 * bit[02]: Support Single-Range Output scheme;
782 * Kernel-only features that can be shown to usermode programs even if
783 * they aren't actually supported by TCG, because qemu-user only runs
814 * in usermode or by 32-bit programs. Those are added to supported
815 * TCG features unconditionally in user-mode emulation mode. This may
819 * Even for long mode, qemu-i386 is not running "a userspace program on a
820 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment"
821 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit
822 * but again the difference is only visible in kernel mode.
827 /* FIXME: Long mode not yet supported for i386 bsd-user */
942 "ds-cpl", "vmx", "smx", "est",
947 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
967 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
976 "lahf-lm", "cmp-legacy", "svm", "extapic",
980 "fma4", "tce", NULL, "nodeid-msr",
981 NULL, "tbm", "topoext", "perfctr-core",
982 "perfctr-nb", NULL, NULL, NULL,
989 * "-cpu host", as it requires consistent cache topology info
997 NULL, NULL, "xstore", "xstore-en",
998 NULL, NULL, "xcrypt", "xcrypt-en",
999 "ace2", "ace2-en", "phe", "phe-en",
1000 "pmm", "pmm-en", NULL, NULL,
1012 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
1013 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
1014 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi",
1015 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
1018 "kvmclock-stable-bit", NULL, NULL, NULL,
1027 "kvm-hint-dedicated", NULL, NULL, NULL,
1039 * KVM hints aren't auto-enabled by -cpu host, they need to be
1040 * explicitly enabled in the command-line.
1047 "npt", "lbrv", "svm-lock", "nrip-save",
1048 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1049 NULL, NULL, "pause-filter", NULL,
1050 "pfthreshold", "avic", NULL, "v-vmsave-vmload",
1054 "svme-addr-chk", NULL, NULL, NULL,
1062 "fsgsbase", "tsc-adjust", "sgx", "bmi1",
1063 "hle", "avx2", "fdp-excptn-only", "smep",
1065 NULL, "zero-fcs-fds", "mpx", NULL,
1068 "clwb", "intel-pt", "avx512pf", "avx512er",
1069 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1084 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
1087 "bus-lock-detect", "cldemote", NULL, "movdiri",
1100 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1102 "avx512-vp2intersect", NULL, "md-clear", NULL,
1104 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr",
1105 NULL, NULL, "amx-bf16", "avx512-fp16",
1106 "amx-tile", "amx-int8", "spec-ctrl", "stibp",
1107 "flush-l1d", "arch-capabilities", "core-capability", "ssbd",
1120 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
1124 NULL, "amx-fp16", NULL, "avx-ifma",
1139 "avx-vnni-int8", "avx-ne-convert", NULL, NULL,
1140 "amx-complex", NULL, "avx-vnni-int16", NULL,
1157 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u",
1158 "bhi-ctrl", "mcdt-no", NULL, NULL,
1176 [16] = "avx10-128",
1177 [17] = "avx10-256",
1178 [18] = "avx10-512",
1206 "overflow-recov", "succor", NULL, NULL,
1225 "ibpb", NULL, "ibrs", "amd-stibp",
1226 NULL, "stibp-always-on", NULL, NULL,
1228 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1229 "amd-psfd", NULL, NULL, NULL,
1238 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
1239 NULL, NULL, "null-sel-clr-base", NULL,
1240 "auto-ibrs", NULL, NULL, NULL,
1245 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL,
1260 "perfmon-v2", NULL, NULL, NULL,
1363 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1364 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1365 "taa-no", NULL, NULL, NULL,
1366 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no",
1367 NULL, "fb-clear", NULL, NULL,
1369 "pbrsb-no", NULL, "gds-no", "rfds-no",
1370 "rfds-clear", NULL, NULL, NULL,
1376 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which
1377 * cannot be read from user mode. Therefore, it has no impact
1378 > on any user-mode operation, and warnings about unsupported
1387 NULL, "split-lock-detect", NULL, NULL,
1405 NULL, "full-width-write", NULL, NULL,
1419 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1420 NULL, NULL, NULL, "vmx-hlt-exit",
1421 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1422 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1423 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1424 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1425 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1426 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1436 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1437 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1438 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1439 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1440 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1441 "vmx-xsaves", NULL, NULL, NULL,
1442 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL,
1453 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1454 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1474 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1476 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1477 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1478 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1479 "vmx-exit-save-efer", "vmx-exit-load-efer",
1480 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1481 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1482 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls",
1492 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1494 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1495 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1496 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1497 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred",
1510 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1511 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1516 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1526 "vmx-ept-execonly", NULL, NULL, NULL,
1527 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1530 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1531 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1532 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1534 "vmx-invvpid", NULL, NULL, NULL,
1536 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1537 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1552 [54] = "vmx-ins-outs",
1553 [55] = "vmx-true-ctls",
1554 [56] = "vmx-any-errcode",
1555 [58] = "vmx-nested-exception",
1560 /* Just to be safe - we don't support setting the MSEG version field. */
1567 [0] = "vmx-eptp-switching",
1584 NULL, NULL, NULL, "intel-pt-lip",
1599 NULL, NULL, NULL, "sgx-edeccssa",
1617 "sgx-exinfo" , NULL, NULL, NULL,
1637 NULL, "sgx-debug", "sgx-mode64", NULL,
1638 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
1639 NULL, NULL, "sgx-aex-notify", NULL,
1869 .offset = 0 /*supervisor mode component, offset = 0 */,
1891 offset = compacted ? ret : esa->offset; in xsave_area_size()
1892 ret = MAX(ret, offset + esa->size); in xsave_area_size()
1905 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | in x86_cpu_xsave_xcr0_components()
1906 cpu->env.features[FEAT_XSAVE_XCR0_LO]; in x86_cpu_xsave_xcr0_components()
1909 /* Return name of 32-bit register, from a R_* constant */
1920 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | in x86_cpu_xsave_xss_components()
1921 cpu->env.features[FEAT_XSAVE_XSS_LO]; in x86_cpu_xsave_xss_components()
1931 CPUX86State *env = &cpu->env; in x86_cpu_get_migratable_flags()
1940 if ((wi->migratable_flags & f) || in x86_cpu_get_migratable_flags()
1941 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { in x86_cpu_get_migratable_flags()
1946 /* when tsc-khz is set explicitly, invtsc is migratable */ in x86_cpu_get_migratable_flags()
1947 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { in x86_cpu_get_migratable_flags()
2024 /* vendor is zero-terminated, 12 character ASCII string */
2051 * This matters only for "-cpu help" and query-cpu-definitions
2061 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); in x86_cpu_versioned_model_name()
2073 return def->versions ?: default_version_list; in x86_cpu_def_get_versions()
2457 * Dual-monitor support (all processors)
2459 * Deactivate dual-monitor treatment
2460 * Number of CR3-target values
2462 * Wait-for-SIPI activity state
2463 * PAUSE-loop exiting (Westmere and newer)
2464 * EPT-violation #VE (Broadwell and newer)
2466 * Conceal non-root operation from PT
2470 * Mode-based execute control (XS/XU)
2477 * Advanced VM-exit information for EPT violations
2478 * Sub-page write permissions
2533 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
2660 .model_id = "Common 32-bit KVM processor"
2933 .alias = "Nehalem-IBRS",
2935 { "spec-ctrl", "on" },
2936 { "model-id",
3009 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
3014 .alias = "Westmere-IBRS",
3016 { "spec-ctrl", "on" },
3017 { "model-id",
3100 .alias = "SandyBridge-IBRS",
3102 { "spec-ctrl", "on" },
3103 { "model-id",
3187 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
3192 .alias = "IvyBridge-IBRS",
3194 { "spec-ctrl", "on" },
3195 { "model-id",
3196 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
3289 .alias = "Haswell-noTSX",
3294 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
3300 .alias = "Haswell-IBRS",
3302 /* Restore TSX features removed by -v2 above */
3306 * Haswell and Haswell-IBRS had stepping=4 in
3310 { "spec-ctrl", "on" },
3311 { "model-id",
3318 .alias = "Haswell-noTSX-IBRS",
3322 /* spec-ctrl was already enabled by -v3 above */
3324 { "model-id",
3420 .alias = "Broadwell-noTSX",
3424 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
3430 .alias = "Broadwell-IBRS",
3432 /* Restore TSX features removed by -v2 above */
3435 { "spec-ctrl", "on" },
3436 { "model-id",
3443 .alias = "Broadwell-noTSX-IBRS",
3447 /* spec-ctrl was already enabled by -v3 above */
3448 { "model-id",
3457 .name = "Skylake-Client",
3493 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3544 .alias = "Skylake-Client-IBRS",
3546 { "spec-ctrl", "on" },
3547 { "model-id",
3554 .alias = "Skylake-Client-noTSX-IBRS",
3558 { "model-id",
3568 { "vmx-xsaves", "on" },
3576 .name = "Skylake-Server",
3617 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3670 .alias = "Skylake-Server-IBRS",
3672 /* clflushopt was not added to Skylake-Server-IBRS */
3673 /* TODO: add -v3 including clflushopt */
3675 { "spec-ctrl", "on" },
3676 { "model-id",
3683 .alias = "Skylake-Server-noTSX-IBRS",
3687 { "model-id",
3696 { "vmx-eptp-switching", "on" },
3705 { "vmx-xsaves", "on" },
3713 .name = "Cascadelake-Server",
3757 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3811 { "arch-capabilities", "on" },
3812 { "rdctl-no", "on" },
3813 { "ibrs-all", "on" },
3814 { "skip-l1dfl-vmentry", "on" },
3815 { "mds-no", "on" },
3820 .alias = "Cascadelake-Server-noTSX",
3831 { "vmx-eptp-switching", "on" },
3839 { "vmx-xsaves", "on" },
3898 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3954 { "vmx-xsaves", "on" },
3962 .name = "Icelake-Server",
4011 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4064 .alias = "Icelake-Server-noTSX",
4074 { "arch-capabilities", "on" },
4075 { "rdctl-no", "on" },
4076 { "ibrs-all", "on" },
4077 { "skip-l1dfl-vmentry", "on" },
4078 { "mds-no", "on" },
4079 { "pschange-mc-no", "on" },
4080 { "taa-no", "on" },
4087 { "sha-ni", "on" },
4091 { "vmx-rdseed-exit", "on" },
4092 { "vmx-pml", "on" },
4093 { "vmx-eptp-switching", "on" },
4103 { "vmx-xsaves", "on" },
4109 .note = "5-level EPT",
4111 { "vmx-page-walk-5", "on" },
4117 .note = "TSX, taa-no",
4119 /* Restore TSX features removed by -v2 above */
4257 { "sbdr-ssdp-no", "on" },
4258 { "fbsdp-no", "on" },
4259 { "psdp-no", "on" },
4267 { "tsc-adjust", "on" },
4414 { "tsc-adjust", "on" },
4419 { "avx10-128", "on" },
4420 { "avx10-256", "on" },
4421 { "avx10-512", "on" },
4422 { "avx10-version", "1" },
4659 { "vmx-xsaves", "on" },
4782 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
4791 { "vmx-xsaves", "on" },
4797 .note = "no split lock detect, no core-capability",
4799 { "split-lock-detect", "off" },
4800 { "core-capability", "off" },
5027 .alias = "EPYC-IBPB",
5030 { "model-id",
5039 { "perfctr-core", "on" },
5043 { "model-id",
5051 { "model-id",
5052 "AMD EPYC-v4 Processor" },
5118 .name = "EPYC-Rome",
5164 .model_id = "AMD EPYC-Rome Processor",
5172 { "amd-ssbd", "on" },
5179 { "model-id",
5180 "AMD EPYC-Rome-v3 Processor" },
5189 { "model-id",
5190 "AMD EPYC-Rome-v4 Processor (no XSAVES)" },
5199 .name = "EPYC-Milan",
5250 .model_id = "AMD EPYC-Milan Processor",
5257 { "model-id",
5258 "AMD EPYC-Milan-v2 Processor" },
5261 { "stibp-always-on", "on" },
5262 { "amd-psfd", "on" },
5263 { "no-nested-data-bp", "on" },
5264 { "lfence-always-serializing", "on" },
5265 { "null-sel-clr-base", "on" },
5274 .name = "EPYC-Genoa",
5342 .model_id = "AMD EPYC-Genoa Processor",
5348 * We resolve CPU model aliases using -v1 when using "-machine
5367 x86_cpu_def_get_versions(model->cpudef); in x86_cpu_model_last_version()
5368 while (vdef->version) { in x86_cpu_model_last_version()
5369 v = vdef->version; in x86_cpu_model_last_version()
5378 X86CPUVersion v = model->version; in x86_cpu_model_resolve_version()
5390 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
5399 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { in max_x86_cpu_realize()
5418 xcc->ordering = 9; in max_x86_cpu_class_init()
5420 xcc->model_description = in max_x86_cpu_class_init()
5424 dc->realize = max_x86_cpu_realize; in max_x86_cpu_class_init()
5434 cpu->max_features = true; in max_x86_cpu_initfn()
5443 object_property_set_str(OBJECT(cpu), "model-id", in max_x86_cpu_initfn()
5457 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); in feature_word_description()
5459 switch (f->type) { in feature_word_description()
5462 const char *reg = get_register_name_32(f->cpuid.reg); in feature_word_description()
5465 f->cpuid.eax, reg); in feature_word_description()
5469 f->msr.index); in feature_word_description()
5480 if (cpu->filtered_features[w]) { in x86_cpu_have_filtered_features()
5491 CPUX86State *env = &cpu->env; in mark_unavailable_features()
5495 if (!cpu->force_features) { in mark_unavailable_features()
5496 env->features[w] &= ~mask; in mark_unavailable_features()
5498 cpu->filtered_features[w] |= mask; in mark_unavailable_features()
5510 f->feat_names[i] ? "." : "", in mark_unavailable_features()
5511 f->feat_names[i] ? f->feat_names[i] : "", i); in mark_unavailable_features()
5521 CPUX86State *env = &cpu->env; in x86_cpuid_version_get_family()
5524 value = (env->cpuid_version >> 8) & 0xf; in x86_cpuid_version_get_family()
5526 value += (env->cpuid_version >> 20) & 0xff; in x86_cpuid_version_get_family()
5536 CPUX86State *env = &cpu->env; in x86_cpuid_version_set_family()
5549 env->cpuid_version &= ~0xff00f00; in x86_cpuid_version_set_family()
5551 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); in x86_cpuid_version_set_family()
5553 env->cpuid_version |= value << 8; in x86_cpuid_version_set_family()
5562 CPUX86State *env = &cpu->env; in x86_cpuid_version_get_model()
5565 value = (env->cpuid_version >> 4) & 0xf; in x86_cpuid_version_get_model()
5566 value |= ((env->cpuid_version >> 16) & 0xf) << 4; in x86_cpuid_version_get_model()
5575 CPUX86State *env = &cpu->env; in x86_cpuid_version_set_model()
5588 env->cpuid_version &= ~0xf00f0; in x86_cpuid_version_set_model()
5589 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); in x86_cpuid_version_set_model()
5597 CPUX86State *env = &cpu->env; in x86_cpuid_version_get_stepping()
5600 value = env->cpuid_version & 0xf; in x86_cpuid_version_get_stepping()
5609 CPUX86State *env = &cpu->env; in x86_cpuid_version_set_stepping()
5622 env->cpuid_version &= ~0xf; in x86_cpuid_version_set_stepping()
5623 env->cpuid_version |= value & 0xf; in x86_cpuid_version_set_stepping()
5629 CPUX86State *env = &cpu->env; in x86_cpuid_get_vendor()
5633 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, in x86_cpuid_get_vendor()
5634 env->cpuid_vendor3); in x86_cpuid_get_vendor()
5642 CPUX86State *env = &cpu->env; in x86_cpuid_set_vendor()
5651 env->cpuid_vendor1 = 0; in x86_cpuid_set_vendor()
5652 env->cpuid_vendor2 = 0; in x86_cpuid_set_vendor()
5653 env->cpuid_vendor3 = 0; in x86_cpuid_set_vendor()
5655 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); in x86_cpuid_set_vendor()
5656 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); in x86_cpuid_set_vendor()
5657 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); in x86_cpuid_set_vendor()
5664 CPUX86State *env = &cpu->env; in x86_cpuid_get_model_id()
5670 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); in x86_cpuid_get_model_id()
5680 CPUX86State *env = &cpu->env; in x86_cpuid_set_model_id()
5687 memset(env->cpuid_model, 0, 48); in x86_cpuid_set_model_id()
5694 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); in x86_cpuid_set_model_id()
5704 value = cpu->env.tsc_khz * 1000; in x86_cpuid_get_tsc_freq()
5724 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; in x86_cpuid_set_tsc_freq()
5727 /* Generic getter for "feature-words" and "filtered-features" properties */
5741 * We didn't have MSR features when "feature-words" was in x86_cpu_get_feature_words()
5744 if (wi->type != CPUID_FEATURE_WORD) { in x86_cpu_get_feature_words()
5748 qwi->cpuid_input_eax = wi->cpuid.eax; in x86_cpu_get_feature_words()
5749 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; in x86_cpu_get_feature_words()
5750 qwi->cpuid_input_ecx = wi->cpuid.ecx; in x86_cpu_get_feature_words()
5751 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; in x86_cpu_get_feature_words()
5752 qwi->features = array[w]; in x86_cpu_get_feature_words()
5760 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); in x86_cpu_get_feature_words()
5763 /* Convert all '_' in a feature string option name to '-', to make feature
5764 * name conform to QOM property naming rule, which uses '-' instead of '_'.
5769 *s = '-'; in feat2prop()
5797 /* Compatibility hack to maintain legacy +-feat semantic,
5798 * where +-feat overwrites any feature set by
5799 * feat=on|feat even if the later is parsed after +-feat
5800 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
5809 /* Parse "+feature,-feature,feature=foo" CPU feature string
5841 } else if (featurestr[0] == '-') { in x86_cpu_parse_featurestr()
5866 "Don't mix both \"-%s\" and \"%s=%s\"", in x86_cpu_parse_featurestr()
5872 if (!strcmp(name, "tsc-freq")) { in x86_cpu_parse_featurestr()
5883 name = "tsc-frequency"; in x86_cpu_parse_featurestr()
5887 prop->driver = typename; in x86_cpu_parse_featurestr()
5888 prop->property = g_strdup(name); in x86_cpu_parse_featurestr()
5889 prop->value = g_strdup(val); in x86_cpu_parse_featurestr()
5926 x86_cpu_list_feature_names(xc->filtered_features, &result); in x86_cpu_get_unavailable_features()
5927 visit_type_strList(v, "unavailable-features", &result, errp); in x86_cpu_get_unavailable_features()
5937 for (tmp = features; tmp; tmp = tmp->next) { in listflags()
5938 const char *name = tmp->data; in listflags()
5958 if (cc_a->ordering != cc_b->ordering) { in x86_cpu_list_compare()
5959 ret = cc_a->ordering - cc_b->ordering; in x86_cpu_list_compare()
5978 char *r = object_property_get_str(obj, "model-id", &error_abort); in x86_cpu_class_get_model_id()
5987 if (!cc->model || !cc->model->is_alias) { in x86_cpu_class_get_alias_of()
5990 version = x86_cpu_model_resolve_version(cc->model); in x86_cpu_class_get_alias_of()
5994 return x86_cpu_versioned_model_name(cc->model->cpudef, version); in x86_cpu_class_get_alias_of()
6002 g_autofree char *desc = g_strdup(cc->model_description); in x86_cpu_list_entry()
6007 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { in x86_cpu_list_entry()
6013 if (!desc && cc->model && cc->model->note) { in x86_cpu_list_entry()
6014 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); in x86_cpu_list_entry()
6020 if (cc->model && cc->model->cpudef->deprecation_note) { in x86_cpu_list_entry()
6025 qemu_printf(" %-20s %s\n", name, desc); in x86_cpu_list_entry()
6044 if (fw->feat_names[j]) { in x86_cpu_list()
6045 names = g_list_append(names, (gpointer)fw->feat_names[j]); in x86_cpu_list()
6070 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { in x86_cpu_class_check_missing_features()
6089 x86_cpu_list_feature_names(xc->filtered_features, tail); in x86_cpu_class_check_missing_features()
6102 info->name = x86_cpu_class_get_model_name(cc); in x86_cpu_definition_entry()
6103 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); in x86_cpu_definition_entry()
6104 info->has_unavailable_features = true; in x86_cpu_definition_entry()
6105 info->q_typename = g_strdup(object_class_get_name(oc)); in x86_cpu_definition_entry()
6106 info->migration_safe = cc->migration_safe; in x86_cpu_definition_entry()
6107 info->has_migration_safe = true; in x86_cpu_definition_entry()
6108 info->q_static = cc->static_model; in x86_cpu_definition_entry()
6109 if (cc->model && cc->model->cpudef->deprecation_note) { in x86_cpu_definition_entry()
6110 info->deprecated = true; in x86_cpu_definition_entry()
6112 info->deprecated = false; in x86_cpu_definition_entry()
6119 info->alias_of = x86_cpu_class_get_alias_of(cc); in x86_cpu_definition_entry()
6143 switch (wi->type) { in x86_cpu_get_supported_feature_word()
6145 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, in x86_cpu_get_supported_feature_word()
6146 wi->cpuid.ecx, in x86_cpu_get_supported_feature_word()
6147 wi->cpuid.reg); in x86_cpu_get_supported_feature_word()
6151 wi->msr.index); in x86_cpu_get_supported_feature_word()
6155 if (wi->type != CPUID_FEATURE_WORD) { in x86_cpu_get_supported_feature_word()
6158 r = hvf_get_supported_cpuid(wi->cpuid.eax, in x86_cpu_get_supported_feature_word()
6159 wi->cpuid.ecx, in x86_cpu_get_supported_feature_word()
6160 wi->cpuid.reg); in x86_cpu_get_supported_feature_word()
6162 r = wi->tcg_features; in x86_cpu_get_supported_feature_word()
6171 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no in x86_cpu_get_supported_feature_word()
6172 * way for userspace to get out of its 32-bit jail, we can leave in x86_cpu_get_supported_feature_word()
6182 if (cpu && !IS_AMD_CPU(&cpu->env)) { in x86_cpu_get_supported_feature_word()
6208 if (cpu && cpu->migratable) { in x86_cpu_get_supported_feature_word()
6273 for (pv = props; pv->prop; pv++) { in x86_cpu_apply_props()
6274 if (!pv->value) { in x86_cpu_apply_props()
6277 object_property_parse(OBJECT(cpu), pv->prop, pv->value, in x86_cpu_apply_props()
6296 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { in x86_cpu_apply_version_props()
6299 for (p = vdef->props; p && p->prop; p++) { in x86_cpu_apply_version_props()
6300 object_property_parse(OBJECT(cpu), p->prop, p->value, in x86_cpu_apply_version_props()
6304 if (vdef->version == version) { in x86_cpu_apply_version_props()
6312 assert(vdef->version == version); in x86_cpu_apply_version_props()
6320 const CPUCaches *cache_info = model->cpudef->cache_info; in x86_cpu_get_versioned_cache_info()
6326 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { in x86_cpu_get_versioned_cache_info()
6327 if (vdef->cache_info) { in x86_cpu_get_versioned_cache_info()
6328 cache_info = vdef->cache_info; in x86_cpu_get_versioned_cache_info()
6331 if (vdef->version == version) { in x86_cpu_get_versioned_cache_info()
6336 assert(vdef->version == version); in x86_cpu_get_versioned_cache_info()
6346 const X86CPUDefinition *def = model->cpudef; in x86_cpu_load_model()
6347 CPUX86State *env = &cpu->env; in x86_cpu_load_model()
6352 * query-cpu-model-expansion is always complete. in x86_cpu_load_model()
6356 object_property_set_uint(OBJECT(cpu), "min-level", def->level, in x86_cpu_load_model()
6358 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, in x86_cpu_load_model()
6361 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); in x86_cpu_load_model()
6362 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); in x86_cpu_load_model()
6363 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, in x86_cpu_load_model()
6365 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, in x86_cpu_load_model()
6368 env->features[w] = def->features[w]; in x86_cpu_load_model()
6371 /* legacy-cache defaults to 'off' if CPU model provides cache info */ in x86_cpu_load_model()
6372 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); in x86_cpu_load_model()
6374 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; in x86_cpu_load_model()
6376 /* sysenter isn't supported in compatibility mode on AMD, in x86_cpu_load_model()
6377 * syscall isn't supported in compatibility mode on Intel. in x86_cpu_load_model()
6380 * KVM's sysenter/syscall emulation in compatibility mode and in x86_cpu_load_model()
6388 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); in x86_cpu_load_model()
6390 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, in x86_cpu_load_model()
6397 * We can simply clear env->user_features here since it will be filled later in x86_cpu_load_model()
6400 memset(&env->user_features, 0, sizeof(env->user_features)); in x86_cpu_load_model()
6406 return "i386:x86-64"; in x86_gdb_arch_name()
6418 xcc->model = model; in x86_cpu_cpudef_class_init()
6419 xcc->migration_safe = true; in x86_cpu_cpudef_class_init()
6420 cc->deprecation_note = model->cpudef->deprecation_note; in x86_cpu_cpudef_class_init()
6450 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); in x86_register_cpudef_types()
6452 assert(def->model_id && strlen(def->model_id) <= 48); in x86_register_cpudef_types()
6456 m->cpudef = def; in x86_register_cpudef_types()
6457 m->version = CPU_VERSION_AUTO; in x86_register_cpudef_types()
6458 m->is_alias = true; in x86_register_cpudef_types()
6459 x86_register_cpu_model_type(def->name, m); in x86_register_cpudef_types()
6463 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { in x86_register_cpudef_types()
6465 x86_cpu_versioned_model_name(def, vdef->version); in x86_register_cpudef_types()
6468 m->cpudef = def; in x86_register_cpudef_types()
6469 m->version = vdef->version; in x86_register_cpudef_types()
6470 m->note = vdef->note; in x86_register_cpudef_types()
6473 if (vdef->alias) { in x86_register_cpudef_types()
6475 am->cpudef = def; in x86_register_cpudef_types()
6476 am->version = vdef->version; in x86_register_cpudef_types()
6477 am->is_alias = true; in x86_register_cpudef_types()
6478 x86_register_cpu_model_type(vdef->alias, am); in x86_register_cpudef_types()
6486 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { in cpu_x86_virtual_addr_width()
6505 topo_info.dies_per_pkg = env->nr_dies; in cpu_x86_cpuid()
6506 topo_info.modules_per_die = env->nr_modules; in cpu_x86_cpuid()
6507 topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; in cpu_x86_cpuid()
6508 topo_info.threads_per_core = cs->nr_threads; in cpu_x86_cpuid()
6516 limit = env->cpuid_xlevel2; in cpu_x86_cpuid()
6518 limit = env->cpuid_xlevel; in cpu_x86_cpuid()
6522 limit = env->cpuid_level; in cpu_x86_cpuid()
6528 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) in cpu_x86_cpuid()
6530 index = env->cpuid_level; in cpu_x86_cpuid()
6535 *eax = env->cpuid_level; in cpu_x86_cpuid()
6536 *ebx = env->cpuid_vendor1; in cpu_x86_cpuid()
6537 *edx = env->cpuid_vendor2; in cpu_x86_cpuid()
6538 *ecx = env->cpuid_vendor3; in cpu_x86_cpuid()
6541 *eax = env->cpuid_version; in cpu_x86_cpuid()
6542 *ebx = (cpu->apic_id << 24) | in cpu_x86_cpuid()
6544 *ecx = env->features[FEAT_1_ECX]; in cpu_x86_cpuid()
6545 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { in cpu_x86_cpuid()
6548 *edx = env->features[FEAT_1_EDX]; in cpu_x86_cpuid()
6553 if (!cpu->enable_pmu) { in cpu_x86_cpuid()
6559 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
6562 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { in cpu_x86_cpuid()
6568 if (!cpu->enable_l3_cache) { in cpu_x86_cpuid()
6571 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); in cpu_x86_cpuid()
6573 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | in cpu_x86_cpuid()
6574 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | in cpu_x86_cpuid()
6575 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); in cpu_x86_cpuid()
6579 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
6598 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { in cpu_x86_cpuid()
6605 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, in cpu_x86_cpuid()
6608 if (!cpu->l1_cache_per_core) { in cpu_x86_cpuid()
6613 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, in cpu_x86_cpuid()
6616 if (!cpu->l1_cache_per_core) { in cpu_x86_cpuid()
6621 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, in cpu_x86_cpuid()
6626 if (cpu->enable_l3_cache) { in cpu_x86_cpuid()
6627 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, in cpu_x86_cpuid()
6641 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ in cpu_x86_cpuid()
6642 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ in cpu_x86_cpuid()
6643 *ecx = cpu->mwait.ecx; /* flags */ in cpu_x86_cpuid()
6644 *edx = cpu->mwait.edx; /* mwait substates */ in cpu_x86_cpuid()
6648 *eax = env->features[FEAT_6_EAX]; in cpu_x86_cpuid()
6656 /* Maximum ECX value for sub-leaves */ in cpu_x86_cpuid()
6657 *eax = env->cpuid_level_func7; in cpu_x86_cpuid()
6658 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ in cpu_x86_cpuid()
6659 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ in cpu_x86_cpuid()
6660 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { in cpu_x86_cpuid()
6663 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ in cpu_x86_cpuid()
6665 *eax = env->features[FEAT_7_1_EAX]; in cpu_x86_cpuid()
6666 *edx = env->features[FEAT_7_1_EDX]; in cpu_x86_cpuid()
6670 *edx = env->features[FEAT_7_2_EDX]; in cpu_x86_cpuid()
6683 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ in cpu_x86_cpuid()
6690 if (cpu->enable_pmu) { in cpu_x86_cpuid()
6701 if (!cpu->enable_cpuid_0xb) { in cpu_x86_cpuid()
6707 *edx = cpu->apic_id; in cpu_x86_cpuid()
6730 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { in cpu_x86_cpuid()
6737 if (!x86_has_extended_topo(env->avail_cpu_topo)) { in cpu_x86_cpuid()
6750 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { in cpu_x86_cpuid()
6756 *eax = env->features[FEAT_XSAVE_XCR0_LO]; in cpu_x86_cpuid()
6757 *edx = env->features[FEAT_XSAVE_XCR0_HI]; in cpu_x86_cpuid()
6764 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); in cpu_x86_cpuid()
6769 *eax = env->features[FEAT_XSAVE]; in cpu_x86_cpuid()
6771 *ecx = env->features[FEAT_XSAVE_XSS_LO]; in cpu_x86_cpuid()
6772 *edx = env->features[FEAT_XSAVE_XSS_HI]; in cpu_x86_cpuid()
6773 if (kvm_enabled() && cpu->enable_pmu && in cpu_x86_cpuid()
6774 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && in cpu_x86_cpuid()
6780 } else if (count == 0xf && cpu->enable_pmu in cpu_x86_cpuid()
6781 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { in cpu_x86_cpuid()
6787 *eax = esa->size; in cpu_x86_cpuid()
6788 *ebx = esa->offset; in cpu_x86_cpuid()
6789 *ecx = esa->ecx & in cpu_x86_cpuid()
6792 *eax = esa->size; in cpu_x86_cpuid()
6802 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { in cpu_x86_cpuid()
6808 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve in cpu_x86_cpuid()
6816 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { in cpu_x86_cpuid()
6829 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware in cpu_x86_cpuid()
6837 *eax &= env->features[FEAT_SGX_12_0_EAX]; in cpu_x86_cpuid()
6838 *ebx &= env->features[FEAT_SGX_12_0_EBX]; in cpu_x86_cpuid()
6840 *eax &= env->features[FEAT_SGX_12_1_EAX]; in cpu_x86_cpuid()
6842 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; in cpu_x86_cpuid()
6843 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; in cpu_x86_cpuid()
6850 !kvm_enable_sgx_provisioning(cs->kvm_state)) { in cpu_x86_cpuid()
6862 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || in cpu_x86_cpuid()
6875 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { in cpu_x86_cpuid()
6890 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { in cpu_x86_cpuid()
6911 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { in cpu_x86_cpuid()
6926 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { in cpu_x86_cpuid()
6927 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; in cpu_x86_cpuid()
6936 if (tcg_enabled() && cpu->expose_tcg) { in cpu_x86_cpuid()
6956 *eax = env->cpuid_xlevel; in cpu_x86_cpuid()
6957 *ebx = env->cpuid_vendor1; in cpu_x86_cpuid()
6958 *edx = env->cpuid_vendor2; in cpu_x86_cpuid()
6959 *ecx = env->cpuid_vendor3; in cpu_x86_cpuid()
6962 *eax = env->cpuid_version; in cpu_x86_cpuid()
6964 *ecx = env->features[FEAT_8000_0001_ECX]; in cpu_x86_cpuid()
6965 *edx = env->features[FEAT_8000_0001_EDX]; in cpu_x86_cpuid()
6972 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || in cpu_x86_cpuid()
6973 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || in cpu_x86_cpuid()
6974 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { in cpu_x86_cpuid()
6978 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && in cpu_x86_cpuid()
6979 !(env->hflags & HF_LMA_MASK)) { in cpu_x86_cpuid()
6986 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; in cpu_x86_cpuid()
6987 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; in cpu_x86_cpuid()
6988 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; in cpu_x86_cpuid()
6989 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; in cpu_x86_cpuid()
6993 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
7001 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); in cpu_x86_cpuid()
7002 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); in cpu_x86_cpuid()
7006 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
7018 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, in cpu_x86_cpuid()
7019 cpu->enable_l3_cache ? in cpu_x86_cpuid()
7020 env->cache_info_amd.l3_cache : NULL, in cpu_x86_cpuid()
7025 *ebx = env->features[FEAT_8000_0007_EBX]; in cpu_x86_cpuid()
7027 *edx = env->features[FEAT_8000_0007_EDX]; in cpu_x86_cpuid()
7031 *eax = cpu->phys_bits; in cpu_x86_cpuid()
7032 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { in cpu_x86_cpuid()
7035 *eax |= (cpu->guest_phys_bits << 16); in cpu_x86_cpuid()
7037 *ebx = env->features[FEAT_8000_0008_EBX]; in cpu_x86_cpuid()
7046 (threads_per_pkg - 1); in cpu_x86_cpuid()
7053 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { in cpu_x86_cpuid()
7057 *edx = env->features[FEAT_SVM]; /* optional features */ in cpu_x86_cpuid()
7067 if (cpu->cache_info_passthrough) { in cpu_x86_cpuid()
7073 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, in cpu_x86_cpuid()
7077 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, in cpu_x86_cpuid()
7081 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, in cpu_x86_cpuid()
7085 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, in cpu_x86_cpuid()
7092 if (cpu->amd_topoext_features_only) { in cpu_x86_cpuid()
7097 if (cpu->core_id <= 255) { in cpu_x86_cpuid()
7109 if (kvm_enabled() && cpu->enable_pmu && in cpu_x86_cpuid()
7110 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { in cpu_x86_cpuid()
7112 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, in cpu_x86_cpuid()
7117 *eax = env->cpuid_xlevel2; in cpu_x86_cpuid()
7124 *eax = env->cpuid_version; in cpu_x86_cpuid()
7127 *edx = env->features[FEAT_C000_0001_EDX]; in cpu_x86_cpuid()
7150 *eax = env->features[FEAT_8000_0021_EAX]; in cpu_x86_cpuid()
7151 *ebx = env->features[FEAT_8000_0021_EBX]; in cpu_x86_cpuid()
7167 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; in x86_cpu_set_sgxlepubkeyhash()
7168 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; in x86_cpu_set_sgxlepubkeyhash()
7169 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; in x86_cpu_set_sgxlepubkeyhash()
7170 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; in x86_cpu_set_sgxlepubkeyhash()
7176 if (!esa->size) { in cpuid_has_xsave_feature()
7180 if (env->features[esa->feature] & esa->bits) { in cpuid_has_xsave_feature()
7183 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F in cpuid_has_xsave_feature()
7184 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { in cpuid_has_xsave_feature()
7196 CPUX86State *env = &cpu->env; in x86_cpu_reset_hold()
7201 if (xcc->parent_phases.hold) { in x86_cpu_reset_hold()
7202 xcc->parent_phases.hold(obj, type); in x86_cpu_reset_hold()
7211 env->old_exception = -1; in x86_cpu_reset_hold()
7214 env->int_ctl = 0; in x86_cpu_reset_hold()
7215 env->hflags2 |= HF2_GIF_MASK; in x86_cpu_reset_hold()
7216 env->hflags2 |= HF2_VGIF_MASK; in x86_cpu_reset_hold()
7217 env->hflags &= ~HF_GUEST_MASK; in x86_cpu_reset_hold()
7220 env->a20_mask = ~0x0; in x86_cpu_reset_hold()
7221 env->smbase = 0x30000; in x86_cpu_reset_hold()
7222 env->msr_smi_count = 0; in x86_cpu_reset_hold()
7224 env->idt.limit = 0xffff; in x86_cpu_reset_hold()
7225 env->gdt.limit = 0xffff; in x86_cpu_reset_hold()
7226 env->ldt.limit = 0xffff; in x86_cpu_reset_hold()
7227 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); in x86_cpu_reset_hold()
7228 env->tr.limit = 0xffff; in x86_cpu_reset_hold()
7229 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); in x86_cpu_reset_hold()
7250 env->eip = 0xfff0; in x86_cpu_reset_hold()
7251 env->regs[R_EDX] = env->cpuid_version; in x86_cpu_reset_hold()
7253 env->eflags = 0x2; in x86_cpu_reset_hold()
7257 env->fptags[i] = 1; in x86_cpu_reset_hold()
7261 env->mxcsr = 0x1f80; in x86_cpu_reset_hold()
7263 env->xstate_bv = 0; in x86_cpu_reset_hold()
7265 env->pat = 0x0007040600070406ULL; in x86_cpu_reset_hold()
7269 * KVM handles TSC = 0 specially and thinks we are hot-plugging in x86_cpu_reset_hold()
7272 if (env->tsc != 0) { in x86_cpu_reset_hold()
7273 env->tsc = 1; in x86_cpu_reset_hold()
7276 env->tsc = 0; in x86_cpu_reset_hold()
7279 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; in x86_cpu_reset_hold()
7280 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { in x86_cpu_reset_hold()
7281 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; in x86_cpu_reset_hold()
7284 memset(env->dr, 0, sizeof(env->dr)); in x86_cpu_reset_hold()
7285 env->dr[6] = DR6_FIXED_1; in x86_cpu_reset_hold()
7286 env->dr[7] = DR7_FIXED_1; in x86_cpu_reset_hold()
7294 /* Enable all the features for user-mode. */ in x86_cpu_reset_hold()
7295 if (env->features[FEAT_1_EDX] & CPUID_SSE) { in x86_cpu_reset_hold()
7308 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { in x86_cpu_reset_hold()
7311 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { in x86_cpu_reset_hold()
7316 env->xcr0 = xcr0; in x86_cpu_reset_hold()
7321 * - IA32_MTRR_DEF_TYPE MSR.E = 0 in x86_cpu_reset_hold()
7322 * - IA32_MTRR_PHYSMASKn.V = 0 in x86_cpu_reset_hold()
7325 env->mtrr_deftype = 0; in x86_cpu_reset_hold()
7326 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); in x86_cpu_reset_hold()
7327 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); in x86_cpu_reset_hold()
7329 env->interrupt_injected = -1; in x86_cpu_reset_hold()
7330 env->exception_nr = -1; in x86_cpu_reset_hold()
7331 env->exception_pending = 0; in x86_cpu_reset_hold()
7332 env->exception_injected = 0; in x86_cpu_reset_hold()
7333 env->exception_has_payload = false; in x86_cpu_reset_hold()
7334 env->exception_payload = 0; in x86_cpu_reset_hold()
7335 env->nmi_injected = false; in x86_cpu_reset_hold()
7336 env->triple_fault_pending = false; in x86_cpu_reset_hold()
7338 /* We hard-wire the BSP to the first CPU. */ in x86_cpu_reset_hold()
7339 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); in x86_cpu_reset_hold()
7341 cs->halted = !cpu_is_bsp(cpu); in x86_cpu_reset_hold()
7349 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; in x86_cpu_reset_hold()
7361 if (cpu->apic_state) { in x86_cpu_after_reset()
7362 device_cold_reset(cpu->apic_state); in x86_cpu_after_reset()
7369 CPUX86State *cenv = &cpu->env; in mce_init()
7372 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 in mce_init()
7373 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == in mce_init()
7375 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | in mce_init()
7376 (cpu->enable_lmce ? MCG_LMCE_P : 0); in mce_init()
7377 cenv->mcg_ctl = ~(uint64_t)0; in mce_init()
7379 cenv->mce_banks[bank * 4] = ~(uint64_t)0; in mce_init()
7394 CPUX86State *env = &cpu->env; in x86_cpu_adjust_feat_level()
7396 uint32_t eax = fi->cpuid.eax; in x86_cpu_adjust_feat_level()
7400 if (!env->features[w]) { in x86_cpu_adjust_feat_level()
7406 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); in x86_cpu_adjust_feat_level()
7409 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); in x86_cpu_adjust_feat_level()
7412 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); in x86_cpu_adjust_feat_level()
7417 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, in x86_cpu_adjust_feat_level()
7418 fi->cpuid.ecx); in x86_cpu_adjust_feat_level()
7425 CPUX86State *env = &cpu->env; in x86_cpu_enable_xsave_components()
7430 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { in x86_cpu_enable_xsave_components()
7431 env->features[FEAT_XSAVE_XCR0_LO] = 0; in x86_cpu_enable_xsave_components()
7432 env->features[FEAT_XSAVE_XCR0_HI] = 0; in x86_cpu_enable_xsave_components()
7433 env->features[FEAT_XSAVE_XSS_LO] = 0; in x86_cpu_enable_xsave_components()
7434 env->features[FEAT_XSAVE_XSS_HI] = 0; in x86_cpu_enable_xsave_components()
7452 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; in x86_cpu_enable_xsave_components()
7453 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; in x86_cpu_enable_xsave_components()
7454 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; in x86_cpu_enable_xsave_components()
7455 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; in x86_cpu_enable_xsave_components()
7482 * - CPU instance creation (instance_init) will run only CPU
7483 * model loading. CPU expansion can't run at instance_init-time
7485 * - CPU realization will perform both CPU model expansion and CPUID
7487 * - query-cpu-definitions needs to run all 3 steps. It needs
7488 * to run CPUID filtering, as the 'unavailable-features'
7490 * - The query-cpu-model-expansion QMP command only needs to run
7500 CPUX86State *env = &cpu->env; in x86_cpu_expand_features()
7505 for (l = plus_features; l; l = l->next) { in x86_cpu_expand_features()
7506 const char *prop = l->data; in x86_cpu_expand_features()
7512 for (l = minus_features; l; l = l->next) { in x86_cpu_expand_features()
7513 const char *prop = l->data; in x86_cpu_expand_features()
7519 /*TODO: Now cpu->max_features doesn't overwrite features in x86_cpu_expand_features()
7524 if (cpu->max_features) { in x86_cpu_expand_features()
7529 env->features[w] |= in x86_cpu_expand_features()
7531 ~env->user_features[w] & in x86_cpu_expand_features()
7535 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { in x86_cpu_expand_features()
7538 env->avx10_version = ebx & 0xff; in x86_cpu_expand_features()
7544 if (!(env->features[d->from.index] & d->from.mask)) { in x86_cpu_expand_features()
7545 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; in x86_cpu_expand_features()
7548 mark_unavailable_features(cpu, d->to.index, in x86_cpu_expand_features()
7549 unavailable_features & env->user_features[d->to.index], in x86_cpu_expand_features()
7552 env->features[d->to.index] &= ~unavailable_features; in x86_cpu_expand_features()
7556 if (!kvm_enabled() || !cpu->expose_kvm) { in x86_cpu_expand_features()
7557 env->features[FEAT_KVM] = 0; in x86_cpu_expand_features()
7564 if (cpu->full_cpuid_auto_level) { in x86_cpu_expand_features()
7581 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { in x86_cpu_expand_features()
7582 if (cpu->intel_pt_auto_level) { in x86_cpu_expand_features()
7583 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); in x86_cpu_expand_features()
7584 } else if (cpu->env.cpuid_min_level < 0x14) { in x86_cpu_expand_features()
7587 … "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); in x86_cpu_expand_features()
7592 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. in x86_cpu_expand_features()
7595 * cpu->vendor_cpuid_only has been unset for compatibility with older in x86_cpu_expand_features()
7598 if (x86_has_extended_topo(env->avail_cpu_topo) && in x86_cpu_expand_features()
7599 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { in x86_cpu_expand_features()
7600 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); in x86_cpu_expand_features()
7604 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { in x86_cpu_expand_features()
7605 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); in x86_cpu_expand_features()
7609 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { in x86_cpu_expand_features()
7610 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); in x86_cpu_expand_features()
7615 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); in x86_cpu_expand_features()
7618 if (env->features[FEAT_8000_0021_EAX]) { in x86_cpu_expand_features()
7619 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); in x86_cpu_expand_features()
7623 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { in x86_cpu_expand_features()
7624 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); in x86_cpu_expand_features()
7629 if (env->cpuid_level_func7 == UINT32_MAX) { in x86_cpu_expand_features()
7630 env->cpuid_level_func7 = env->cpuid_min_level_func7; in x86_cpu_expand_features()
7632 if (env->cpuid_level == UINT32_MAX) { in x86_cpu_expand_features()
7633 env->cpuid_level = env->cpuid_min_level; in x86_cpu_expand_features()
7635 if (env->cpuid_xlevel == UINT32_MAX) { in x86_cpu_expand_features()
7636 env->cpuid_xlevel = env->cpuid_min_xlevel; in x86_cpu_expand_features()
7638 if (env->cpuid_xlevel2 == UINT32_MAX) { in x86_cpu_expand_features()
7639 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; in x86_cpu_expand_features()
7655 CPUX86State *env = &cpu->env; in x86_cpu_filter_features()
7672 uint64_t requested_features = env->features[w]; in x86_cpu_filter_features()
7681 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && in x86_cpu_filter_features()
7697 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { in x86_cpu_filter_features()
7701 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. in x86_cpu_filter_features()
7709 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { in x86_cpu_filter_features()
7714 if (version < env->avx10_version) { in x86_cpu_filter_features()
7717 prefix, env->avx10_version, version); in x86_cpu_filter_features()
7719 env->avx10_version = version; in x86_cpu_filter_features()
7722 } else if (env->avx10_version) { in x86_cpu_filter_features()
7724 warn_report("%s: avx10.%d.", prefix, env->avx10_version); in x86_cpu_filter_features()
7736 /* Hyper-V vendor id */ in x86_cpu_hyperv_realize()
7737 if (!cpu->hyperv_vendor) { in x86_cpu_hyperv_realize()
7738 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", in x86_cpu_hyperv_realize()
7741 len = strlen(cpu->hyperv_vendor); in x86_cpu_hyperv_realize()
7743 warn_report("hv-vendor-id truncated to 12 characters"); in x86_cpu_hyperv_realize()
7746 memset(cpu->hyperv_vendor_id, 0, 12); in x86_cpu_hyperv_realize()
7747 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); in x86_cpu_hyperv_realize()
7750 cpu->hyperv_interface_id[0] = 0x31237648; in x86_cpu_hyperv_realize()
7751 cpu->hyperv_interface_id[1] = 0; in x86_cpu_hyperv_realize()
7752 cpu->hyperv_interface_id[2] = 0; in x86_cpu_hyperv_realize()
7753 cpu->hyperv_interface_id[3] = 0; in x86_cpu_hyperv_realize()
7756 cpu->hyperv_limits[0] = 64; in x86_cpu_hyperv_realize()
7757 cpu->hyperv_limits[1] = 0; in x86_cpu_hyperv_realize()
7758 cpu->hyperv_limits[2] = 0; in x86_cpu_hyperv_realize()
7766 CPUX86State *env = &cpu->env; in x86_cpu_realizefn()
7771 /* Use pc-relative instructions in system-mode */ in x86_cpu_realizefn()
7775 if (cpu->apic_id == UNASSIGNED_APIC_ID) { in x86_cpu_realizefn()
7776 error_setg(errp, "apic-id property was not initialized properly"); in x86_cpu_realizefn()
7781 * Process Hyper-V enlightenments. in x86_cpu_realizefn()
7792 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT in x86_cpu_realizefn()
7793 * with user-provided setting. in x86_cpu_realizefn()
7795 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { in x86_cpu_realizefn()
7796 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { in x86_cpu_realizefn()
7797 error_setg(errp, "invalid lbr-fmt"); in x86_cpu_realizefn()
7800 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; in x86_cpu_realizefn()
7801 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; in x86_cpu_realizefn()
7809 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; in x86_cpu_realizefn()
7815 if (!cpu->enable_pmu) { in x86_cpu_realizefn()
7820 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " in x86_cpu_realizefn()
7827 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { in x86_cpu_realizefn()
7828 if (cpu->enforce_cpuid) { in x86_cpu_realizefn()
7841 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; in x86_cpu_realizefn()
7842 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] in x86_cpu_realizefn()
7851 * These may be set by the accel-specific code, in x86_cpu_realizefn()
7860 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { in x86_cpu_realizefn()
7866 if (cpu->guest_phys_bits == -1) { in x86_cpu_realizefn()
7871 cpu->guest_phys_bits = 0; in x86_cpu_realizefn()
7874 if (cpu->ucode_rev == 0) { in x86_cpu_realizefn()
7878 * accel-specific code in cpu_exec_realizefn. in x86_cpu_realizefn()
7881 cpu->ucode_rev = 0x01000065; in x86_cpu_realizefn()
7883 cpu->ucode_rev = 0x100000000ULL; in x86_cpu_realizefn()
7891 * requires the accel-specific code in cpu_exec_realizefn to in x86_cpu_realizefn()
7892 * have already acquired the CPUID data into cpu->mwait. in x86_cpu_realizefn()
7894 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; in x86_cpu_realizefn()
7905 * accel-specific code in cpu_exec_realizefn. in x86_cpu_realizefn()
7907 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { in x86_cpu_realizefn()
7908 if (cpu->phys_bits && in x86_cpu_realizefn()
7909 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || in x86_cpu_realizefn()
7910 cpu->phys_bits < 32)) { in x86_cpu_realizefn()
7911 error_setg(errp, "phys-bits should be between 32 and %u " in x86_cpu_realizefn()
7913 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); in x86_cpu_realizefn()
7918 * compat_props or by the host code in host-cpu.c). in x86_cpu_realizefn()
7921 if (cpu->phys_bits == 0) { in x86_cpu_realizefn()
7922 cpu->phys_bits = TCG_PHYS_ADDR_BITS; in x86_cpu_realizefn()
7924 if (cpu->guest_phys_bits && in x86_cpu_realizefn()
7925 (cpu->guest_phys_bits > cpu->phys_bits || in x86_cpu_realizefn()
7926 cpu->guest_phys_bits < 32)) { in x86_cpu_realizefn()
7927 error_setg(errp, "guest-phys-bits should be between 32 and %u " in x86_cpu_realizefn()
7929 cpu->phys_bits, cpu->guest_phys_bits); in x86_cpu_realizefn()
7936 if (cpu->phys_bits != 0) { in x86_cpu_realizefn()
7937 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); in x86_cpu_realizefn()
7940 if (cpu->guest_phys_bits != 0) { in x86_cpu_realizefn()
7941 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); in x86_cpu_realizefn()
7945 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { in x86_cpu_realizefn()
7946 cpu->phys_bits = 36; in x86_cpu_realizefn()
7948 cpu->phys_bits = 32; in x86_cpu_realizefn()
7953 if (!cpu->legacy_cache) { in x86_cpu_realizefn()
7955 x86_cpu_get_versioned_cache_info(cpu, xcc->model); in x86_cpu_realizefn()
7957 if (!xcc->model || !cache_info) { in x86_cpu_realizefn()
7960 "CPU model '%s' doesn't support legacy-cache=off", name); in x86_cpu_realizefn()
7963 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = in x86_cpu_realizefn()
7967 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; in x86_cpu_realizefn()
7968 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; in x86_cpu_realizefn()
7969 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; in x86_cpu_realizefn()
7970 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; in x86_cpu_realizefn()
7972 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; in x86_cpu_realizefn()
7973 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; in x86_cpu_realizefn()
7974 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; in x86_cpu_realizefn()
7975 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; in x86_cpu_realizefn()
7977 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; in x86_cpu_realizefn()
7978 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; in x86_cpu_realizefn()
7979 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; in x86_cpu_realizefn()
7980 env->cache_info_amd.l3_cache = &legacy_l3_cache; in x86_cpu_realizefn()
7987 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { in x86_cpu_realizefn()
8007 * cs->nr_threads hasn't be populated yet and the checking is incorrect. in x86_cpu_realizefn()
8010 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && in x86_cpu_realizefn()
8011 cs->nr_threads > 1) { in x86_cpu_realizefn()
8013 "hyperthreading(%d). Please configure -smp " in x86_cpu_realizefn()
8015 "feature.", cs->nr_threads); in x86_cpu_realizefn()
8026 xcc->parent_realize(dev, &local_err); in x86_cpu_realizefn()
8045 if (cpu->apic_state) { in x86_cpu_unrealizefn()
8046 object_unparent(OBJECT(cpu->apic_state)); in x86_cpu_unrealizefn()
8047 cpu->apic_state = NULL; in x86_cpu_unrealizefn()
8050 xcc->parent_unrealize(dev); in x86_cpu_unrealizefn()
8063 uint64_t f = cpu->env.features[fp->w]; in x86_cpu_get_bit_prop()
8064 bool value = (f & fp->mask) == fp->mask; in x86_cpu_get_bit_prop()
8076 if (dev->realized) { in x86_cpu_set_bit_prop()
8086 cpu->env.features[fp->w] |= fp->mask; in x86_cpu_set_bit_prop()
8088 cpu->env.features[fp->w] &= ~fp->mask; in x86_cpu_set_bit_prop()
8090 cpu->env.user_features[fp->w] |= fp->mask; in x86_cpu_set_bit_prop()
8111 fp = op->opaque; in x86_cpu_register_bit_prop()
8112 assert(fp->w == w); in x86_cpu_register_bit_prop()
8113 fp->mask |= mask; in x86_cpu_register_bit_prop()
8116 fp->w = w; in x86_cpu_register_bit_prop()
8117 fp->mask = mask; in x86_cpu_register_bit_prop()
8130 const char *name = fi->feat_names[bitnr]; in x86_cpu_register_feature_bit_props()
8136 /* Property names should use "-" instead of "_". in x86_cpu_register_feature_bit_props()
8164 esa->size = 0; in x86_cpu_post_initfn()
8174 CPUX86State *env = &cpu->env; in x86_cpu_init_default_topo()
8176 env->nr_modules = 1; in x86_cpu_init_default_topo()
8177 env->nr_dies = 1; in x86_cpu_init_default_topo()
8180 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); in x86_cpu_init_default_topo()
8181 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); in x86_cpu_init_default_topo()
8182 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); in x86_cpu_init_default_topo()
8189 CPUX86State *env = &cpu->env; in x86_cpu_initfn()
8193 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", in x86_cpu_initfn()
8195 NULL, NULL, (void *)env->features); in x86_cpu_initfn()
8196 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", in x86_cpu_initfn()
8198 NULL, NULL, (void *)cpu->filtered_features); in x86_cpu_initfn()
8202 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); in x86_cpu_initfn()
8203 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); in x86_cpu_initfn()
8205 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); in x86_cpu_initfn()
8208 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); in x86_cpu_initfn()
8209 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); in x86_cpu_initfn()
8210 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); in x86_cpu_initfn()
8211 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); in x86_cpu_initfn()
8212 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); in x86_cpu_initfn()
8213 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); in x86_cpu_initfn()
8214 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); in x86_cpu_initfn()
8215 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); in x86_cpu_initfn()
8216 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); in x86_cpu_initfn()
8217 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); in x86_cpu_initfn()
8218 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); in x86_cpu_initfn()
8219 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); in x86_cpu_initfn()
8220 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); in x86_cpu_initfn()
8221 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); in x86_cpu_initfn()
8222 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); in x86_cpu_initfn()
8223 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); in x86_cpu_initfn()
8224 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); in x86_cpu_initfn()
8225 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); in x86_cpu_initfn()
8226 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); in x86_cpu_initfn()
8227 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); in x86_cpu_initfn()
8228 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); in x86_cpu_initfn()
8232 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); in x86_cpu_initfn()
8233 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; in x86_cpu_initfn()
8234 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); in x86_cpu_initfn()
8236 if (xcc->model) { in x86_cpu_initfn()
8237 x86_cpu_load_model(cpu, xcc->model); in x86_cpu_initfn()
8245 return cpu->apic_id; in x86_cpu_get_arch_id()
8253 return cpu->env.cr[0] & CR0_PG_MASK; in x86_cpu_get_paging_enabled()
8261 cpu->env.eip = value; in x86_cpu_set_pc()
8269 return cpu->env.eip + cpu->env.segs[R_CS].base; in x86_cpu_get_pc()
8275 CPUX86State *env = &cpu->env; in x86_cpu_pending_interrupt()
8286 if (env->hflags2 & HF2_GIF_MASK) { in x86_cpu_pending_interrupt()
8288 !(env->hflags & HF_SMM_MASK)) { in x86_cpu_pending_interrupt()
8291 !(env->hflags2 & HF2_NMI_MASK)) { in x86_cpu_pending_interrupt()
8296 (((env->hflags2 & HF2_VINTR_MASK) && in x86_cpu_pending_interrupt()
8297 (env->hflags2 & HF2_HIF_MASK)) || in x86_cpu_pending_interrupt()
8298 (!(env->hflags2 & HF2_VINTR_MASK) && in x86_cpu_pending_interrupt()
8299 (env->eflags & IF_MASK && in x86_cpu_pending_interrupt()
8300 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { in x86_cpu_pending_interrupt()
8303 } else if (env->hflags2 & HF2_VGIF_MASK) { in x86_cpu_pending_interrupt()
8305 (env->eflags & IF_MASK) && in x86_cpu_pending_interrupt()
8306 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { in x86_cpu_pending_interrupt()
8318 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; in x86_cpu_has_work()
8323 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; in x86_mmu_index_pl()
8326 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : in x86_mmu_index_pl()
8327 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; in x86_mmu_index_pl()
8335 return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); in x86_cpu_mmu_index()
8340 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; in x86_mmu_index_kernel_pl()
8342 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : in x86_mmu_index_kernel_pl()
8343 (pl < 3 && (env->eflags & AC_MASK) in x86_mmu_index_kernel_pl()
8351 return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); in cpu_mmu_index_kernel()
8357 CPUX86State *env = &cpu->env; in x86_disas_set_info()
8359 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 in x86_disas_set_info()
8360 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 in x86_disas_set_info()
8363 info->cap_arch = CS_ARCH_X86; in x86_disas_set_info()
8364 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 in x86_disas_set_info()
8365 : env->hflags & HF_CS32_MASK ? CS_MODE_32 in x86_disas_set_info()
8367 info->cap_insn_unit = 1; in x86_disas_set_info()
8368 info->cap_insn_split = 8; in x86_disas_set_info()
8380 hflags = env->hflags & HFLAG_COPY_MASK; in x86_update_hflags()
8381 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; in x86_update_hflags()
8382 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); in x86_update_hflags()
8383 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & in x86_update_hflags()
8385 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); in x86_update_hflags()
8387 if (env->cr[4] & CR4_OSFXSR_MASK) { in x86_update_hflags()
8391 if (env->efer & MSR_EFER_LMA) { in x86_update_hflags()
8395 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { in x86_update_hflags()
8398 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> in x86_update_hflags()
8399 (DESC_B_SHIFT - HF_CS32_SHIFT); in x86_update_hflags()
8400 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> in x86_update_hflags()
8401 (DESC_B_SHIFT - HF_SS32_SHIFT); in x86_update_hflags()
8402 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || in x86_update_hflags()
8406 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | in x86_update_hflags()
8407 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; in x86_update_hflags()
8410 env->hflags = hflags; in x86_update_hflags()
8415 /* apic_id = 0 by default for *-user, see commit 9886e834 */
8416 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
8417 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
8418 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
8419 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0),
8420 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
8421 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
8423 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
8424 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
8425 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
8426 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1),
8427 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
8428 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
8430 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
8432 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT),
8434 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
8436 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
8438 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
8440 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
8442 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
8444 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
8446 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
8448 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
8450 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
8452 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
8454 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
8456 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
8458 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
8460 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
8462 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
8464 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
8466 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features,
8468 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features,
8470 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features,
8472 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features,
8474 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features,
8476 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
8479 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features,
8482 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
8483 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false),
8486 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build,
8488 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major,
8490 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor,
8492 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0),
8493 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0),
8494 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0),
8498 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
8500 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
8501 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1),
8502 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
8503 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
8504 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
8505 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
8510 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
8511 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
8512 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
8513 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0),
8514 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
8515 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
8516 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
8517 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
8518 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true),
8519 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true),
8521 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
8522 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid,
8524 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
8525 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
8526 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
8532 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
8533 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false),
8534 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false),
8539 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
8542 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
8548 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
8549 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
8551 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
8553 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true),
8558 #include "hw/core/sysemu-cpu-ops.h"
8583 &xcc->parent_realize); in x86_cpu_common_class_init()
8585 &xcc->parent_unrealize); in x86_cpu_common_class_init()
8589 &xcc->parent_phases); in x86_cpu_common_class_init()
8590 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; in x86_cpu_common_class_init()
8592 cc->class_by_name = x86_cpu_class_by_name; in x86_cpu_common_class_init()
8593 cc->parse_features = x86_cpu_parse_featurestr; in x86_cpu_common_class_init()
8594 cc->has_work = x86_cpu_has_work; in x86_cpu_common_class_init()
8595 cc->mmu_index = x86_cpu_mmu_index; in x86_cpu_common_class_init()
8596 cc->dump_state = x86_cpu_dump_state; in x86_cpu_common_class_init()
8597 cc->set_pc = x86_cpu_set_pc; in x86_cpu_common_class_init()
8598 cc->get_pc = x86_cpu_get_pc; in x86_cpu_common_class_init()
8599 cc->gdb_read_register = x86_cpu_gdb_read_register; in x86_cpu_common_class_init()
8600 cc->gdb_write_register = x86_cpu_gdb_write_register; in x86_cpu_common_class_init()
8601 cc->get_arch_id = x86_cpu_get_arch_id; in x86_cpu_common_class_init()
8604 cc->sysemu_ops = &i386_sysemu_ops; in x86_cpu_common_class_init()
8607 cc->gdb_arch_name = x86_gdb_arch_name; in x86_cpu_common_class_init()
8609 cc->gdb_core_xml_file = "i386-64bit.xml"; in x86_cpu_common_class_init()
8611 cc->gdb_core_xml_file = "i386-32bit.xml"; in x86_cpu_common_class_init()
8613 cc->disas_set_info = x86_disas_set_info; in x86_cpu_common_class_init()
8615 dc->user_creatable = true; in x86_cpu_common_class_init()
8629 object_class_property_add_str(oc, "model-id", in x86_cpu_common_class_init()
8632 object_class_property_add(oc, "tsc-frequency", "int", in x86_cpu_common_class_init()
8636 * The "unavailable-features" property has the same semantics as in x86_cpu_common_class_init()
8637 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" in x86_cpu_common_class_init()
8641 object_class_property_add(oc, "unavailable-features", "strList", in x86_cpu_common_class_init()
8646 object_class_property_add(oc, "crash-information", "GuestPanicInformation", in x86_cpu_common_class_init()
8671 /* "base" CPU model, used by query-cpu-model-expansion */
8676 xcc->static_model = true; in x86_cpu_base_class_init()
8677 xcc->migration_safe = true; in x86_cpu_base_class_init()
8678 xcc->model_description = "base CPU model type with no features enabled"; in x86_cpu_base_class_init()
8679 xcc->ordering = 8; in x86_cpu_base_class_init()