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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
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H A Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19 privilege modes per hart; machine mode and supervisor mode.
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/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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/openbmc/linux/arch/riscv/include/asm/
H A Dcsr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
17 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
39 #define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */
48 #define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */
49 #define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */
50 #define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */
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/openbmc/linux/Documentation/riscv/
H A Duabi.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Linux User ABI
7 ------------------------------------
14 #. Single-letter extensions come first, in canonical order.
17 #. All multi-letter extensions will be separated from other extensions by an
21 single-letter extensions and before any higher-privileged extensions.
29 #. Standard supervisor-level extensions (starting with 'S') will be listed
30 after standard unprivileged extensions. If multiple supervisor-level
33 #. Standard machine-level extensions (starting with 'Zxm') will be listed
34 after any lower-privileged, standard extensions. If multiple machine-level
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/openbmc/qemu/target/riscv/
H A Dcpu_bits.h1 /* RISC-V ISA constants */
52 /* User Floating-Point CSRs */
160 /* 32-bit only */
172 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
176 /* Machine-Level Interrupts (AIA) */
180 /* Virtual Interrupts for Supervisor Level (AIA) */
184 /* Machine-Level High-Half CSRs (AIA) */
191 /* Supervisor Trap Setup */
197 /* Supervisor Configuration CSRs */
200 /* Supervisor state CSRs */
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/openbmc/linux/arch/microblaze/include/asm/
H A Dmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
27 unsigned long w:1; /* Write-thru cache mode */
36 # define PP_RWXX 0 /* Supervisor read/write, User none */
37 # define PP_RWRX 1 /* Supervisor read/write, User read */
38 # define PP_RWRW 2 /* Supervisor read/write, User read/write */
39 # define PP_RXRX 3 /* Supervisor read, User read */
44 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
46 unsigned long n:1; /* No-execute */
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/openbmc/u-boot/arch/powerpc/include/asm/
H A Dmmu.h28 unsigned long w:1; /* Write-thru cache mode */
37 #define PP_RWXX 0 /* Supervisor read/write, User none */
38 #define PP_RWRX 1 /* Supervisor read/write, User read */
39 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
40 #define PP_RXRX 3 /* Supervisor read, User read */
45 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
47 unsigned long n:1; /* No-execute */
59 unsigned long ks:1; /* Supervisor key (normally 0) */
72 unsigned long vs:1; /* Supervisor valid */
90 unsigned long w:1; /* Write-thru cache */
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/openbmc/linux/arch/x86/kvm/
H A Dmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
57 return ((2ULL << (e - s)) - 1) << s; in rsvd_bits()
61 * The number of non-reserved physical address bits irrespective of features
81 return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1; in kvm_mmu_max_gfn()
129 if (likely(vcpu->arch.mmu->root.hpa != INVALID_PAGE)) in kvm_mmu_reload()
151 u64 root_hpa = vcpu->arch.mmu->root.hpa; in kvm_mmu_load_pgd()
157 vcpu->arch.mmu->root_role.level); in kvm_mmu_load_pgd()
166 * be stale. Refresh CR0.WP and the metadata on-demand when checking in kvm_mmu_refresh_passthrough_bits()
172 if (!tdp_enabled || mmu == &vcpu->arch.guest_mmu) in kvm_mmu_refresh_passthrough_bits()
195 * For explicit supervisor accesses, SMAP is disabled if EFLAGS.AC = 1. in permission_fault()
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/openbmc/linux/arch/powerpc/include/asm/nohash/32/
H A Dpte-8xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * We also use the two level tables, but we can put the real bits in them
10 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
16 * the TLB entry (24 and 25) for these indicators. Although the level 1
18 * set these at the page level since they get copied from the Mx_TWC
21 * These will get masked from the level 2 descriptor at TLB load time, and
46 #define _PAGE_NA 0x0200 /* Supervisor NA, User no access */
47 #define _PAGE_RO 0x0600 /* Supervisor RO, User no access */
162 pte_update(vma->vm_mm, address, ptep, clr, set, huge); in __ptep_set_access_flags()
H A Dmmu-8xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * During software tablewalk, the registers used perform mask/shift-add
33 * respectively NA for All or X for Supervisor and no access for User.
35 * "all Supervisor" rules (Access to all)
43 * 4-15 => Not Used
57 /* A "level 1" or "segment" or whatever you want to call it register.
120 /* The pointer to the base address of the first level page table.
125 #define M_L1TB 0xfffff000 /* Level 1 table base address */
126 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */
129 /* A "level 1" or "segment" or whatever you want to call it register.
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/openbmc/u-boot/arch/arm/mach-imx/
H A Dinit.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/imx-regs.h>
10 #include <asm/mach-imx/boot_mode.h>
22 * Set all MPROTx to be non-bufferable, trusted for R/W, in init_aips()
23 * not forced to user-mode. in init_aips()
25 writel(0x77777777, &aips1->mprot0); in init_aips()
26 writel(0x77777777, &aips1->mprot1); in init_aips()
27 writel(0x77777777, &aips2->mprot0); in init_aips()
28 writel(0x77777777, &aips2->mprot1); in init_aips()
31 * Set all OPACRx to be non-bufferable, not require in init_aips()
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/openbmc/qemu/hw/intc/
H A Driscv_aplic.c2 * RISC-V APLIC (Advanced Platform Level Interrupt Controller)
23 #include "qemu/error-report.h"
25 #include "exec/address-spaces.h"
29 #include "hw/qdev-properties.h"
80 ((1UL << (__lhxs)) - 1)
83 ((1UL << (__lhxw)) - 1)
91 ((1UL << (__hhxw)) - 1)
167 if (!irq || aplic->num_irqs <= irq) { in riscv_aplic_irq_rectified_val()
171 sourcecfg = aplic->sourcecfg[irq]; in riscv_aplic_irq_rectified_val()
181 raw_input = (aplic->state[irq] & APLIC_ISTATE_INPUT) ? 1 : 0; in riscv_aplic_irq_rectified_val()
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/openbmc/linux/arch/openrisc/include/asm/
H A Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
215 #define SPR_SR_SM 0x00000001 /* Supervisor Mode */
231 #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
239 #define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
240 #define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
248 #define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
249 #define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
258 #define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
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H A Dthread_info.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
35 * low level task data that entry.S needs immediate access to
36 * - this struct should fit entirely inside of one cache line
37 * - this struct shares the supervisor stack pages
38 * - if the contents of this structure are changed, the assembly constants
45 unsigned long flags; /* low level flags */
75 #define get_thread_info(ti) get_task_struct((ti)->task)
76 #define put_thread_info(ti) put_task_struct((ti)->task)
84 * - pending work-to-be-done flags are in LSW
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/openbmc/linux/tools/perf/pmu-events/arch/arm64/
H A Drecommended.json3 "PublicDescription": "Attributable Level 1 data cache access, read",
9 "PublicDescription": "Attributable Level 1 data cache access, write",
15 "PublicDescription": "Attributable Level 1 data cache refill, read",
21 "PublicDescription": "Attributable Level 1 data cache refill, write",
27 "PublicDescription": "Attributable Level 1 data cache refill, inner",
33 "PublicDescription": "Attributable Level 1 data cache refill, outer",
39 "PublicDescription": "Attributable Level 1 data cache Write-Back, victim",
42 "BriefDescription": "L1D cache Write-Back, victim"
45 "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency",
48 "BriefDescription": "L1D cache Write-Back, cleaning and coherency"
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/openbmc/linux/arch/mips/include/asm/octeon/
H A Docteon.h6 * Copyright (C) 2004-2008 Cavium Networks
57 /* Start of block referenced by assembly code - do not change! */
66 /* End of This block referenced by assembly code - do not change! */
117 /* End of This block referenced by assembly code - do not change! */
124 * Warning low bit scrambled in little-endian.
182 /* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
189 /* OCTEON II - Selects the bit in the counter used for
196 /* OCTEON II - This field is an extension of
199 /* R/W If set, marked write-buffer entries time out
201 * write-buffer entries use the maximum timeout. */
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/openbmc/u-boot/arch/arm/include/asm/
H A Dmacro.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * include/asm-arm/macro.h
5 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
24 * caches are enabled or on a multi-core system.
68 * Branch according to exception level
81 * Branch if current processor is a Cortex-A57 core.
87 cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */
92 * Branch if current processor is a Cortex-A53 core.
98 cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */
108 /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
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/openbmc/linux/arch/nios2/include/asm/
H A Dthread_info.h2 * NiosII low-level thread information
30 * low level task data that entry.S needs immediate access to
31 * - this struct should fit entirely inside of one cache line
32 * - this struct shares the supervisor stack pages
33 * - if the contents of this structure are changed, the assembly constants
38 unsigned long flags; /* low level flags */
62 return (struct thread_info *)(sp & ~(THREAD_SIZE - 1)); in current_thread_info()
68 * - these are process state flags that various assembly files may need to
70 * - pending work-to-be-done flags are in LSW
71 * - other flags in MSW
/openbmc/u-boot/drivers/misc/
H A DKconfig50 bool "Rockchip e-fuse support"
53 Enable (read-only) access for the e-fuse block found in Rockchip
55 or through child-nodes that are generated based on the e-fuse map
74 Enable command-line access to the Chrome OS EC (Embedded
76 a number of sub-commands for performing EC tasks such as
112 keyboard (use the -l flag to enable the LCD), verified boot context,
121 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
126 bool "Enable support for DS4510 CPU supervisor"
128 Enable support for the Maxim DS4510 CPU supervisor. It has an
129 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
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/openbmc/linux/arch/arm/mach-imx/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0
42 * Set all MPROTx to be non-bufferable, trusted for R/W, in imx_set_aips()
43 * not forced to user-mode. in imx_set_aips()
49 * Set all OPACRx to be non-bufferable, to not require in imx_set_aips()
50 * supervisor privilege level for access, allow for in imx_set_aips()
/openbmc/linux/arch/arc/include/asm/
H A Dthread_info.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
7 * anyways one page allocation, thus slab alloc can be short-circuited and
32 * low level task data that entry.S needs immediate access to
33 * - this struct should fit entirely inside of one cache line
34 * - this struct shares the supervisor stack pages
35 * - if the contents of this structure are changed, the assembly constants
39 unsigned long flags; /* low level flags */
49 * - this is not related to init_task per se
62 return (struct thread_info *)(sp & ~(THREAD_SIZE - 1)); in current_thread_info()
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/openbmc/linux/arch/s390/include/asm/
H A Dthread_info.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <asm/asm-offsets.h>
27 #define STACK_INIT_OFFSET (THREAD_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE)
34 * low level task data that entry.S needs immediate access to
35 * - this struct should fit entirely inside of one cache line
36 * - this struct shares the supervisor stack pages
37 * - if the contents of this structure are changed, the assembly constants must also be changed
40 unsigned long flags; /* low level flags */
67 #define TIF_UPROBE 3 /* breakpointed or single-stepping */
/openbmc/linux/arch/loongarch/include/asm/
H A Dthread_info.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * thread_info.h: LoongArch low-level thread information
5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
18 * low level task data that entry.S needs immediate access to
19 * - this struct should fit entirely inside of one cache line
20 * - this struct shares the supervisor stack pages
21 * - if the contents of this structure are changed, the assembly constants
26 unsigned long flags; /* low level flags */
60 #define THREAD_MASK (THREAD_SIZE - 1UL)
64 * - these are process state flags that various assembly files may need to
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/openbmc/qemu/target/m68k/
H A Dcpu.h4 * Copyright (c) 2005-2007 CodeSourcery
24 #include "exec/cpu-defs.h"
25 #include "qemu/cpu-float.h"
26 #include "cpu-qom.h"
45 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */
46 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */
47 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */
52 #define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */
53 #define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */
62 #define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */
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