1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_NOHASH_32_PTE_8xx_H
3 #define _ASM_POWERPC_NOHASH_32_PTE_8xx_H
4 #ifdef __KERNEL__
5 
6 /*
7  * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
8  * We also use the two level tables, but we can put the real bits in them
9  * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
10  * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
11  * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
12  * based upon user/super access.  The TLB does not have accessed nor write
13  * protect.  We assume that if the TLB get loaded with an entry it is
14  * accessed, and overload the changed bit for write protect.  We use
15  * two bits in the software pte that are supposed to be set to zero in
16  * the TLB entry (24 and 25) for these indicators.  Although the level 1
17  * descriptor contains the guarded and writethrough/copyback bits, we can
18  * set these at the page level since they get copied from the Mx_TWC
19  * register when the TLB entry is loaded.  We will use bit 27 for guard, since
20  * that is where it exists in the MD_TWC, and bit 26 for writethrough.
21  * These will get masked from the level 2 descriptor at TLB load time, and
22  * copied to the MD_TWC before it gets loaded.
23  * Large page sizes added.  We currently support two sizes, 4K and 8M.
24  * This also allows a TLB hander optimization because we can directly
25  * load the PMD into MD_TWC.  The 8M pages are only used for kernel
26  * mapping of well known areas.  The PMD (PGD) entries contain control
27  * flags in addition to the address, so care must be taken that the
28  * software no longer assumes these are only pointers.
29  */
30 
31 /* Definitions for 8xx embedded chips. */
32 #define _PAGE_PRESENT	0x0001	/* V: Page is valid */
33 #define _PAGE_NO_CACHE	0x0002	/* CI: cache inhibit */
34 #define _PAGE_SH	0x0004	/* SH: No ASID (context) compare */
35 #define _PAGE_SPS	0x0008	/* SPS: Small Page Size (1 if 16k, 512k or 8M)*/
36 #define _PAGE_DIRTY	0x0100	/* C: page changed */
37 
38 /* These 4 software bits must be masked out when the L2 entry is loaded
39  * into the TLB.
40  */
41 #define _PAGE_GUARDED	0x0010	/* Copied to L1 G entry in DTLB */
42 #define _PAGE_ACCESSED	0x0020	/* Copied to L1 APG 1 entry in I/DTLB */
43 #define _PAGE_EXEC	0x0040	/* Copied to PP (bit 21) in ITLB */
44 #define _PAGE_SPECIAL	0x0080	/* SW entry */
45 
46 #define _PAGE_NA	0x0200	/* Supervisor NA, User no access */
47 #define _PAGE_RO	0x0600	/* Supervisor RO, User no access */
48 
49 #define _PAGE_HUGE	0x0800	/* Copied to L1 PS bit 29 */
50 
51 /* cache related flags non existing on 8xx */
52 #define _PAGE_COHERENT	0
53 #define _PAGE_WRITETHRU	0
54 
55 #define _PAGE_KERNEL_RO		(_PAGE_SH | _PAGE_RO)
56 #define _PAGE_KERNEL_ROX	(_PAGE_SH | _PAGE_RO | _PAGE_EXEC)
57 #define _PAGE_KERNEL_RW		(_PAGE_SH | _PAGE_DIRTY)
58 #define _PAGE_KERNEL_RWX	(_PAGE_SH | _PAGE_DIRTY | _PAGE_EXEC)
59 
60 #define _PMD_PRESENT	0x0001
61 #define _PMD_PRESENT_MASK	_PMD_PRESENT
62 #define _PMD_BAD	0x0f90
63 #define _PMD_PAGE_MASK	0x000c
64 #define _PMD_PAGE_8M	0x000c
65 #define _PMD_PAGE_512K	0x0004
66 #define _PMD_ACCESSED	0x0020	/* APG 1 */
67 #define _PMD_USER	0x0040	/* APG 2 */
68 
69 #define _PTE_NONE_MASK	0
70 
71 #ifdef CONFIG_PPC_16K_PAGES
72 #define _PAGE_PSIZE	_PAGE_SPS
73 #else
74 #define _PAGE_PSIZE		0
75 #endif
76 
77 #define _PAGE_BASE_NC	(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
78 #define _PAGE_BASE	(_PAGE_BASE_NC)
79 
80 /* Permission masks used to generate the __P and __S table */
81 #define PAGE_NONE	__pgprot(_PAGE_BASE | _PAGE_NA)
82 #define PAGE_SHARED	__pgprot(_PAGE_BASE)
83 #define PAGE_SHARED_X	__pgprot(_PAGE_BASE | _PAGE_EXEC)
84 #define PAGE_COPY	__pgprot(_PAGE_BASE | _PAGE_RO)
85 #define PAGE_COPY_X	__pgprot(_PAGE_BASE | _PAGE_RO | _PAGE_EXEC)
86 #define PAGE_READONLY	__pgprot(_PAGE_BASE | _PAGE_RO)
87 #define PAGE_READONLY_X	__pgprot(_PAGE_BASE | _PAGE_RO | _PAGE_EXEC)
88 
89 #ifndef __ASSEMBLY__
pte_wrprotect(pte_t pte)90 static inline pte_t pte_wrprotect(pte_t pte)
91 {
92 	return __pte(pte_val(pte) | _PAGE_RO);
93 }
94 
95 #define pte_wrprotect pte_wrprotect
96 
pte_read(pte_t pte)97 static inline int pte_read(pte_t pte)
98 {
99 	return (pte_val(pte) & _PAGE_RO) != _PAGE_NA;
100 }
101 
102 #define pte_read pte_read
103 
pte_write(pte_t pte)104 static inline int pte_write(pte_t pte)
105 {
106 	return !(pte_val(pte) & _PAGE_RO);
107 }
108 
109 #define pte_write pte_write
110 
pte_mkwrite_novma(pte_t pte)111 static inline pte_t pte_mkwrite_novma(pte_t pte)
112 {
113 	return __pte(pte_val(pte) & ~_PAGE_RO);
114 }
115 
116 #define pte_mkwrite_novma pte_mkwrite_novma
117 
pte_user(pte_t pte)118 static inline bool pte_user(pte_t pte)
119 {
120 	return !(pte_val(pte) & _PAGE_SH);
121 }
122 
123 #define pte_user pte_user
124 
pte_mkprivileged(pte_t pte)125 static inline pte_t pte_mkprivileged(pte_t pte)
126 {
127 	return __pte(pte_val(pte) | _PAGE_SH);
128 }
129 
130 #define pte_mkprivileged pte_mkprivileged
131 
pte_mkuser(pte_t pte)132 static inline pte_t pte_mkuser(pte_t pte)
133 {
134 	return __pte(pte_val(pte) & ~_PAGE_SH);
135 }
136 
137 #define pte_mkuser pte_mkuser
138 
pte_mkhuge(pte_t pte)139 static inline pte_t pte_mkhuge(pte_t pte)
140 {
141 	return __pte(pte_val(pte) | _PAGE_SPS | _PAGE_HUGE);
142 }
143 
144 #define pte_mkhuge pte_mkhuge
145 
146 static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr, pte_t *p,
147 				     unsigned long clr, unsigned long set, int huge);
148 
ptep_set_wrprotect(struct mm_struct * mm,unsigned long addr,pte_t * ptep)149 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
150 {
151 	pte_update(mm, addr, ptep, 0, _PAGE_RO, 0);
152 }
153 #define ptep_set_wrprotect ptep_set_wrprotect
154 
__ptep_set_access_flags(struct vm_area_struct * vma,pte_t * ptep,pte_t entry,unsigned long address,int psize)155 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
156 					   pte_t entry, unsigned long address, int psize)
157 {
158 	unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_EXEC);
159 	unsigned long clr = ~pte_val(entry) & _PAGE_RO;
160 	int huge = psize > mmu_virtual_psize ? 1 : 0;
161 
162 	pte_update(vma->vm_mm, address, ptep, clr, set, huge);
163 
164 	flush_tlb_page(vma, address);
165 }
166 #define __ptep_set_access_flags __ptep_set_access_flags
167 
pgd_leaf_size(pgd_t pgd)168 static inline unsigned long pgd_leaf_size(pgd_t pgd)
169 {
170 	if (pgd_val(pgd) & _PMD_PAGE_8M)
171 		return SZ_8M;
172 	return SZ_4M;
173 }
174 
175 #define pgd_leaf_size pgd_leaf_size
176 
pte_leaf_size(pte_t pte)177 static inline unsigned long pte_leaf_size(pte_t pte)
178 {
179 	pte_basic_t val = pte_val(pte);
180 
181 	if (val & _PAGE_HUGE)
182 		return SZ_512K;
183 	if (val & _PAGE_SPS)
184 		return SZ_16K;
185 	return SZ_4K;
186 }
187 
188 #define pte_leaf_size pte_leaf_size
189 
190 #endif
191 
192 #endif /* __KERNEL__ */
193 #endif /*  _ASM_POWERPC_NOHASH_32_PTE_8xx_H */
194