Home
last modified time | relevance | path

Searched +full:sub +full:- +full:processor (Results 1 – 25 of 109) sorted by relevance

12345

/openbmc/qemu/docs/specs/
H A Dppc-xive.rst5 The POWER9 processor comes with a new interrupt controller
19 The XIVE IC is composed of three sub-engines, each taking care of a
22 - Interrupt Virtualization Source Engine (IVSE), or Source Controller
23 (SC). These are found in PCI PHBs, in the Processor Service
25 controller for the core IPIs and other sub-chips (NX, CAP, NPU) of
26 the chip/processor. They are configured to feed the IVRE with
28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
32 - Interrupt Virtualization Presentation Engine (IVPE) or Presentation
40 +------------------------------------+ IPIs
41 | +---------+ +---------+ +--------+ | +-------+
[all …]
H A Dfsi.rst8 FSI is a point-to-point two wire interface which is capable of supporting
13 FSI allows a service processor access to the internal buses of a host POWER
14 processor to perform configuration or debugging. FSI has long existed in POWER
18 Working backwards from the POWER processor, the fundamental pieces of interest
32 3. The FSI master: A controller in the platform service processor (e.g. BMC)
34 FSI is a bit-based protocol supporting synchronous and DMA-driven accesses
37 4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER
40 MMIO-mapping of the CFAM address straight onto a sub-region of the OPB
43 5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the
58 As for FSI, its symbols and wire-protocol are not modelled at all. This is not
[all …]
/openbmc/u-boot/doc/
H A DREADME.blackfin1 Notes for the Blackfin architecture port of Das U-Boot
8 Blackfin Processors embody a new breed of 16/32-bit embedded processor, ideally
9 suited for products where a convergence of capabilities are necessary -
10 multi-format audio, video, voice and image processing; multi-mode baseband and
11 packet processing; control processing; and real-time security. The Blackfin's
16 The Blackfin processor is wholly developed by Analog Devices Inc.
26 In particular, bug reports, feature requests, help etc... for Das U-Boot are
27 handled in the Das U-Boot sub project:
28 http://blackfin.uclinux.org/gf/project/u-boot
38 the Blackfin processor. You can obtain such a cross-compiler here:
[all …]
/openbmc/phosphor-mrw-tools/
H A Dinventory.pl27 my %includedTargetTypes = ("chip-sp-bmc" => 1,
28 "chip-apss-psoc" => 1);
41 my $targetObj = Targets->new;
42 $targetObj->loadXML($serverwizFile);
44 foreach $target (sort keys %{ $targetObj->getAllTargets() })
46 $type = $targetObj->getType($target);
53 if (!$targetObj->isBadAttribute($target, "FRU_NAME")) {
54 $fruName = $targetObj->getAttribute($target,"FRU_NAME");
57 my $targetType = $targetObj->getTargetType($target);
90 my $json = JSON->new;
[all …]
H A DInventory.pm14 #Chips that are modeled as modules (card-chip together)
22 sub getInventory
44 #This will pick up FRUs and other chips like the BMC and processor.
45 sub findItems
49 for my $target (sort keys %{$targetObj->getAllTargets()}) {
53 if (!$targetObj->isBadAttribute($target, "TYPE")) {
54 $type = $targetObj->getAttribute($target, "TYPE");
57 if (!$targetObj->isBadAttribute($target, "RU_TYPE")) {
58 $ruType = $targetObj->getAttribute($target, "RU_TYPE");
73 #is a card-chip instance that plugs into a connector on the
[all …]
H A Dgen_callouts.pl31 my $targets = Targets->new;
32 $targets->loadXML($mrwFile);
40 …s/devices/platform/ahb/ahb:apb/ahb:apb:bus\@1e78a000/1e78a100.i2c-bus/i2c-<port>/<port>-00<address…
41 my $fsiMasterPath = "/sys/devices/platform/gpio-fsi/fsi0/slave\@00:00/raw";
42 my $fsiSlavePath = "/sys/devices/platform/gpio-fsi/fsi0/slave\@00:00/00:00:00:0a/fsi1/slave\@<link>…
53 sub genI2CCallouts
56 my $connections = $targets->findConnections($bmc, "I2C");
57 # hash of arrays - {I2C master port : list of connected slave Targets}
60 for my $i2c (@{$connections->{CONN}})
62 my $master = $i2c->{SOURCE};
[all …]
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME2 --------
6 ------------------
7 The QorIQ LS1 family, which includes the LS1021A communications processor,
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
[all …]
/openbmc/u-boot/arch/x86/lib/
H A Dscu.c1 // SPDX-License-Identifier: GPL-2.0+
38 * scu_ipc_send_command() - send command to SCU
43 * A write to this register results in an interrupt to the SCU core processor
49 writel(cmd, &regs->cmd); in scu_ipc_send_command()
53 * scu_ipc_check_status() - check status of last command
68 status = readl(&regs->status); in scu_ipc_check_status()
73 } while (--loop_count); in scu_ipc_check_status()
75 return -ETIMEDOUT; in scu_ipc_check_status()
79 return -EIO; in scu_ipc_check_status()
85 static int scu_ipc_cmd(struct ipc_regs *regs, u32 cmd, u32 sub, in scu_ipc_cmd() argument
[all …]
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME2 --------
6 ------------------
7 The QorIQ LS1 family, which includes the LS1021A communications processor,
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
[all …]
/openbmc/openpower-hw-diags/test/
H A Dtest-pll-unlock.cpp4 #include <analyzer/ras-data/ras-data-parser.hpp>
25 // Sub-test #1 - single PLL unlock attention on proc 1, clock 1
39 rasData.getResolution(sig11)->resolve(sd); in TEST()
80 // Sub-test #2 - PLL unlock attention on multiple procs and clocks. Isolating
89 // PLL unlock signatures for each clock per processor. in TEST()
95 // Plugins for each processor. in TEST()
159 // Sub-test #3 - PLL unlock on single OCMB.
175 rasData.getResolution(sig)->resolve(sd); in TEST()
219 // Sub-test #4 - PLL unlock on multiple OCMBs in the same domain.
241 rasData.getResolution(sig0)->resolve(sd); in TEST()
[all …]
/openbmc/docs/designs/
H A Dguard-on-bmc.md5 On systems with multiple processor units and other redundant vital resources,
56 ![Guard Usecases](https://user-images.githubusercontent.com/16666879/70852658-0edfda80-1eca-11ea-9d…
58 - When user requests, create a record in the right guard record repository,
60 - An option should be given to user to create guard record for DIMM and
61 Processor core to manually keep it out of service.
62 - An option should be given to the user to delete a guard record.
63 - An option should be given to list the guard records.
64 - An option should be given to delete all guard records
65 - Industry standard interfaces should be provided to carry out these operations
70 - The guard records on the units which are owned by the host will be applied
[all …]
H A Ddevice-tree-gpio-naming.md12 subsystem. The replacement is a "descriptor-based" character device interface.
25 specific field used to name the GPIOs in the DTS is `gpio-line-names`. This
29 scheme in the face of a universe of potential use-cases.
37 - Ensure common function GPIOs within OpenBMC use the same naming convention
42 naming convention and then the sub bullets list the common GPIO names to be used
52 Pattern: `*-button`
55 BMC-less machines use a button to trigger system behavior and in a BMC-managed
59 #### power-button
68 - `host*-ready`: Host ready, active high
69 - `host*-ready-n`: Host ready, active low
[all …]
/openbmc/openbmc-test-automation/lib/
H A Dipmi_utils.py37 not supported - defaulting to 0x0e
41 sol_info[Set in progress]: set-complete
43 sol_info[Non-Volatile Bit Rate (kbps)]: IPMI-Over-Serial-Setting
46 sol_info[Volatile Bit Rate (kbps)]: IPMI-Over-Serial-Setting
78 # "retry-count").
184 # process it as a sub-dictionary.
188 + " | grep -E '^(Auth Type Enable)"
189 + "?[ ]+: ' | sed -re 's/^(Auth Type Enable)?[ ]+: //g'"
196 # names (i.e. the 'Auth Type Enable' sub-fields).
197 cmd_buf = "lan print " + channel_number + " | grep -E -v '^[ ]+: '"
[all …]
/openbmc/qemu/include/hw/ppc/
H A Dxive.h5 * The POWER9 processor comes with a new interrupt controller, called
12 * +------------------------------------+ IPIs
13 * | +---------+ +---------+ +--------+ | +-------+
14 * | |VC | |CQ | |PC |----> | CORES |
15 * | | esb | | | | |----> | |
16 * | | eas | | Bridge | | tctx |----> | |
18 * +------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+
19 * | RAM | +------------------|-----------------+ | | |
22 * | | +--------------------v------------------------v-v-v--+ other
23 * | <--+ Power Bus +--> chips
[all …]
H A Dopenpic.h50 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
75 bool level:1; /* level-triggered */
92 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
122 /* Count of IRQ sources asserting on non-INT outputs */
150 /* Sub-regions */
156 uint32_t pir; /* Processor initialization register */
/openbmc/qemu/include/hw/xen/interface/
H A Darch-arm.h1 /* SPDX-License-Identifier: MIT */
3 * arch-arm.h
21 * 32- or 64-bit), the second argument in x1/r1, the third in x2/r2,
26 * is an inter-procedure-call scratch register (e.g. for use in linker
40 * EABI) and Procedure Call Standard for the ARM 64-bit Architecture
41 * (AAPCS64). Where there is a conflict the 64-bit standard should be
47 * which is mapped as Normal Inner Write-Back Outer Write-Back Inner-Shareable.
49 * - hypercall arguments passed via a pointer to guest memory.
50 * - memory shared via the grant table mechanism (including PV I/O
52 * - memory shared with the hypervisor (struct shared_info, struct
[all …]
/openbmc/u-boot/board/sbc8548/
H A DREADME6 memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
7 and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
10 U-Boot Configuration:
13 The following possible U-Boot configuration targets are available:
26 a base clock of 66MHz. Note that you need both PCI enabled in U-Boot
34 then you should build a U-Boot with a _PCI_33_ config and store this
36 card. [The above discussion assumes that the SW2[1-4] has not been changed
41 and three, but with PCI-e support enabled as well.
43 PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
44 is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
[all …]
/openbmc/u-boot/arch/xtensa/include/asm/
H A Dasmmacro.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2005 - 2013 Tensilica Inc.
4 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
27 * Some little helpers for loops. Use zero-overhead-loops
28 * where applicable and if supported by the processor.
58 movi \at, ((\size + \incr - 1) / (\incr))
64 .ifgt \incr_log2 - 1
65 addi \at, \as, (1 << \incr_log2) - 1
77 sub \at, \as, \ar
78 .ifgt \incr_log2 - 1
[all …]
/openbmc/u-boot/board/sbc8349/
H A DREADME3 U-Boot for Wind River SBC834x Boards
8 design that uses the MPC8347E or MPC8349E processor. U-Boot support
9 for this board is heavily based on the existing U-Boot support for
33 Note that U-Boot versions up to and including 2009.06 had essentially
34 two copies of U-Boot in flash; one at the very beginning, which set
39 Use of the U-Boot command "fli" will indicate what parts are in use.
40 Details for storing U-Boot to flash using a Wind River ICE can be found
41 on page 19 of the board manual (request ERG-00328-001). The following
44 - Connect ICE and establish connection to it from WorkBench/OCD.
45 - Ensure you have background mode (BKM) in the OCD terminal window.
[all …]
/openbmc/qemu/scripts/kvm/
H A Dvmxcap5 # Copyright 2009-2010 Red Hat, Inc.
11 # the COPYING file in the top-level directory.
74 print(' %-40s %s' % (self.bits[bit], s))
76 # All 64 bits in the tertiary controls MSR are allowed-1
105 v = (value >> lo) & ((1 << (hi - lo + 1)) - 1)
106 print(' %-40s %s' % (self.bits[bits], fmt(v)))
115 49: 'Dual-monitor support',
125 name = 'pin-based controls',
130 6: 'Activate VMX-preemption timer',
138 name = 'primary processor-based controls',
[all …]
/openbmc/libcper/specification/document/
H A Dcper-json-specification.tex7 \title{CPER-JSON Specification}
47 in a human-readable JSON format, intended to be interoperable with standard CPER binary.
50 …ive JSON schema\footnote{As defined by \href{https://json-schema.org/draft/2020-12/json-schema-cor…
178 …ypes of sectoin body are defined in UEFI specification section N.2.2 Table N-5 and section N.2.4.\\
195 containmentWarning & boolean & If true, the error was not contained within the processor or memory …
197 reset & boolean & If true, indicates the component has been reset and must be re-initialised or re-…
212 This section describes generic CPER structures that are re-used throughout the specification.
217 This structure describes the revision of a single CPER record or sub-structure.
253 % Generic processor error section.
254 \section{Generic Processor Error Section}
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema-installed/
H A DProcessor.v1_21_0.json2 "$id": "http://redfish.dmtf.org/schemas/v1/Processor.v1_21_0.json",
3 "$ref": "#/definitions/Processor",
4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2025 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
26 "#Processor.Reset": {
29 "#Processor.ResetToDefaults": {
34 "description": "The available OEM-specific actions for this resource.",
35 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
57 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/json-schema/
H A DProcessor.v1_21_0.json2 "$id": "http://redfish.dmtf.org/schemas/v1/Processor.v1_21_0.json",
3 "$ref": "#/definitions/Processor",
4 "$schema": "http://redfish.dmtf.org/schemas/v1/redfish-schema-v1.json",
5 …"copyright": "Copyright 2014-2025 DMTF. For the full DMTF copyright policy, see http://www.dmtf.or…
12 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
26 "#Processor.Reset": {
29 "#Processor.ResetToDefaults": {
34 "description": "The available OEM-specific actions for this resource.",
35 …"longDescription": "This property shall contain the available OEM-specific actions for this resour…
57 "^([a-zA-Z_][a-zA-Z0-9_]*)?@(odata|Redfish|Message)\\.[a-zA-Z_][a-zA-Z0-9_]*$": {
[all …]
/openbmc/openbmc/meta-arm/meta-arm/lib/oeqa/runtime/cases/
H A Dfvp_devices.py12 * Allows the "run" behavior to be overridden in sub-classes
21 retry -= 1
28 self.fail("Command '%s' returned non-zero exit "
35 cmd = f'find "/sys/class/{cls}" -type l -maxdepth 1'
82 ' -name "cpu@*" -maxdepth 1 | wc -l')
93 _, cpus = self.run_cmd('grep -c "processor" /proc/cpuinfo')
103 for i in range(self.num_cpus - 1):
106 self.assertFalse(self.disable_cpu(self.num_cpus - 1))
108 # Ensure all CPUs are re-enabled
116 self.check_devices("rtc", 1, ["rtc-pl031"])
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
8 /* U-Boot - Startup Code for PowerPC based Embedded Boards
11 * The processor starts at 0x00000100 and the code is executed
23 #include <asm-offsets.h>
33 #include <asm/u-boot.h>
60 * r3 - 1st arg to board_init(): IMMP pointer
61 * r4 - 2nd arg to board_init(): boot flag
64 .long 0x27051956 /* U-Boot Magic Number */
76 /*----------------------------------------------------------------------*/
84 /*----------------------------------------------------------------------*/
[all …]

12345