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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
[all …]
H A Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
19 controller, a dedicated local power/sleep controller etc. The DSP processor
20 cores in the K3 SoCs are usually either a TMS320C66x CorePac processor or a
[all …]
H A Dti,keystone-rproc.txt5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
10 a dedicated local power/sleep controller etc. The DSP processor core in
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
15 Each DSP Core sub-system is represented as a single DT node, and should also
17 or optional properties that enable the OS running on the host processor (ARM
18 CorePac) to perform the device management of the remote processor and to
19 communicate with the remote processor.
22 --------------------
25 - compatible: Should be one of the following,
[all …]
H A Dti,davinci-rproc.txt4 Binding status: Unstable - Subject to changes for DT representation of clocks
7 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
8 is used to offload some of the processor-intensive tasks or algorithms, for
11 The processor cores in the sub-system usually contain additional sub-modules
13 controller, a dedicated local power/sleep controller etc. The DSP processor
18 Each DSP Core sub-system is represented as a single DT node.
21 --------------------
24 - compatible: Should be one of the following,
25 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
27 - reg: Should contain an entry for each value in 'reg-names'.
[all …]
H A Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI K3 R5F processor subsystems
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
15 external to the various processor subsystems and is connected on an
21 controller within a processor subsystem, and there can be more than one line
22 going to a specific processor's interrupt controller. The interrupt line
35 lines can also be routed to different processor sub-systems on DRA7xx as they
40 to different processor subsystems over a limited number of common interrupt
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dtscs454.c1 // SPDX-License-Identifier: GPL-2.0
2 // tscs454.c -- TSCS454 ALSA SoC Audio driver
21 #include <sound/soc-dapm.h>
50 pll->id = id; in pll_init()
51 mutex_init(&pll->lock); in pll_init()
66 aif->id = id; in aif_init()
85 cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; in init_coeff_ram_cache()
90 init_coeff_ram_cache(ram->cache); in coeff_ram_init()
91 mutex_init(&ram->lock); in coeff_ram_init()
103 status->streams |= mask; in set_aif_status_active()
[all …]
/openbmc/linux/Documentation/userspace-api/media/
H A Dglossary.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
45 **Digital Signal Processor**
51 **Field-programmable Gate Array**
56 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
65 together make a larger user-facing functional peripheral. For
73 **Inter-Integrated Circuit**
75 A multi-master, multi-slave, packet switched, single-ended,
77 like sub-device hardware components.
79 See http://www.nxp.com/docs/en/user-guide/UM10204.pdf.
101 **Image Signal Processor**
[all …]
/openbmc/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv11 1, 0, EAX, 13:12, processor, Processor Type
22 1, 0, ECX, 2, dtes64, DS area uses 64-bit layout
33 1, 0, ECX, 13, cmpxchg16b, 'CMPXCHG16B - Compare and Exchange Bytes' supported
36 1, 0, ECX, 17, pcid, Process-Context Identifiers feature present
43 …1, 0, ECX, 24, tsc_deadline_timer, LAPIC supports one-shot operation using a TSC deadline …
45 1, 0, ECX, 26, xsave, XSAVE/XRSTOR processor extended states (XSETBV/XGETBV/XCR0)
48 1, 0, ECX, 29, f16c, 16-bit floating-point conversion instruction supported
52 1, 0, EDX, 1, vme, Virtual-8086 Mode Enhancement
67 1, 0, EDX, 17, pse36, 36-Bit Page Size Extension
68 1, 0, EDX, 18, psn, Processor Serial Number
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dhead-nommu.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-nommu.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2006 Hyok S. Choi
8 * Common kernel startup code (non-paged MM)
16 #include <asm/asm-offsets.h>
25 * ---------------------------
28 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
31 * See linux/arch/arm/tools/mach-types for the complete list of machine
46 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
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H A Dhead-common.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-common.S
5 * Copyright (C) 1994-2002 Russell King
18 #define OF_DT_MAGIC 0xedfe0dd0 /* 0xd00dfeed in big-endian */
71 * r0 = cp#15 control register (exc_ret for M-class)
74 * r9 = processor ID
97 sub r2, r2, r1
104 sub r2, r1, r0
112 str r9, [r0] @ Save processor ID
149 .size __mmap_switched_data, . - __mmap_switched_data
[all …]
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1994-2002 Russell King
9 * Kernel startup code for all 32-bit CPUs
19 #include <asm/asm-offsets.h>
48 .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
69 sub \rd, \rd, #PG_DIR_SIZE
74 * ---------------------------
77 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
83 * See linux/arch/arm/tools/mach-types for the complete list of machine
87 * crap here - that's what the boot loader (or in extreme, well justified
[all …]
/openbmc/linux/Documentation/admin-guide/media/
H A Dqcom_camss.rst1 .. SPDX-License-Identifier: GPL-2.0
9 ------------
25 ----------------------------------
30 - 2 / 3 CSIPHY modules. They handle the Physical layer of the CSI2 receivers.
32 - 2 / 4 CSID (CSI Decoder) modules. They handle the Protocol and Application
36 - ISPIF (ISP Interface) module. Handles the routing of the data streams from
38 - 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
48 -----------------------
52 - Input from camera sensor via CSIPHY;
53 - Generation of test input data by the TG in CSID;
[all …]
/openbmc/qemu/docs/specs/
H A Dppc-xive.rst5 The POWER9 processor comes with a new interrupt controller
19 The XIVE IC is composed of three sub-engines, each taking care of a
22 - Interrupt Virtualization Source Engine (IVSE), or Source Controller
23 (SC). These are found in PCI PHBs, in the Processor Service
25 controller for the core IPIs and other sub-chips (NX, CAP, NPU) of
26 the chip/processor. They are configured to feed the IVRE with
28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
32 - Interrupt Virtualization Presentation Engine (IVPE) or Presentation
40 +------------------------------------+ IPIs
41 | +---------+ +---------+ +--------+ | +-------+
[all …]
/openbmc/phosphor-mrw-tools/
H A DInventory.pm14 #Chips that are modeled as modules (card-chip together)
22 sub getInventory
44 #This will pick up FRUs and other chips like the BMC and processor.
45 sub findItems
49 for my $target (sort keys %{$targetObj->getAllTargets()}) {
53 if (!$targetObj->isBadAttribute($target, "TYPE")) {
54 $type = $targetObj->getAttribute($target, "TYPE");
57 if (!$targetObj->isBadAttribute($target, "RU_TYPE")) {
58 $ruType = $targetObj->getAttribute($target, "RU_TYPE");
73 #is a card-chip instance that plugs into a connector on the
[all …]
H A Dinventory.pl27 my %includedTargetTypes = ("chip-sp-bmc" => 1,
28 "chip-apss-psoc" => 1);
41 my $targetObj = Targets->new;
42 $targetObj->loadXML($serverwizFile);
44 foreach $target (sort keys %{ $targetObj->getAllTargets() })
46 $type = $targetObj->getType($target);
53 if (!$targetObj->isBadAttribute($target, "FRU_NAME")) {
54 $fruName = $targetObj->getAttribute($target,"FRU_NAME");
57 my $targetType = $targetObj->getTargetType($target);
90 my $json = JSON->new;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Domap-ocp2scp.txt1 * OMAP OCP2SCP - ocp interface to scp interface
4 - compatible : Should be "ti,am437x-ocp2scp" for AM437x processor
5 Should be "ti,omap-ocp2scp" for all others
6 - reg : Address and length of the register set for the device
7 - #address-cells, #size-cells : Must be present if the device has sub-nodes
8 - ranges : the child address space are mapped 1:1 onto the parent address space
9 - ti,hwmods : must be "ocp2scp_usb_phy"
11 Sub-nodes:
12 All the devices connected to ocp2scp are described using sub-node to ocp2scp
15 compatible = "ti,omap-ocp2scp";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,kpss-gcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
10 - Christian Marangi <ansuelsmth@gmail.com>
13 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
15 to the kpss-gcc registers.
20 - enum:
21 - qcom,kpss-gcc-ipq8064
[all …]
/openbmc/u-boot/doc/
H A DREADME.blackfin1 Notes for the Blackfin architecture port of Das U-Boot
8 Blackfin Processors embody a new breed of 16/32-bit embedded processor, ideally
9 suited for products where a convergence of capabilities are necessary -
10 multi-format audio, video, voice and image processing; multi-mode baseband and
11 packet processing; control processing; and real-time security. The Blackfin's
16 The Blackfin processor is wholly developed by Analog Devices Inc.
26 In particular, bug reports, feature requests, help etc... for Das U-Boot are
27 handled in the Das U-Boot sub project:
28 http://blackfin.uclinux.org/gf/project/u-boot
38 the Blackfin processor. You can obtain such a cross-compiler here:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dzii,rave-sp.txt1 Zodiac Inflight Innovations RAVE Supervisory Processor
3 RAVE Supervisory Processor communicates with SoC over UART. It is
9 - compatible: Should be one of:
10 - "zii,rave-sp-niu"
11 - "zii,rave-sp-mezz"
12 - "zii,rave-sp-esb"
13 - "zii,rave-sp-rdu1"
14 - "zii,rave-sp-rdu2"
16 - current-speed: Should be set to baud rate SP device is using
18 RAVE SP consists of the following sub-devices:
[all …]
/openbmc/linux/drivers/crypto/ccp/
H A Dsp-dev.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD Secure Processor driver
5 * Copyright (C) 2017-2018 Advanced Micro Devices, Inc.
22 #include "ccp-dev.h"
23 #include "sp-dev.h"
29 MODULE_DESCRIPTION("AMD Secure Processor driver");
31 /* List of SPs, SP count, read-write access lock, and access functions
39 /* Ever-increasing value to produce unique unit numbers */
48 list_add_tail(&sp->entry, &sp_units); in sp_add_device()
59 list_del(&sp->entry); in sp_del_device()
[all …]
/openbmc/linux/arch/sparc/kernel/
H A Dhead_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
25 #include <asm/processor.h>
93 * SILO can invoke us with 32-bit address masking enabled,
125 .asciz "call-method"
133 .asciz "SUNW,set-trap-table"
137 .asciz "SUNW,UltraSPARC-T"
139 .asciz "SPARC-"
141 .asciz "SPARC64-X"
169 mov (1b - prom_peer_name), %l1
170 sub %l0, %l1, %l1
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/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME2 --------
6 ------------------
7 The QorIQ LS1 family, which includes the LS1021A communications processor,
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
[all …]
/openbmc/u-boot/arch/x86/lib/
H A Dscu.c1 // SPDX-License-Identifier: GPL-2.0+
38 * scu_ipc_send_command() - send command to SCU
43 * A write to this register results in an interrupt to the SCU core processor
49 writel(cmd, &regs->cmd); in scu_ipc_send_command()
53 * scu_ipc_check_status() - check status of last command
68 status = readl(&regs->status); in scu_ipc_check_status()
73 } while (--loop_count); in scu_ipc_check_status()
75 return -ETIMEDOUT; in scu_ipc_check_status()
79 return -EIO; in scu_ipc_check_status()
85 static int scu_ipc_cmd(struct ipc_regs *regs, u32 cmd, u32 sub, in scu_ipc_cmd() argument
[all …]
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME2 --------
6 ------------------
7 The QorIQ LS1 family, which includes the LS1021A communications processor,
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
[all …]

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