Lines Matching +full:sub +full:- +full:processor
5 The POWER9 processor comes with a new interrupt controller
19 The XIVE IC is composed of three sub-engines, each taking care of a
22 - Interrupt Virtualization Source Engine (IVSE), or Source Controller
23 (SC). These are found in PCI PHBs, in the Processor Service
25 controller for the core IPIs and other sub-chips (NX, CAP, NPU) of
26 the chip/processor. They are configured to feed the IVRE with
28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
32 - Interrupt Virtualization Presentation Engine (IVPE) or Presentation
40 +------------------------------------+ IPIs
41 | +---------+ +---------+ +--------+ | +-------+
42 | |IVRE | |Common Q | |IVPE |----> | CORES |
43 | | esb | | | | |----> | |
44 | | eas | | Bridge | | tctx |----> | |
46 +------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+
47 | RAM | +------------------|-----------------+ | | |
50 | | +--------------------v------------------------v-v-v--+ other
51 | <--+ Power Bus +--> chips
52 | esb | +---------+-----------------------+------------------+
54 | end | +--|------+ |
55 | nvt | +----+----+ | +----+----+
56 +------+ |IVSE | | |IVSE |
58 | PQ-bits | | | PQ-bits |
59 | local |-+ | in VC |
60 +---------+ +---------+
64 PQ-bits: 2 bits source state machine (P:pending Q:queued)
74 --------------------
76 Each of the sub-engines uses a set of tables to redirect interrupts
81 +-------+
83 or +------>|entries|
85 Memory | +-------+
88 +-------------------------------------------------+
90 Hypervisor +------+ +---+--+ +---+--+ +------+
92 (skiboot) +----+-+ +----+-+ +----+-+ +------+
95 +-------------------------------------------------+
98 +----|--|--------|--|--------|--|-+ +-|-----+ +------+
100 IPI or ---+ + v + v + v |---| + .. |-----> |
102 | IVRE | | IVPE | +------+
103 +---------------------------------+ +-------+
106 The IVSE have a 2-bits state machine, P for pending and Q for queued,
113 a notification path to a CPU and an in-memory Event Queue, in which
118 the processor HW threads. It maintains the interrupt context state of
122 -----------------------------
127 - hypervisor exception
128 - O/S exception
129 - Event-Based Branch (user level)
130 - msgsnd (doorbell)
137 - Interrupt Priority Register (PIPR)
138 - Interrupt Pending Buffer (IPB)
139 - Current Processor Priority (CPPR)
140 - Notification Source Register (NSR)
166 The PIPR is then compared to the Current Processor Priority
187 the IVPE sub-engine which does a CAM scan to find a CPU to deliver the