stores (full) in projects: openbmc - OpenGrok search results

Searched full:stores (Results 1 – 25 of 1608) sorted by relevance

/openbmc/linux/Documentation/ABI/testing/
H A D	sysfs-bus-mei	`6 Description: Stores the same MODALIAS value emitted by uevent 13 Description: Stores mei client device name 20 Description: Stores mei client device uuid 27 Description: Stores mei client protocol version 34 Description: Stores mei client maximum number of connections 41 Description: Stores mei client fixed address, if any 48 Description: Stores mei client vtag support status 55 Description: Stores mei client maximum message length`
/openbmc/linux/Documentation/core-api/
H A D	refcount-vs-atomic.rst	42 stores (all po-earlier instructions) on the same CPU are completed 44 It also guarantees that all po-earlier stores on the same CPU 45 and all propagated stores from other CPUs must propagate to all 50 stores (all po-earlier instructions) on the same CPU are completed 52 stores on the same CPU and all propagated stores from other CPUs 58 stores (all po-later instructions) on the same CPU are 60 po-later stores on the same CPU must propagate to all other CPUs 67 then further stores are ordered against this operation. 68 Control dependency on stores are not implemented using any explicit 69 barriers, but rely on CPU not to speculate on stores. This is only [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A D	uncore-memory.json	3 …"BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM ca… 11 …"BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM ca… 19 …"BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM c… 27 …"BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM c… 49 …id memory mode, this event counts all read requests as well as streaming stores that hit or miss i… 63 …hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, r…
/openbmc/linux/tools/memory-model/Documentation/
H A D	control-dependencies.txt	11 One such challenge is that control dependencies order only later stores. 31 However, stores are not speculated. This means that ordering is 43 the compiler might fuse the store to "b" with other stores. Worse yet, 60 identical stores on both branches of the "if" statement as follows: 104 guaranteed only when the stores differ, for example: 212 only to the stores in the then-clause and else-clause of the "if" statement 219 () Control dependencies can order prior loads against later stores. 221 Not prior loads against later loads, nor prior stores against 224 stores and later loads, smp_mb(). 226 () If both legs of the "if" statement contain identical stores to [all …]
H A D	explanation.txt	103 device, stores it in a buffer, and sets a flag to indicate the buffer 135 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1 141 This pattern of memory accesses, where one CPU stores values to two 198 it, as loads can obtain values only from earlier stores. 203 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2 207 P0 stores 1 to buf before storing 1 to flag, since it executes 223 each CPU stores to its own shared location and then loads from the 271 W: P0 stores 1 to flag executes before 274 Z: P0 stores 1 to buf executes before 275 W: P0 stores 1 to flag. [all …]
/openbmc/linux/tools/perf/util/
H A D	mem-events.h	`61 u32 store; /* count of all stores in trace / 62 u32 st_uncache; / stores to uncacheable address / 64 u32 st_l1hit; / count of stores that hit L1D / 65 u32 st_l1miss; / count of stores that miss L1D / 66 u32 st_na; / count of stores with memory level is not available / 89 u32 nomap; / count of load/stores with no phys addrs */`
/openbmc/linux/arch/powerpc/include/asm/
H A D	barrier.h	`19 * providing an ordering (separately) for (a) cacheable stores and (b) 20 * loads and stores to non-cacheable memory (e.g. I/O devices). 22 * mb() prevents loads and stores being reordered across this point. 24 * wmb() prevents stores being reordered across this point. 32 * doesn't order loads with respect to previous stores. Lwsync can be 109 * pmem_wmb() ensures that all stores for which the modification`
/openbmc/linux/arch/ia64/include/asm/
H A D	barrier.h	`23 * wmb(): Guarantees that all preceding stores to memory- 25 * stores and that all following stores will be 26 * visible only after all previous stores. 52 * IA64 GCC turns volatile stores into st.rel and volatile loads into ld.acq no`
/openbmc/linux/arch/mips/include/asm/octeon/
H A D	octeon.h	211 * stores; if clear, SYNCWS and SYNCS only order 212 * unmarked stores. SYNCWSMARKED has no effect when 222 * loads/stores can use XKPHYS addresses with 225 /* R/W If set (and UX set), user-level loads/stores 229 * loads/stores can use XKPHYS addresses with 232 /* R/W If set (and UX set), user-level loads/stores 235 /* R/W If set, all stores act as SYNCW (NOMERGE must 238 /* R/W If set, no stores merge, and all stores reach 265 /* R/W If set, CVMSEG is available for loads/stores in 268 /* R/W If set, CVMSEG is available for loads/stores in [all …]
/openbmc/linux/tools/arch/powerpc/include/asm/
H A D	barrier.h	`15 * providing an ordering (separately) for (a) cacheable stores and (b) 16 * loads and stores to non-cacheable memory (e.g. I/O devices). 18 * mb() prevents loads and stores being reordered across this point. 20 * wmb() prevents stores being reordered across this point.`
/openbmc/linux/arch/sparc/kernel/
H A D	dtlb_prot.S	`12 * [TL == 0] 1) User stores to readonly pages. 13 * [TL == 0] 2) Nucleus stores to user readonly pages. 14 * [TL > 0] 3) Nucleus stores to user readonly stack frame. 20 membar #Sync ! Synchronize stores`
/openbmc/linux/tools/arch/ia64/include/asm/
H A D	barrier.h	`25 * wmb(): Guarantees that all preceding stores to memory- 27 * stores and that all following stores will be 28 * visible only after all previous stores.`
/openbmc/linux/tools/testing/selftests/kvm/x86_64/
H A D	pmu_event_filter_test.c	112 uint64_t stores; member 505 const uint64_t stores = rdmsr(msr_base + 1); in masked_events_guest_test() local 516 pmc_results.stores = rdmsr(msr_base + 1) - stores; in masked_events_guest_test() 588 * For each test, the guest enables 3 PMU counters (loads, stores, 589 * loads + stores). The filter is then set in KVM with the masked events 610 .msg = "Only allow stores.", 619 .msg = "Only allow loads + stores.", 629 .msg = "Only allow loads and stores.", 640 .msg = "Only allow loads and loads + stores.", 650 .msg = "Only allow stores and loads + stores.", [all …]
/openbmc/linux/arch/sparc/lib/
H A D	M7memset.S	32 * For small 6 or fewer bytes stores, bytes will be stored. 34 * For less than 32 bytes stores, align the address on 4 byte boundary. 41 * Using BIS stores, set the first long word of each 46 * Using BIS stores, set the first long word of each of 66 * similar to prefetching for normal stores. 71 * BIS stores must be followed by a membar #StoreStore. The benefit of 79 * store and the final stores. 167 ! Use long word stores. 179 and %o2, 63, %o3 ! %o3 = bytes left after blk stores. 187 ! initial cache-clearing stores
/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A D	translation.json	`10 …efDescription": "Stores completed from S2Q (2nd-level store queue). This event includes regular st…`
/openbmc/linux/tools/include/linux/
H A D	refcount.h	`25 * future stores against the inc, this ensures we'll never modify the object 29 * stores will be issued before, it also provides a control dependency, which 33 * succeeded. This means the stores aren't fully ordered, but this is fine 73 * and thereby orders future stores. See the comment on top. 116 * Provides release memory ordering, such that prior loads and stores are done`
/openbmc/linux/include/linux/
H A D	refcount.h	73 * future stores against the inc, this ensures we'll never modify the object 77 * stores will be issued before, it also provides a control dependency, which 81 * succeeded. This means the stores aren't fully ordered, but this is fine 177 * and thereby orders future stores. See the comment on top. 213 * and thereby orders future stores. See the comment on top. 239 * and thereby orders future stores. See the comment on top. 297 * Provides release memory ordering, such that prior loads and stores are done 325 * Provides release memory ordering, such that prior loads and stores are done 354 * Provides release memory ordering, such that prior loads and stores are done
/openbmc/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	virtual-memory.json	101 …Counts the number of first level TLB misses but second level hits due to stores that did not start… 109 "BriefDescription": "Stores that miss the DTLB and hit the STLB.", 112 …"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)… 139 …n": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it m… 148 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This i… 157 …tion": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies addr… 166 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i… 172 …ounts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.", 175 … the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH…
/openbmc/linux/include/uapi/sound/
H A D	snd_sst_tokens.h	`34 * %SKL_TKN_U8_CORE_ID: Stores module affinity value.Can take 65 * %SKL_TKN_U16_PIN_INST_ID: Stores the pin instance id 67 * %SKL_TKN_U16_MOD_INST_ID: Stores the mdule instance id 73 * %SKL_TKN_U32_OBS: Stores Output Buffer size 75 * %SKL_TKN_U32_IBS: Stores input buffer size 84 * %SKL_TKN_U32_PIPE_ID: Stores the pipe id`
/openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	virtual-memory.json	60 "BriefDescription": "Stores that miss the DTLB and hit the STLB.", 63 …"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)… 80 …n": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it m… 88 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This i… 96 …tion": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies addr… 104 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i…
/openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	virtual-memory.json	57 …"BriefDescription": "Counts the number of page walks due to stores that miss the PDE (Page Directo… 64 …Counts the number of first level TLB misses but second level hits due to stores that did not start… 74 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl… 82 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl… 90 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl… 98 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl… 103 …ounts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.", 106 … the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A pa…
/openbmc/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	virtual-memory.json	57 …"BriefDescription": "Counts the number of page walks due to stores that miss the PDE (Page Directo… 64 …Counts the number of first level TLB misses but second level hits due to stores that did not start… 74 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl… 82 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl… 90 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl… 98 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl… 103 …ounts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.", 106 … the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A pa…
/openbmc/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A D	virtual-memory.json	76 "BriefDescription": "Stores that miss the DTLB and hit the STLB.", 79 …"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)… 98 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl… 107 …n": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it m… 116 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This i… 125 …tion": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies addr… 134 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i…
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A D	pixfmt-yuv-planar.rst	13 stores the Y components. The second plane is the chroma plane and stores the 311 ``V4L2_PIX_FMT_NV12MT_16X16`` is similar to ``V4L2_PIX_FMT_NV12M`` but stores 312 pixels in 2D 16x16 tiles, and stores tiles linearly in memory. 316 ``V4L2_PIX_FMT_NV12MT`` is similar to ``V4L2_PIX_FMT_NV12M`` but stores 317 pixels in 2D 64x32 tiles, and stores 2x2 groups of tiles in 325 ``V4L2_PIX_FMT_NV12_4L4`` stores pixels in 4x4 tiles, and stores 330 ``V4L2_PIX_FMT_NV12_16L16`` stores pixels in 16x16 tiles, and stores 335 ``V4L2_PIX_FMT_NV12_32L32`` stores pixels in 32x32 tiles, and stores 340 ``V4L2_PIX_FMT_NV12M_8L128`` is similar to ``V4L2_PIX_FMT_NV12M`` but stores 341 pixels in 2D 8x128 tiles, and stores tiles linearly in memory. [all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	virtual-memory.json	60 "BriefDescription": "Stores that miss the DTLB and hit the STLB.", 63 …"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)… 80 …n": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it m… 88 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This i… 96 …tion": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies addr… 104 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i…

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