1*12f06532SRichard Henderson /* SPDX-License-Identifier: MIT */ 2*12f06532SRichard Henderson /* 3*12f06532SRichard Henderson * Define target-specific memory model 4*12f06532SRichard Henderson * Copyright (c) 2008 Fabrice Bellard 5*12f06532SRichard Henderson */ 6*12f06532SRichard Henderson 7*12f06532SRichard Henderson #ifndef TCG_TARGET_MO_H 8*12f06532SRichard Henderson #define TCG_TARGET_MO_H 9*12f06532SRichard Henderson 10*12f06532SRichard Henderson /* 11*12f06532SRichard Henderson * This defines the natural memory order supported by this architecture 12*12f06532SRichard Henderson * before guarantees made by various barrier instructions. 13*12f06532SRichard Henderson * 14*12f06532SRichard Henderson * The x86 has a pretty strong memory ordering which only really 15*12f06532SRichard Henderson * allows for some stores to be re-ordered after loads. 16*12f06532SRichard Henderson */ 17*12f06532SRichard Henderson #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 18*12f06532SRichard Henderson 19*12f06532SRichard Henderson #endif 20