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Searched +full:stm32 +full:- +full:timer +full:- +full:counter (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp157c.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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/openbmc/u-boot/drivers/timer/
H A DKconfig1 menu "Timer Support"
3 config TIMER config
4 bool "Enable driver model for timer drivers"
7 Enable driver model for timer access. It uses the same API as
8 lib/time.c, but now implemented by the uclass. The first timer
9 will be used. The timer is usually a 32 bits free-running up
10 counter. There may be no real tick, and no timer interrupt.
13 bool "Enable driver model for timer drivers in SPL"
14 depends on TIMER && SPL
16 Enable support for timer drivers in SPL. These can be used to get
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H A Dstm32_timer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
11 #include <timer.h>
15 /* Timer control1 register */
56 struct stm32_timer_regs *regs = priv->base; in stm32_timer_get_count()
58 *count = readl(&regs->cnt); in stm32_timer_get_count()
75 return -EINVAL; in stm32_timer_probe()
77 priv->base = (struct stm32_timer_regs *)addr; in stm32_timer_probe()
89 regs = priv->base; in stm32_timer_probe()
91 /* Stop the timer */ in stm32_timer_probe()
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/openbmc/u-boot/arch/arm/mach-stm32mp/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
11 #include <asm/arch/stm32.h>
48 * - boot instance = bit 31:16
49 * - boot device = bit 15:0
109 * Bit 23 ITAMP8E: monotonic counter overflow in security_init()
125 /* Freeze IWDG2 if Cortex-A7 is in debug mode */ in dbgmcu_init()
165 /* early armv7 timer init: needed for polling */ in arch_cpu_init()
178 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; in arch_cpu_init()
190 /* Enable D-cache. I-cache is already enabled in start.S */ in enable_caches()
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/openbmc/u-boot/drivers/mmc/
H A Dstm32_sdmmc2.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
48 #define SDMMC_DTIMER 0x24 /* SDMMC data timer */
51 #define SDMMC_DCOUNT 0x30 /* SDMMC data counter */
201 data_ctrl = (__ilog2(data->blocksize) << in stm32_sdmmc2_start_data()
205 if (data->flags & MMC_DATA_READ) { in stm32_sdmmc2_start_data()
207 idmabase0 = (u32)data->dest; in stm32_sdmmc2_start_data()
209 idmabase0 = (u32)data->src; in stm32_sdmmc2_start_data()
213 writel(SDMMC_CMD_TIMEOUT, priv->base + SDMMC_DTIMER); in stm32_sdmmc2_start_data()
216 writel(ctx->data_length, priv->base + SDMMC_DLEN); in stm32_sdmmc2_start_data()
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/openbmc/qemu/
H A DMAINTAINERS10 consult qemu-devel and not any specific individual privately.
23 W: Web-page with status/info
59 ------------------------------
63 L: qemu-devel@nongnu.org
72 R: Philippe Mathieu-Daudé <philmd@linaro.org>
75 F: docs/devel/build-environment.rst
76 F: docs/devel/code-of-conduct.rst
78 F: docs/devel/conflict-resolution.rst
80 F: docs/devel/submitting-a-patch.rst
81 F: docs/devel/submitting-a-pull-request.rst
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/openbmc/
Dopengrok1.0.log1 2025-12-15 03:01:05.452-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-12-15 03:01:05.518-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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Dopengrok2.0.log1 2025-12-14 03:01:07.427-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-12-14 03:01:07.482-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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