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/openbmc/linux/drivers/hwtracing/intel_th/
H A Dsth.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Intel Corporation.
16 #include <linux/stm.h>
22 void __iomem *base; member
26 struct stm_data stm; member
33 struct intel_th_channel __iomem *sw_map = sth->channels; in sth_channel()
35 return &sw_map[(master - sth->stm.sw_start) * sth->stm.sw_nchannels + in sth_channel()
70 struct sth_device *sth = container_of(stm_data, struct sth_device, stm); in sth_stm_packet()
73 u64 __iomem *outp = &out->Dn; in sth_stm_packet()
96 writeb_relaxed(*payload, sth->base + reg); in sth_stm_packet()
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/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-stm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
8 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
12 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
15 * generic STM API by Chunyan Zhang
16 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
24 #include <linux/coresight-stm.h>
31 #include <linux/stm.h>
33 #include "coresight-priv.h"
34 #include "coresight-trace-id.h"
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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-stm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
23 The STM is a trace source that is integrated into a CoreSight system, designed
24 primarily for high-bandwidth trace of instrumentation embedded into software.
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/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dsc9836.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #address-cells = <2>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a53";
23 enable-method = "psci";
28 compatible = "arm,cortex-a53";
30 enable-method = "psci";
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
42 compatible = "arm,cortex-a53";
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H A Dsc9860.dtsi6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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/openbmc/linux/Documentation/trace/coresight/
H A Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
43 | |->### | ! | |->### | ! | ! . | || DAP ||
49 *****************************************************************<-|
63 | * ===== F =====<---------|
65 |-->:: CTI ::<!! === N ===
69 |------>&& ETB &&<......II I =======
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/openbmc/u-boot/include/
H A Dflash.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2000-2005
14 /*-----------------------------------------------------------------------
45 const char *name; /* human-readable name */
50 #ifdef CONFIG_CFI_FLASH /* DM-specific parts */
52 phys_addr_t base; member
115 extern ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info);
116 extern int jedec_flash_match(flash_info_t *info, ulong base);
120 /*-----------------------------------------------------------------------
134 /*-----------------------------------------------------------------------
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/openbmc/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
31 #mbox-cells = <1>;
33 clock-names = "apb_pclk";
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/openbmc/linux/arch/x86/include/asm/
H A Dhyperv-tlfs.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
89 * than inter-processor interrupts
94 * EOI, ICR and TPR rather than their memory-mapped counterparts
97 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
107 * Recommend not using Auto End-Of-Interrupt feature
119 /* Indicates that the hypervisor is nested within a Hyper-V partition. */
155 * flushes gva -> hpa mapping entries. To flush the TLB entries derived
176 /* Hyper-V specific model specific registers (MSRs) */
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/openbmc/linux/drivers/spi/
H A Dspi-st-ssc4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
55 void __iomem *base; member
74 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
77 count = spi_st->words_remaining; in ssc_write_tx_fifo()
80 if (spi_st->tx_ptr) { in ssc_write_tx_fifo()
81 if (spi_st->bytes_per_word == 1) { in ssc_write_tx_fifo()
82 word = *spi_st->tx_ptr++; in ssc_write_tx_fifo()
84 word = *spi_st->tx_ptr++; in ssc_write_tx_fifo()
85 word = *spi_st->tx_ptr++ | (word << 8); in ssc_write_tx_fifo()
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/openbmc/linux/arch/arm/kernel/
H A Dentry-header.S1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/asm-offsets.h>
9 #include <asm/uaccess-asm.h>
13 @ -----------------
59 * ARMv7-M exception entry/exit macros.
86 @ we cannot rely on r0-r3 and r12 matching the value saved in the
87 @ exception frame because of tail-chaining. So these have to be
89 ldmia r12!, {r0-r3}
94 sub sp, #PT_REGS_SIZE-S_IP
95 stmdb sp!, {r0-r11}
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/openbmc/linux/arch/arm/mm/
H A Dalignment.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Modifications for ARM processor (c) 1995-2001 Russell King
8 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
32 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
52 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
72 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
104 * LDM, STM, LDRD and STRD still need to be handled. in safe_usermode()
107 * CPUs since we spin re-faulting the instruction without in safe_usermode()
158 return -EFAULT; in alignment_proc_write()
160 ai_usermode = safe_usermode(mode - '0', true); in alignment_proc_write()
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/openbmc/linux/drivers/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 # Rewritten to use lists instead of if-statements.
11 MAKEFLAGS += --include-dir=$(srctree)
14 obj-y += cache/
15 obj-y += irqchip/
16 obj-y += bus/
18 obj-$(CONFIG_GENERIC_PHY) += phy/
21 obj-$(CONFIG_PINCTRL) += pinctrl/
22 obj-$(CONFIG_GPIOLIB) += gpio/
23 obj-y += pwm/
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/openbmc/u-boot/drivers/mtd/
H A Djedec_flash.c1 // SPDX-License-Identifier: GPL-2.0+
54 /* STM */
97 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
101 * data widths automatically initialized - that means that
133 .addr2 = 0x0000 /* is used - must be last entry */
154 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
405 …tic inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base) in fill_info() argument
413 size_ratio = info->portwidth / info->chipwidth; in fill_info()
415 debug("Found JEDEC Flash: %s\n", jedec_entry->name); in fill_info()
416 info->vendor = jedec_entry->CmdSet; in fill_info()
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/openbmc/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved
25 #include <soc/tegra/tegra-cbb.h>
108 struct tegra_cbb base; member
130 return container_of(cbb, struct tegra234_cbb, base); in to_tegra234_cbb()
141 if (!cbb->fabric->firewall_base || in tegra234_cbb_write_access_allowed()
142 !cbb->fabric->firewall_ctl || in tegra234_cbb_write_access_allowed()
143 !cbb->fabric->firewall_wr_ctl) { in tegra234_cbb_write_access_allowed()
144 dev_info(&pdev->dev, "SoC data missing for firewall\n"); in tegra234_cbb_write_access_allowed()
148 if ((cbb->fabric->firewall_ctl > FIREWALL_APERTURE_SZ) || in tegra234_cbb_write_access_allowed()
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/openbmc/linux/crypto/
H A Dansi_cprng.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 * See http://csrc.nist.gov/groups/STM/cavp/documents/rng/931rngext.pdf
91 hexdump("Input DT: ", ctx->DT, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
92 hexdump("Input I: ", ctx->I, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
93 hexdump("Input V: ", ctx->V, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
106 memcpy(tmp, ctx->DT, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
107 output = ctx->I; in _get_more_prng_bytes()
117 xor_vectors(ctx->I, ctx->V, tmp, DEFAULT_BLK_SZ); in _get_more_prng_bytes()
119 output = ctx->rand_data; in _get_more_prng_bytes()
126 if (!memcmp(ctx->rand_data, ctx->last_rand_data, in _get_more_prng_bytes()
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/openbmc/qemu/hw/arm/
H A Dsmmuv3-internal.h2 * ARM SMMUv3 support - Internal API
4 * Copyright (C) 2014-2016 Broadcom Corporation
25 #include "hw/arm/smmu-common.h"
184 return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE); in smmu_enabled()
212 return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN); in smmuv3_eventq_irq_enabled()
217 return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN); in smmuv3_gerror_irq_enabled()
222 #define Q_BASE(q) ((q)->base & SMMU_BASE_ADDR_MASK)
223 #define WRAP_MASK(q) (1 << (q)->log2size)
224 #define INDEX_MASK(q) (((1 << (q)->log2size)) - 1)
225 #define WRAP_INDEX_MASK(q) ((1 << ((q)->log2size + 1)) - 1)
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/thermal/thermal.h>
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H A Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/gpio/gpio.h>
13 interrupt-parent = <&intc>;
15 qcom,msm-id = <292 0x0>;
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H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
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/openbmc/linux/include/linux/
H A Dlibata.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2003-2005 Red Hat, Inc. All rights reserved.
4 * Copyright 2003-2005 Jeff Garzik
7 * as Documentation/driver-api/libata.rst
16 #include <linux/dma-mapping.h>
28 * Define if arch has non-standard setup. This is a _PCI_ standard
32 #include <asm/libata-portmap.h>
39 * compile-time options: to be removed as soon as all the drivers are
69 ATA_ALL_DEVICES = (1 << ATA_MAX_DEVICES) - 1,
72 ATA_SHT_THIS_ID = -1,
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/openbmc/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2_coresight.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2019-2022 HabanaLabs, Ltd.
13 #define COMPONENT_ID_INVALID ((u32)(-1))
45 * struct component_config_offsets - per cs_dbg unit - view off all related components indices
46 * @funnel_id: funnel id - index in debug_funnel_regs
47 * @etf_id: etf id - index in debug_etf_regs
48 * @stm_id: stm id - index in debug_stm_regs
49 * @spmu_id: spmu_id - index in debug_spmu_regs
51 * @bmon_ids: array of bmon id (max size - MAX_BMONS_PER_UNIT) index in debug_bmon_regs
1933 if (hdev->pldm) in gaudi2_coresight_timeout()
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/openbmc/linux/arch/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
150 The ARM series is a line of low-power-consumption RISC chip designs
152 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
153 manufactured, but legacy ARM-based PC hardware remains popular in
164 supported in LLD until version 14. The combined range is -/+ 256 MiB,
257 Patch phys-to-virt and virt-to-phys translation functions at
261 This can only be used with non-XIP MMU kernels where the base
307 bool "MMU-based Paged Memory Management Support"
310 Select if you want MMU-based virtualised addressing space
350 # https://github.com/llvm/llvm-project/issues/50764
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/openbmc/linux/drivers/net/ethernet/marvell/
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
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/openbmc/linux/include/uapi/drm/
H A Dhabanalabs_accel.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 * Copyright 2016-2022 HabanaLabs, Ltd.
15 * Defines that are asic-specific but constitutes as ABI between kernel driver
196 * stream id is a running number from 0 up to (N-1), where N is the number
657 * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is
684 * enum hl_device_status - Device status information.
716 * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command
718 * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event
719 * HL_NOTIFIER_EVENT_UNDEFINED_OPCODE - Indicates undefined operation code
720 * HL_NOTIFIER_EVENT_DEVICE_RESET - Indicates device requires a reset
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