/openbmc/u-boot/doc/ |
H A D | README.mpc85xx-spin-table | 1 Spin table in cache 3 As specified by ePAPR v1.1, the spin table needs to be in cached memory. After 4 DDR is initialized and U-Boot relocates itself into DDR, the spin table is 6 __secondary_start_page. For other cores to use the spin table, the booting 15 core 0 puts the physical address of the spin table (which is in release.S and 21 the new space. The new TLB covers the physical address of the spin table page, 22 with WIMGE =0b00100. Now secondary cores can keep polling the spin table 23 without stress DDR bus because both the code and the spin table is in cache.
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/openbmc/linux/arch/arm64/boot/dts/arm/ |
H A D | foundation-v8-spin-table.dtsi | 4 * ARMv8 Foundation model DTS (spin table configuration) 8 enable-method = "spin-table"; 9 cpu-release-addr = <0x0 0x8000fff8>; 13 enable-method = "spin-table"; 14 cpu-release-addr = <0x0 0x8000fff8>; 18 enable-method = "spin-table"; 19 cpu-release-addr = <0x0 0x8000fff8>; 23 enable-method = "spin-table"; 24 cpu-release-addr = <0x0 0x8000fff8>;
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H A D | rtsm_ve-aemv8a.dts | 1 // SPDX-License-Identifier: GPL-2.0 5 * Architecture Envelope Model (AEM) ARMv8-A 11 /dts-v1/; 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 17 #include "rtsm_ve-motherboard.dtsi" 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 36 #address-cells = <2>; 37 #size-cells = <0>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/arm/ |
H A D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 59 On 32-bit ARM v7 or later systems this property is 68 On ARM v8 64-bit systems this property is required 71 * If cpus node's #address-cells property is set to 2 79 * If cpus node's #address-cells property is set to 1 [all …]
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/openbmc/linux/drivers/gpu/drm/i915/gt/ |
H A D | selftest_mocs.c | 1 // SPDX-License-Identifier: MIT 17 struct drm_i915_mocs_table table; member 33 ce->ring_size = SZ_16K; in mocs_context_create() 43 err = -ETIME; in request_add_sync() 49 static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin) in request_add_spin() argument 55 if (spin && !igt_wait_for_spinner(spin, rq)) in request_add_spin() 56 err = -ETIME; in request_add_spin() 69 flags = get_mocs_settings(gt->i915, &arg->table); in live_mocs_init() 71 return -EINVAL; in live_mocs_init() 74 arg->l3cc = &arg->table; in live_mocs_init() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/cpu/ |
H A D | cpu-topology.txt | 6 1 - Introduction 12 - socket 13 - cluster 14 - core 15 - thread 18 symmetric multi-threading (SMT) is supported or not. 29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be 39 2 - cpu-map node 42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct 46 - cpu-map node [all …]
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/openbmc/linux/arch/arm64/boot/dts/apple/ |
H A D | t6002.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/interrupt-controller/apple-aic.h> 12 #include <dt-bindings/interrupt-controller/irq.h> 13 #include <dt-bindings/pinctrl/apple.h> 15 #include "multi-die-cpp.h" 17 #include "t600x-common.dtsi" 20 compatible = "apple,t6002", "apple,arm-platform"; 22 #address-cells = <2>; 23 #size-cells = <2>; [all …]
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H A D | t600x-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 11 #address-cells = <2>; 12 #size-cells = <2>; 15 #address-cells = <2>; 16 #size-cells = <0>; 18 cpu-map { 63 enable-method = "spin-table"; 64 cpu-release-addr = <0 0>; /* To be filled by loader */ 65 next-level-cache = <&l2_cache_0>; 66 i-cache-size = <0x20000>; [all …]
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H A D | t8103.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/interrupt-controller/apple-aic.h> 12 #include <dt-bindings/interrupt-controller/irq.h> 13 #include <dt-bindings/pinctrl/apple.h> 16 compatible = "apple,t8103", "apple,arm-platform"; 18 #address-cells = <2>; 19 #size-cells = <2>; 22 #address-cells = <2>; 23 #size-cells = <0>; [all …]
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/openbmc/u-boot/arch/arm/cpu/armv8/ |
H A D | Kconfig | 8 The default exception vector table is only used for the crash 15 bool "Enable multiple CPUs to enter into U-Boot" 21 CPUECTLR_EL1.SMPEN bit before U-Boot. 36 bool "Support spin-table enable method" 39 Say Y here to support "spin-table" enable method for booting Linux. 42 - Specify enable-method = "spin-table" in each CPU node in the 44 - Bring secondary CPUs into U-Boot proper in a board specific 46 secondary CPUs will spin in unprotected memory area because the 47 master CPU protects the relocated spin code. 49 U-Boot automatically does: [all …]
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H A D | spin_table.c | 1 // SPDX-License-Identifier: GPL-2.0+ 17 unsigned long rsv_size = &spin_table_reserve_end - in spin_table_update_dt() 22 return -ENODEV; in spin_table_update_dt() 33 * spin-table. Otherwise, just return successfully to not in spin_table_update_dt() 36 prop = fdt_getprop(fdt, offset, "enable-method", NULL); in spin_table_update_dt() 37 if (!prop || strcmp(prop, "spin-table")) in spin_table_update_dt() 48 ret = fdt_setprop_u64(fdt, offset, "cpu-release-addr", in spin_table_update_dt() 51 return -ENOSPC; in spin_table_update_dt() 56 return -ENOSPC; in spin_table_update_dt() 58 printf(" Reserved memory region for spin-table: addr=%lx size=%lx\n", in spin_table_update_dt()
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/openbmc/u-boot/arch/arm/dts/ |
H A D | bcm2837.dtsi | 9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 12 compatible = "brcm,bcm2836-l1-intc"; 14 interrupt-controller; 15 #interrupt-cells = <1>; 16 interrupt-parent = <&local_intc>; 21 compatible = "arm,armv7-timer"; 22 interrupt-parent = <&local_intc>; 27 always-on; 31 #address-cells = <1>; 32 #size-cells = <0>; [all …]
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/openbmc/linux/arch/arm64/boot/dts/altera/ |
H A D | socfpga_stratix10_swvp.dts | 1 // SPDX-License-Identifier: GPL-2.0 10 compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10"; 27 stdout-path = "serial1:115200n8"; 28 linux,initrd-start = <0x10000000>; 29 linux,initrd-end = <0x125c8324>; 39 enable-method = "spin-table"; 40 cpu-release-addr = <0x0 0x0000fff8>; 44 enable-method = "spin-table"; 45 cpu-release-addr = <0x0 0x0000fff8>; 49 enable-method = "spin-table"; [all …]
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/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
H A D | release.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 3 * Copyright 2008-2012 Freescale Semiconductor, Inc. 7 #include <asm-offsets.h> 101 /* Enable/invalidate the I-Cache */ 119 /* Enable/invalidate the D-Cache */ 137 #define toreset(x) (x - __secondary_start_page + 0xfffff000) 139 /* get our PIR to figure out our table entry */ 148 * 0-17 Reserved (logic 0s) 149 * 18-19 CHIP_ID, 2'b00 - SoC 1 150 * all others - reserved [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | s32v234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Copyright 2015-2016 Freescale Semiconductor, Inc. 4 * Copyright 2016-2018 NXP 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 23 #address-cells = <2>; 24 #size-cells = <0>; 28 compatible = "arm,cortex-a53"; [all …]
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/openbmc/linux/arch/arm64/boot/dts/microchip/ |
H A D | sparx5_pcb_common.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 14 enable-method = "spin-table"; 18 enable-method = "spin-table";
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/openbmc/linux/arch/arm/boot/dts/broadcom/ |
H A D | bcm2837.dtsi | 2 #include "bcm2835-common.dtsi" 10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 13 compatible = "brcm,bcm2836-l1-intc"; 15 interrupt-controller; 16 #interrupt-cells = <2>; 17 interrupt-parent = <&local_intc>; 21 arm-pmu { 22 compatible = "arm,cortex-a53-pmu"; 23 interrupt-parent = <&local_intc>; 28 compatible = "arm,armv7-timer"; [all …]
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/openbmc/linux/arch/arm64/boot/dts/toshiba/ |
H A D | tmpv7708.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 10 #include <dt-bindings/clock/toshiba,tmpv770x.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 18 #address-cells = <2>; 19 #size-cells = <2>; 22 #address-cells = <1>; 23 #size-cells = <0>; [all …]
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/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/css/ |
H A D | default.css | 4 body { padding-top: 50px; } 7 img.logo { height: 30px; vertical-align: bottom; } 10 .toaster-navbar-brand { float: left; margin: 7px 25px 0 0; } 11 .toaster-navbar-brand a.brand { color: #777; height: 50px; padding: 15px 5px 15px 15px; font-size: … 12 .toaster-navbar-brand > a { text-decoration: none; } 13 .toaster-navbar-brand > a.brand:hover { color: #5e5e5e; } 16 .glyphicon-info-sign { color: #777; font-size: 16px; } 17 .glyphicon-info-sign:hover { color: #999; cursor: pointer; } 19 /* Override the negative right margin for the navbar-right class */ 20 #new-project-button { margin-right: 0; } [all …]
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/openbmc/linux/drivers/clk/stm32/ |
H A D | clk-stm32-core.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved 7 #include <linux/clk-provider.h> 16 u32 *table; member 32 const struct clk_div_table *table; member 98 spinlock_t *lock; /* spin lock */ 108 spinlock_t *lock; /* spin lock */ 118 spinlock_t *lock; /* spin lock */ 130 spinlock_t *lock; /* spin lock */
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/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ |
H A D | mp.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 3 * Copyright 2014-2015, Freescale Semiconductor 10 * Each spin table element is defined as 18 * the actual spin table is an array of these structures
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/openbmc/linux/arch/powerpc/platforms/85xx/ |
H A D | smp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 * Copyright 2006-2008, 2011-2012, 2015 Freescale Semiconductor Inc. 26 #include <asm/code-patching.h> 58 qoriq_pm_ops->freeze_time_base(true); in mpc85xx_give_timebase() 61 * e5500/e6500 have a workaround for erratum A-006958 in place in mpc85xx_give_timebase() 62 * that will reread the timebase until TBL is non-zero. in mpc85xx_give_timebase() 66 * TBL is non-zero, we ensure that TB does not change. We don't in mpc85xx_give_timebase() 91 qoriq_pm_ops->freeze_time_base(false); in mpc85xx_give_timebase() 122 qoriq_pm_ops->irq_mask(cpu); in smp_85xx_cpu_offline_self() 131 cur_cpu_spec->cpu_down_flush(); in smp_85xx_cpu_offline_self() [all …]
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/openbmc/linux/Documentation/hwmon/ |
H A D | lm93.rst | 10 Addresses scanned: I2C 0x2c-0x2e 18 Addresses scanned: I2C 0x2c-0x2e 24 - Mark M. Hoffman <mhoffman@lightlink.com> 25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com> 26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org> 27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de> 30 ----------------- 33 Set to non-zero to force some initializations (default is 0). 38 Configures in7 and in8 limit type, where 0 means absolute and non-zero 54 -------------------- [all …]
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/openbmc/u-boot/arch/arm/mach-rmobile/ |
H A D | lowlevel_init_gen3.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 14 #include <asm-offsets.h> 24 * For single-entry systems the lowlevel init is very simple. 49 * Slave should wait for master clearing spin table. 51 * value of spin table and jumping to wrong place.
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/openbmc/linux/arch/powerpc/boot/dts/ |
H A D | iss4xx-mpic.dts | 15 /dts-v1/; 20 #address-cells = <2>; 21 #size-cells = <1>; 22 model = "ibm,iss-4xx"; 23 compatible = "ibm,iss-4xx"; 24 dcr-parent = <&{/cpus/cpu@0}>; 31 #address-cells = <1>; 32 #size-cells = <0>; 38 clock-frequency = <100000000>; // 100Mhz :-) 39 timebase-frequency = <100000000>; [all …]
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