Home
last modified time | relevance | path

Searched +full:spin +full:- +full:table (Results 1 – 25 of 49) sorted by relevance

12

/openbmc/u-boot/doc/
H A DREADME.mpc85xx-spin-table1 Spin table in cache
3 As specified by ePAPR v1.1, the spin table needs to be in cached memory. After
4 DDR is initialized and U-Boot relocates itself into DDR, the spin table is
6 __secondary_start_page. For other cores to use the spin table, the booting
15 core 0 puts the physical address of the spin table (which is in release.S and
21 the new space. The new TLB covers the physical address of the spin table page,
22 with WIMGE =0b00100. Now secondary cores can keep polling the spin table
23 without stress DDR bus because both the code and the spin table is in cache.
H A DREADME.arm641 U-Boot for arm64
5 The initial arm64 U-Boot port was developed before hardware was available,
7 These days U-Boot runs on a variety of 64-bit capable ARM hardware, from
13 1. U-Boot can run at any exception level it is entered in, it is
14 recommened to enter it in EL3 if U-Boot takes some responsibilities of a
16 or SMP bringup). U-Boot can be entered in EL2 when its main purpose is
20 2. U-Boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
21 use rela relocation format, a tool(tools/relocate-rela) by Scott Wood
22 is used to encode the initial addend of rela to u-boot.bin. After running,
23 the U-Boot will be relocated to destination again.
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dbcm2837.dtsi9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 compatible = "brcm,bcm2836-l1-intc";
14 interrupt-controller;
15 #interrupt-cells = <1>;
16 interrupt-parent = <&local_intc>;
21 compatible = "arm,armv7-timer";
22 interrupt-parent = <&local_intc>;
27 always-on;
31 #address-cells = <1>;
32 #size-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/
H A DKconfig8 The default exception vector table is only used for the crash
15 bool "Enable multiple CPUs to enter into U-Boot"
21 CPUECTLR_EL1.SMPEN bit before U-Boot.
36 bool "Support spin-table enable method"
39 Say Y here to support "spin-table" enable method for booting Linux.
42 - Specify enable-method = "spin-table" in each CPU node in the
44 - Bring secondary CPUs into U-Boot proper in a board specific
46 secondary CPUs will spin in unprotected memory area because the
47 master CPU protects the relocated spin code.
49 U-Boot automatically does:
[all …]
H A Dspin_table.c1 // SPDX-License-Identifier: GPL-2.0+
17 unsigned long rsv_size = &spin_table_reserve_end - in spin_table_update_dt()
22 return -ENODEV; in spin_table_update_dt()
33 * spin-table. Otherwise, just return successfully to not in spin_table_update_dt()
36 prop = fdt_getprop(fdt, offset, "enable-method", NULL); in spin_table_update_dt()
37 if (!prop || strcmp(prop, "spin-table")) in spin_table_update_dt()
48 ret = fdt_setprop_u64(fdt, offset, "cpu-release-addr", in spin_table_update_dt()
51 return -ENOSPC; in spin_table_update_dt()
56 return -ENOSPC; in spin_table_update_dt()
58 printf(" Reserved memory region for spin-table: addr=%lx size=%lx\n", in spin_table_update_dt()
H A Dcpu-dt.c1 // SPDX-License-Identifier: GPL-2.0+
18 * the SMP boot method between PSCI and spin-table. in psci_update_dt()
27 __secure_end - __secure_start); in psci_update_dt()
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
7 #include <asm-offsets.h>
22 #include <asm/boot0-linux-kernel-header.h>
25 * Various SoCs need something special and SoC-specific up front in
45 .quad _end - _start
49 .quad __bss_start - _start
53 .quad __bss_end - _start
63 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
67 adr x0, _start /* x0 <- Runtime value of _start */
68 ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2008-2012 Freescale Semiconductor, Inc.
7 #include <asm-offsets.h>
101 /* Enable/invalidate the I-Cache */
119 /* Enable/invalidate the D-Cache */
137 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
139 /* get our PIR to figure out our table entry */
148 * 0-17 Reserved (logic 0s)
149 * 18-19 CHIP_ID, 2'b00 - SoC 1
150 * all others - reserved
[all …]
H A Dfdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
49 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); in ft_fixup_cpu()
50 while (off != -FDT_ERR_NOTFOUND) { in ft_fixup_cpu()
68 enable_method = "fsl,brr-holdoff"; in ft_fixup_cpu()
71 enable_method = "fsl,eebpcr-holdoff"; in ft_fixup_cpu()
74 /* Cores out of reset and in a spin-loop */ in ft_fixup_cpu()
75 enable_method = "spin-table"; in ft_fixup_cpu()
77 fdt_setprop(blob, off, "cpu-release-addr", in ft_fixup_cpu()
81 fdt_setprop_string(blob, off, "enable-method", in ft_fixup_cpu()
[all …]
H A Dmp.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
27 * Determine if U-Boot should keep secondary cores in reset, or let them out
48 out_be32(&pic->pir, 1 << nr); in cpu_reset()
50 (void)in_be32(&pic->pir); in cpu_reset()
51 out_be32(&pic->pir, 0x0); in cpu_reset()
58 u32 *table, id = get_my_id(); in cpu_status() local
64 table = (u32 *)&__spin_table; in cpu_status()
65 printf("table base @ 0x%p\n", table); in cpu_status()
69 table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; in cpu_status()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dmp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014-2015, Freescale Semiconductor
10 * Each spin table element is defined as
18 * the actual spin table is an array of these structures
/openbmc/u-boot/arch/arm/mach-rmobile/
H A Dlowlevel_init_gen3.S1 /* SPDX-License-Identifier: GPL-2.0+ */
14 #include <asm-offsets.h>
24 * For single-entry systems the lowlevel init is very simple.
49 * Slave should wait for master clearing spin table.
51 * value of spin table and jumping to wrong place.
/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/css/
H A Ddefault.css4 body { padding-top: 50px; }
7 img.logo { height: 30px; vertical-align: bottom; }
10 .toaster-navbar-brand { float: left; margin: 7px 25px 0 0; }
11 .toaster-navbar-brand a.brand { color: #777; height: 50px; padding: 15px 5px 15px 15px; font-size: …
12 .toaster-navbar-brand > a { text-decoration: none; }
13 .toaster-navbar-brand > a.brand:hover { color: #5e5e5e; }
16 .glyphicon-info-sign { color: #777; font-size: 16px; }
17 .glyphicon-info-sign:hover { color: #999; cursor: pointer; }
19 /* Override the negative right margin for the navbar-right class */
20 #new-project-button { margin-right: 0; }
[all …]
H A Dfont-awesome.min.css4 * -------------------------------------------------------
6 * can be found at: http://fortawesome.github.com/Font-Awesome/
9 * -------------------------------------------------------
10 * - The Font Awesome font is licensed under the SIL Open Font License - http://scripts.sil.org/OFL
11 * - Font Awesome CSS, LESS, and SASS files are licensed under the MIT License -
12 * http://opensource.org/licenses/mit-license.html
13 …* - The Font Awesome pictograms are licensed under the CC BY 3.0 License - http://creativecommons…
14 * - Attribution is no longer required in Font Awesome 3.0, but much appreciated:
15 * "Font Awesome by Dave Gandy - http://fortawesome.github.com/Font-Awesome"
18 * -------------------------------------------------------
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014-2015 Freescale Semiconductor
12 #include <asm/arch-fsl-layerscape/soc.h>
17 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
19 #include <asm/u-boot.h>
88 /* Set Wuo bit for RN-I 20 */
95 * Set forced-order mode in RNI-6, RNI-20
97 * LS2080A family does not support setting forced-order mode,
115 /* Add fully-coherent masters to DVM domain */
121 /* Set all RN-I ports to QoS of 15 */
[all …]
H A Dmp.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
12 #include <asm/arch-fsl-layerscape/soc.h>
28 u64 *table = get_spin_tbl_addr(); in update_os_arch_secondary_cores() local
33 table[i * WORDS_PER_SPIN_TABLE_ENTRY + in update_os_arch_secondary_cores()
36 table[i * WORDS_PER_SPIN_TABLE_ENTRY + in update_os_arch_secondary_cores()
53 gur_out32(&gur->scratchrw[6], mpidr); in wake_secondary_core_n()
55 rst->brrl |= 1 << ((cluster * cluster_cores) + core); in wake_secondary_core_n()
62 while (gur_in32(&gur->scratchrw[6]) != 0) in wake_secondary_core_n()
79 u64 *table = get_spin_tbl_addr(); in fsl_layerscape_wake_seconday_cores() local
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A DKconfig33 default "fsl,ls1021a-pcie" if ARCH_LS1021A
51 in spin table to properly handle all cores.
/openbmc/u-boot/include/configs/
H A Dthunderx_88xx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
22 /* SMP Spin Table Definitions */
52 #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
57 /* C80000 - 0x40 */
H A Ds32v234evb.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2015-2016 Freescale Semiconductor, Inc.
11 #include <asm/arch/imx-regs.h>
45 /* SMP Spin Table Definitions */
107 "fdt_file=s32v234-evb.dtb\0" \
116 "update_sd_firmware_filename=u-boot.imx\0" \
168 /* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */
177 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/openbmc/qemu/hw/i386/
H A Dpc_sysfw_ovmf.c4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2011-2012 Intel Corporation
27 #include "qemu/error-report.h"
32 #define OVMF_TABLE_FOOTER_GUID "96b582de-1fb2-45f7-baea-a366c55a082d"
58 * if this is OVMF there will be a table footer in pc_system_parse_ovmf_flash()
60 * (= 32 bytes after the table + 16 bytes the GUID itself). in pc_system_parse_ovmf_flash()
65 ptr = flash_ptr + flash_size - (bytes_after_table_footer + sizeof(guid)); in pc_system_parse_ovmf_flash()
70 /* if found, just before is two byte table length */ in pc_system_parse_ovmf_flash()
71 ptr -= sizeof(uint16_t); in pc_system_parse_ovmf_flash()
72 tot_len = le16_to_cpu(*(uint16_t *)ptr) - sizeof(guid) - sizeof(uint16_t); in pc_system_parse_ovmf_flash()
[all …]
/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/templates/
H A Dcommand_line_builds.html6 {% block title %} Import Builds from eventlogs - Toaster {% endblock %}
10 <div class="container-fluid">
13 <div class="fa-spin">
18 <div class="col-md-12">
19 <div class="page-header">
21 <div class="col-md-6">
25 <div class="col-md-6">
26 … <button id="import_all" type="button" class="btn btn-primary navbar-btn navbar-right">
27 … <span class="glyphicon glyphicon-upload" style="vertical-align: top;"></span> Import All
34 <div class="row-fluid" id="empty-state-{{table_name}}">
[all …]
/openbmc/qemu/include/hw/xen/interface/
H A Dgrant_table.h1 /* SPDX-License-Identifier: MIT */
6 * page-ownership transfers.
23 * Each domain has its own grant table. This is a data structure that
26 * table are identified by grant references. A grant reference is an
27 * integer, which indexes into the grant table. It acts as a
31 * This capability-based system allows shared-memory communications
40 * GRANT TABLE REPRESENTATION
43 /* Some rough guidelines on accessing and updating grant-table entries
44 * in a concurrency-safe manner. For more information, Linux contains a
46 …* http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drivers/xen/grant-table.c;…
[all …]
/openbmc/qemu/hw/arm/
H A Draspi.c12 * See the COPYING file in the top-level directory.
24 #include "qemu/error-report.h"
30 #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common")
49 * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/
125 { 0xe3530000 }, /* cmp r3, #0 ;spin while zero */ in write_smpboot()
141 info->smp_loader_start, smpboot, fixupcontext); in write_smpboot()
148 * The mechanism for doing the spin-table is also entirely different. in write_smpboot64()
149 * We must have four 64-bit fields at absolute addresses in write_smpboot64()
159 { 0xd503205f }, /* spin: wfe */ in write_smpboot64()
161 { 0xb4ffffc4 }, /* cbz x4, spin */ in write_smpboot64()
[all …]
/openbmc/u-boot/drivers/ram/rockchip/
H A Ddmc-rk3368.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/memory/rk3368-dmc.h>
10 #include <dt-structs.h>
123 ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
125 ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
133 (((n - 5) & 0x7) << 3)
141 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
143 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
149 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
151 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
[all …]
/openbmc/u-boot/drivers/ata/
H A Ddwc_ahsata.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
99 return (i < timeout_msec) ? 0 : -1; in waiting_for_cmd_completed()
104 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in ahci_setup_oobr()
106 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr); in ahci_setup_oobr()
107 writel(0x02060b14, &host_mmio->oobr); in ahci_setup_oobr()
117 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in ahci_host_init()
120 cap_save = readl(&host_mmio->cap); in ahci_host_init()
124 tmp = readl(&host_mmio->ghc); in ahci_host_init()
126 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc); in ahci_host_init()
[all …]

12