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/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm6375-mdss.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
7 title: Qualcomm SM6375 Display MDSS
13 SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
20 const: qcom,sm6375-mdss
48 const: qcom,sm6375-dpu
55 - const: qcom,sm6375-dsi-ctrl
62 const: qcom,sm6375-dsi-phy-7nm
69 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
70 #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
75 compatible = "qcom,sm6375-mdss";
[all …]
H A Dqcom,sc7180-dpu.yaml20 - qcom,sm6375-dpu
68 - qcom,sm6375-dpu
H A Ddsi-phy-7nm.yaml21 - qcom,sm6375-dsi-phy-7nm
H A Ddsi-controller-main.yaml32 - qcom,sm6375-dsi-ctrl
378 - qcom,sm6375-dsi-ctrl
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm6375-dispcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm6375-dispcc.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SM6375
14 domains on SM6375.
16 See also:: include/dt-bindings/clock/qcom,dispcc-sm6375.h
23 const: qcom,sm6375-dispcc
40 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
44 compatible = "qcom,sm6375-dispcc";
H A Dqcom,sm6375-gcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM6375
14 domains on SM6375
16 See also:: include/dt-bindings/clock/qcom,sm6375-gcc.h
23 const: qcom,sm6375-gcc
41 compatible = "qcom,sm6375-gcc";
H A Dqcom,sm6375-gpucc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller on SM6375
16 See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h
21 - qcom,sm6375-gpucc
53 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
62 compatible = "qcom,sm6375-gpucc";
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm6375-tlmm.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6375-tlmm.yaml#
7 title: Qualcomm Technologies, Inc. SM6375 TLMM block
13 Top Level Mode Multiplexer pin controller in Qualcomm SM6375 SoC.
20 const: qcom,sm6375-tlmm
45 - $ref: "#/$defs/qcom-sm6375-tlmm-state"
48 $ref: "#/$defs/qcom-sm6375-tlmm-state"
52 qcom-sm6375-tlmm-state:
120 compatible = "qcom,sm6375-tlmm";
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm6375.dtsi7 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
8 #include <dt-bindings/clock/qcom,sm6375-gpucc.h>
307 compatible = "qcom,scm-sm6375", "qcom,scm";
645 compatible = "qcom,sm6375-rpm-proc", "qcom,rpm-proc";
656 compatible = "qcom,rpm-sm6375";
660 compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc";
667 compatible = "qcom,sm6375-rpmpd";
812 compatible = "qcom,sm6375-ipcc", "qcom,ipcc";
827 compatible = "qcom,sm6375-tlmm";
922 compatible = "qcom,sm6375-gcc";
[all …]
H A Dsm6375-sony-xperia-murray-pdx225.dts12 #include "sm6375.dtsi"
22 compatible = "sony,pdx225", "qcom,sm6375";
181 firmware-name = "qcom/sm6375/Sony/murray/adsp.mbn";
186 firmware-name = "qcom/sm6375/Sony/murray/cdsp.mbn";
/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Dqcom,scm.yaml58 - qcom,scm-sm6375
118 - qcom,scm-sm6375
137 - qcom,scm-sm6375
/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml32 - qcom,sm6375-smmu-v2
53 - qcom,sm6375-smmu-500
75 - qcom,sm6375-smmu-500
315 - qcom,sm6375-smmu-v2
472 - qcom,sm6375-smmu-500
485 const: qcom,sm6375-smmu-500
/openbmc/linux/drivers/clk/qcom/
H A Dgpucc-sm6375.c14 #include <dt-bindings/clock/qcom,sm6375-gpucc.h>
431 { .compatible = "qcom,sm6375-gpucc" },
467 .name = "gpucc-sm6375",
473 MODULE_DESCRIPTION("QTI GPUCC SM6375 Driver");
H A DMakefile108 obj-$(CONFIG_SM_DISPCC_6375) += dispcc-sm6375.o
115 obj-$(CONFIG_SM_GCC_6375) += gcc-sm6375.o
125 obj-$(CONFIG_SM_GPUCC_6375) += gpucc-sm6375.o
H A Ddispcc-sm6375.c12 #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
571 { .compatible = "qcom,sm6375-dispcc" },
592 .name = "disp_cc-sm6375",
609 MODULE_DESCRIPTION("QTI DISPCC SM6375 Driver");
H A DKconfig809 tristate "SM6375 Display Clock Controller"
814 SM6375 devices.
865 tristate "SM6375 Global Clock Controller"
869 Support for the global clock controller on SM6375 devices.
945 tristate "SM6375 Graphics Clock Controller"
949 Support for the graphics clock controller on SM6375 devices.
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dqcom,sdm845-refgen-regulator.yaml34 - qcom,sm6375-refgen-regulator
/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,osm-l3.yaml33 - qcom,sm6375-cpucp-l3
/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dqcom,imem.yaml31 - qcom,sm6375-imem
/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-qcom-hw.yaml39 - qcom,sm6375-cpufreq-epss
134 - qcom,sm6375-cpufreq-epss
/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dqcom-ipcc.yaml32 - qcom,sm6375-ipcc
/openbmc/linux/drivers/pinctrl/qcom/
H A DKconfig.msm314 tristate "Qualcomm Technologies Inc SM6375 pin controller driver"
319 Technologies Inc SM6375 platform.
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dqcom,gpi.yaml31 - qcom,sm6375-gpi-dma
/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Dqcom,qfprom.yaml41 - qcom,sm6375-qfprom
/openbmc/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-qcom.c259 { .compatible = "qcom,sm6375-mdss" },
564 { .compatible = "qcom,sm6375-smmu-v2", .data = &qcom_smmu_v2_data },
565 { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },

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