| /openbmc/linux/Documentation/devicetree/bindings/display/msm/ |
| H A D | qcom,sm6125-mdss.yaml | 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml#
7 title: Qualcomm SM6125 Display MDSS
13 SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
20 const: qcom,sm6125-mdss
48 const: qcom,sm6125-dpu
55 - const: qcom,sm6125-dsi-ctrl
62 const: qcom,sm6125-dsi-phy-14nm
68 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
69 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
75 compatible = "qcom,sm6125-mdss";
[all …]
|
| H A D | qcom,sc7180-dpu.yaml | 18 - qcom,sm6125-dpu
69 - qcom,sm6125-dpu
|
| H A D | dsi-phy-14nm.yaml | 22 - qcom,sm6125-dsi-phy-14nm
|
| H A D | dsi-controller-main.yaml | 30 - qcom,sm6125-dsi-ctrl
309 - qcom,sm6125-dsi-ctrl
|
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | qcom,gcc-sm6125.yaml | 4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM6125
14 domains on SM6125.
16 See also:: include/dt-bindings/clock/qcom,gcc-sm6125.h
20 const: qcom,gcc-sm6125
46 compatible = "qcom,gcc-sm6125";
|
| H A D | qcom,dispcc-sm6125.yaml | 4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
7 title: Qualcomm Display Clock Controller on SM6125
14 on SM6125.
16 See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
21 - qcom,sm6125-dispcc
77 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
80 compatible = "qcom,sm6125-dispcc";
|
| H A D | qcom,sm6125-gpucc.yaml | 4 $id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller on SM6125
16 See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h
21 - qcom,sm6125-gpucc
48 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
56 compatible = "qcom,sm6125-gpucc";
|
| H A D | qcom,rpmcc.yaml | 47 - qcom,rpmcc-sm6125
124 - qcom,rpmcc-sm6125
|
| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | qcom,sm6125-tlmm.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-tlmm.yaml#
6 title: Qualcomm Technologies, Inc. SM6125 TLMM block
12 Top Level Mode Multiplexer pin controller in Qualcomm SM6125 SoC.
19 const: qcom,sm6125-tlmm
51 - $ref: "#/$defs/qcom-sm6125-tlmm-state"
54 $ref: "#/$defs/qcom-sm6125-tlmm-state"
58 qcom-sm6125-tlmm-state:
112 compatible = "qcom,sm6125-tlmm";
|
| /openbmc/linux/arch/arm64/boot/dts/qcom/ |
| H A D | sm6125.dtsi | 6 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
163 compatible = "qcom,scm-sm6125", "qcom,scm";
185 compatible = "qcom,sm6125-rpm-proc", "qcom,rpm-proc";
195 compatible = "qcom,rpm-sm6125";
199 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
204 compatible = "qcom,sm6125-rpmpd";
386 compatible = "qcom,sm6125-tlmm";
664 compatible = "qcom,gcc-sm6125";
692 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
719 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
[all …]
|
| H A D | sm6125-xiaomi-laurel-sprout.dts | 12 #include "sm6125.dtsi"
17 compatible = "xiaomi,laurel-sprout", "qcom,sm6125";
21 qcom,msm-id = <394 0>; /* sm6125 v1 */
|
| H A D | sm6125-sony-xperia-seine-pdx201.dts | 8 #include "sm6125.dtsi"
16 qcom,msm-id = <394 0x10000>; /* sm6125 v1 */
20 compatible = "sony,pdx201", "qcom,sm6125";
|
| /openbmc/linux/drivers/clk/qcom/ |
| H A D | gpucc-sm6125.c | 13 #include <dt-bindings/clock/qcom,sm6125-gpucc.h>
389 { .compatible = "qcom,sm6125-gpucc" },
418 .name = "gpucc-sm6125",
424 MODULE_DESCRIPTION("QTI GPUCC SM6125 Driver");
|
| H A D | Makefile | 106 obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
113 obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
123 obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o
|
| H A D | Kconfig | 779 tristate "SM6125 Display Clock Controller"
784 SM6125 devices.
848 tristate "SM6125 Global Clock Controller"
851 Support for the global clock controller on SM6125 devices.
935 tristate "SM6125 Graphics Clock Controller"
939 Support for the graphics clock controller on SM6125 devices.
|
| H A D | dispcc-sm6125.c | 11 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
670 { .compatible = "qcom,sm6125-dispcc" },
691 .name = "disp_cc-sm6125",
708 MODULE_DESCRIPTION("QTI DISPCC SM6125 Driver");
|
| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | qcom,sc8280xp-qmp-ufs-phy.yaml | 26 - qcom,sm6125-qmp-ufs-phy
105 - qcom,sm6125-qmp-ufs-phy
|
| /openbmc/linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | qcom,apcs-kpss-global.yaml | 52 - qcom,sm6125-apcs-hmss-global
147 - qcom,sm6125-apcs-hmss-global
|
| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | qcom,dwc3.yaml | 39 - qcom,sm6125-dwc3
311 - qcom,sm6125-dwc3
367 - qcom,sm6125-dwc3
|
| /openbmc/linux/drivers/pinctrl/qcom/ |
| H A D | Kconfig.msm | 298 tristate "Qualcomm Technologies Inc SM6125 pin controller driver"
303 Technologies Inc SM6125 platform.
|
| H A D | Makefile | 48 obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o
|
| /openbmc/linux/Documentation/devicetree/bindings/iommu/ |
| H A D | arm,smmu.yaml | 51 - qcom,sm6125-smmu-500
88 - qcom,sm6125-smmu-500
436 - qcom,sm6125-smmu-500
|
| /openbmc/linux/Documentation/devicetree/bindings/dma/ |
| H A D | qcom,gpi.yaml | 39 - qcom,sm6125-gpi-dma
|
| /openbmc/linux/Documentation/devicetree/bindings/soc/qcom/ |
| H A D | qcom,smd-rpm.yaml | 56 - qcom,rpm-sm6125
|
| /openbmc/linux/Documentation/devicetree/bindings/firmware/ |
| H A D | qcom,scm.yaml | 56 - qcom,scm-sm6125
|