1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (UFS, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,msm8996-qmp-ufs-phy
20      - qcom,msm8998-qmp-ufs-phy
21      - qcom,sa8775p-qmp-ufs-phy
22      - qcom,sc8180x-qmp-ufs-phy
23      - qcom,sc8280xp-qmp-ufs-phy
24      - qcom,sdm845-qmp-ufs-phy
25      - qcom,sm6115-qmp-ufs-phy
26      - qcom,sm6125-qmp-ufs-phy
27      - qcom,sm6350-qmp-ufs-phy
28      - qcom,sm7150-qmp-ufs-phy
29      - qcom,sm8150-qmp-ufs-phy
30      - qcom,sm8250-qmp-ufs-phy
31      - qcom,sm8350-qmp-ufs-phy
32      - qcom,sm8450-qmp-ufs-phy
33      - qcom,sm8550-qmp-ufs-phy
34
35  reg:
36    maxItems: 1
37
38  clocks:
39    minItems: 1
40    maxItems: 3
41
42  clock-names:
43    minItems: 1
44    items:
45      - const: ref
46      - const: ref_aux
47      - const: qref
48
49  power-domains:
50    maxItems: 1
51
52  resets:
53    maxItems: 1
54
55  reset-names:
56    items:
57      - const: ufsphy
58
59  vdda-phy-supply: true
60
61  vdda-pll-supply: true
62
63  "#clock-cells":
64    const: 1
65
66  "#phy-cells":
67    const: 0
68
69required:
70  - compatible
71  - reg
72  - clocks
73  - clock-names
74  - resets
75  - reset-names
76  - vdda-phy-supply
77  - vdda-pll-supply
78  - "#phy-cells"
79
80allOf:
81  - if:
82      properties:
83        compatible:
84          contains:
85            enum:
86              - qcom,sa8775p-qmp-ufs-phy
87              - qcom,sm8450-qmp-ufs-phy
88    then:
89      properties:
90        clocks:
91          minItems: 3
92        clock-names:
93          minItems: 3
94
95  - if:
96      properties:
97        compatible:
98          contains:
99            enum:
100              - qcom,msm8998-qmp-ufs-phy
101              - qcom,sc8180x-qmp-ufs-phy
102              - qcom,sc8280xp-qmp-ufs-phy
103              - qcom,sdm845-qmp-ufs-phy
104              - qcom,sm6115-qmp-ufs-phy
105              - qcom,sm6125-qmp-ufs-phy
106              - qcom,sm6350-qmp-ufs-phy
107              - qcom,sm7150-qmp-ufs-phy
108              - qcom,sm8150-qmp-ufs-phy
109              - qcom,sm8250-qmp-ufs-phy
110              - qcom,sm8350-qmp-ufs-phy
111              - qcom,sm8550-qmp-ufs-phy
112    then:
113      properties:
114        clocks:
115          maxItems: 2
116        clock-names:
117          maxItems: 2
118
119  - if:
120      properties:
121        compatible:
122          contains:
123            enum:
124              - qcom,msm8996-qmp-ufs-phy
125    then:
126      properties:
127        clocks:
128          maxItems: 1
129        clock-names:
130          maxItems: 1
131
132  - if:
133      properties:
134        compatible:
135          contains:
136            enum:
137              - qcom,msm8996-qmp-ufs-phy
138              - qcom,msm8998-qmp-ufs-phy
139    then:
140      properties:
141        power-domains:
142          false
143    else:
144      required:
145        - power-domains
146
147additionalProperties: false
148
149examples:
150  - |
151    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
152
153    ufs_mem_phy: phy@1d87000 {
154        compatible = "qcom,sc8280xp-qmp-ufs-phy";
155        reg = <0x01d87000 0x1000>;
156
157        clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
158        clock-names = "ref", "ref_aux";
159
160        power-domains = <&gcc UFS_PHY_GDSC>;
161
162        resets = <&ufs_mem_hc 0>;
163        reset-names = "ufsphy";
164
165        vdda-phy-supply = <&vreg_l6b>;
166        vdda-pll-supply = <&vreg_l3b>;
167
168        #phy-cells = <0>;
169    };
170