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/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
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H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
26 compatible = "sifive,bullet0", "riscv";
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/openbmc/linux/Documentation/devicetree/bindings/clock/sifive/
H A Dfu540-prci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 SiFive, Inc.
4 ---
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 On the FU540 family of SoCs, most system-wide clock and reset integration
15 is via the PRCI IP block.
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
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/openbmc/linux/drivers/clk/sifive/
H A Dfu540-prci.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018-2021 SiFive, Inc.
4 * Copyright (C) 2018-2019 Wesley Terpstra
5 * Copyright (C) 2018-2019 Paul Walmsley
6 * Copyright (C) 2020-2021 Zong Li
8 * The FU540 PRCI implements clock and reset control for the SiFive
9 * FU540-C000 chip. This driver assumes that it has sole control
10 * over all PRCI resources.
12 * This driver is based on the PRCI driver written by Wesley Terpstra:
13 * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 bool "SiFive SoC driver support"
8 SoC drivers for SiFive Linux-capable SoCs.
13 bool "PRCI driver for SiFive SoCs"
19 Supports the Power Reset Clock interface (PRCI) IP block found in
20 FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
H A Dsifive-prci.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 SiFive, Inc.
10 #include "sifive-prci.h"
11 #include "fu540-prci.h"
12 #include "fu740-prci.h"
19 * __prci_readl() - read from a PRCI register
20 * @pd: PRCI context
21 * @offs: register offset to read from (in bytes, from PRCI base address)
24 * address of the PRCI register target described by @pd, and return
33 return readl_relaxed(pd->va + offs); in __prci_readl()
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/openbmc/u-boot/drivers/clk/sifive/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 bool "SiFive SoC driver support"
10 SoC drivers for SiFive Linux-capable SoCs.
13 bool "PRCI driver for SiFive FU540 SoCs"
17 Supports the Power Reset Clock interface (PRCI) IP block found in
18 FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
H A Dfu540-prci.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018 SiFive, Inc.
18 * The FU540 PRCI implements clock and reset control for the SiFive
19 * FU540-C000 chip. This driver assumes that it has sole control
20 * over all PRCI resources.
22 * This driver is based on the PRCI driver written by Wesley Terpstra.
25 * https://github.com/riscv/riscv-linux
28 * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
32 #include <clk-uclass.h>
40 #include <dt-bindings/clk/sifive-fu540-prci.h>
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/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dsifive-serial.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: serial.yaml#
20 - enum:
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/openbmc/qemu/include/hw/misc/
H A Dsifive_u_prci.h2 * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface
35 * Current FU540-C000 manual says ready bit is at bit 29, but
36 * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31.
39 * see https://github.com/sifive/freedom-u540-c000-bootloader
61 #define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci"
85 * Clock indexes for use by Device Tree data and the PRCI driver.
87 * These values are from sifive-fu540-prci.h in the Linux kernel.
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dsifive,gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive GPIO controller
10 - Paul Walmsley <paul.walmsley@sifive.com>
15 - enum:
16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
18 - canaan,k210-gpiohs
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/openbmc/qemu/hw/riscv/
H A Dsifive_u.c2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
8 * Provides a board compatible with the SiFive Freedom U SDK:
13 * 3) PRCI (Power, Reset, Clock, Interrupt)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
39 #include "qemu/error-report.h"
99 uint64_t mem_size = ms->ram_size; in create_fdt()
108 "sifive,clint0", "riscv,clint0" in create_fdt()
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
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/openbmc/u-boot/doc/
H A DREADME.sifive-fu5401 FU540-C000 RISC-V SoC
3 The FU540-C000 is the world’s first 4+1 64-bit RISC‑V SoC from SiFive.
5 The HiFive Unleashed development platform is based on FU540-C000 and capable
11 1. SiFive UART Driver.
12 2. SiFive PRCI Driver for clock.
16 1. SPI driver is still missing. So MMC card can't be used in U-Boot as of now.
17 2. U-Boot expects the serial console device entry to be present under /chosen
20 stdout-path = "/soc/serial@10010000:115200";
23 Without a serial console U-Boot will panic.
27 1. Add the RISC-V toolchain to your PATH.
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/openbmc/qemu/docs/system/riscv/
H A Dsifive_u.rst1 SiFive HiFive Unleashed (``sifive_u``)
4 SiFive HiFive Unleashed Development Board is the ultimate RISC-V development
5 board featuring the Freedom U540 multi-core RISC-V processor.
8 -----------------
15 * Platform-Level Interrupt Controller (PLIC)
16 * Power, Reset, Clock, Interrupt (PRCI)
17 * L2 Loosely Integrated Memory (L2-LIM)
22 * 1 One-Time Programmable (OTP) memory with stored serial number
30 1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode.
32 is also possible to create a 32-bit variant with the same peripherals except
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/openbmc/
Dopengrok1.0.log1 2025-03-22 03:00:49.337-0500 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-03-22 03:00:49.465-0500 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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Dopengrok2.0.log1 2025-03-21 03:00:54.402-0500 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-03-21 03:00:54.529-0500 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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/openbmc/linux/
H A Dopengrok2.0.log1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)
4 2024-1
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H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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H A Dopengrok0.0.log1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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