1c816e1ddSZong Li // SPDX-License-Identifier: GPL-2.0
2c816e1ddSZong Li /*
3c816e1ddSZong Li * Copyright (C) 2020 SiFive, Inc.
4c816e1ddSZong Li * Copyright (C) 2020 Zong Li
5c816e1ddSZong Li */
6c816e1ddSZong Li
7c816e1ddSZong Li #include <linux/delay.h>
8c816e1ddSZong Li #include <linux/io.h>
9*a96cbb14SRob Herring #include <linux/of.h>
10c816e1ddSZong Li #include "sifive-prci.h"
11c816e1ddSZong Li #include "fu540-prci.h"
12efc91ae4SZong Li #include "fu740-prci.h"
13c816e1ddSZong Li
14c816e1ddSZong Li /*
15c816e1ddSZong Li * Private functions
16c816e1ddSZong Li */
17c816e1ddSZong Li
18c816e1ddSZong Li /**
19c816e1ddSZong Li * __prci_readl() - read from a PRCI register
20c816e1ddSZong Li * @pd: PRCI context
21c816e1ddSZong Li * @offs: register offset to read from (in bytes, from PRCI base address)
22c816e1ddSZong Li *
23c816e1ddSZong Li * Read the register located at offset @offs from the base virtual
24c816e1ddSZong Li * address of the PRCI register target described by @pd, and return
25c816e1ddSZong Li * the value to the caller.
26c816e1ddSZong Li *
27c816e1ddSZong Li * Context: Any context.
28c816e1ddSZong Li *
29c816e1ddSZong Li * Return: the contents of the register described by @pd and @offs.
30c816e1ddSZong Li */
__prci_readl(struct __prci_data * pd,u32 offs)31c816e1ddSZong Li static u32 __prci_readl(struct __prci_data *pd, u32 offs)
32c816e1ddSZong Li {
33c816e1ddSZong Li return readl_relaxed(pd->va + offs);
34c816e1ddSZong Li }
35c816e1ddSZong Li
__prci_writel(u32 v,u32 offs,struct __prci_data * pd)36c816e1ddSZong Li static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
37c816e1ddSZong Li {
38c816e1ddSZong Li writel_relaxed(v, pd->va + offs);
39c816e1ddSZong Li }
40c816e1ddSZong Li
41c816e1ddSZong Li /* WRPLL-related private functions */
42c816e1ddSZong Li
43c816e1ddSZong Li /**
44c816e1ddSZong Li * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
45c816e1ddSZong Li * @c: ptr to a struct wrpll_cfg record to write config into
46c816e1ddSZong Li * @r: value read from the PRCI PLL configuration register
47c816e1ddSZong Li *
48c816e1ddSZong Li * Given a value @r read from an FU740 PRCI PLL configuration register,
49c816e1ddSZong Li * split it into fields and populate it into the WRPLL configuration record
50c816e1ddSZong Li * pointed to by @c.
51c816e1ddSZong Li *
52c816e1ddSZong Li * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
53c816e1ddSZong Li * have the same register layout.
54c816e1ddSZong Li *
55c816e1ddSZong Li * Context: Any context.
56c816e1ddSZong Li */
__prci_wrpll_unpack(struct wrpll_cfg * c,u32 r)57c816e1ddSZong Li static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
58c816e1ddSZong Li {
59c816e1ddSZong Li u32 v;
60c816e1ddSZong Li
61c816e1ddSZong Li v = r & PRCI_COREPLLCFG0_DIVR_MASK;
62c816e1ddSZong Li v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
63c816e1ddSZong Li c->divr = v;
64c816e1ddSZong Li
65c816e1ddSZong Li v = r & PRCI_COREPLLCFG0_DIVF_MASK;
66c816e1ddSZong Li v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
67c816e1ddSZong Li c->divf = v;
68c816e1ddSZong Li
69c816e1ddSZong Li v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
70c816e1ddSZong Li v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
71c816e1ddSZong Li c->divq = v;
72c816e1ddSZong Li
73c816e1ddSZong Li v = r & PRCI_COREPLLCFG0_RANGE_MASK;
74c816e1ddSZong Li v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
75c816e1ddSZong Li c->range = v;
76c816e1ddSZong Li
77c816e1ddSZong Li c->flags &=
78c816e1ddSZong Li (WRPLL_FLAGS_INT_FEEDBACK_MASK | WRPLL_FLAGS_EXT_FEEDBACK_MASK);
79c816e1ddSZong Li
80c816e1ddSZong Li /* external feedback mode not supported */
81c816e1ddSZong Li c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
82c816e1ddSZong Li }
83c816e1ddSZong Li
84c816e1ddSZong Li /**
85c816e1ddSZong Li * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
86c816e1ddSZong Li * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
87c816e1ddSZong Li *
88c816e1ddSZong Li * Using a set of WRPLL configuration values pointed to by @c,
89c816e1ddSZong Li * assemble a PRCI PLL configuration register value, and return it to
90c816e1ddSZong Li * the caller.
91c816e1ddSZong Li *
92c816e1ddSZong Li * Context: Any context. Caller must ensure that the contents of the
93c816e1ddSZong Li * record pointed to by @c do not change during the execution
94c816e1ddSZong Li * of this function.
95c816e1ddSZong Li *
96c816e1ddSZong Li * Returns: a value suitable for writing into a PRCI PLL configuration
97c816e1ddSZong Li * register
98c816e1ddSZong Li */
__prci_wrpll_pack(const struct wrpll_cfg * c)99c816e1ddSZong Li static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
100c816e1ddSZong Li {
101c816e1ddSZong Li u32 r = 0;
102c816e1ddSZong Li
103c816e1ddSZong Li r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
104c816e1ddSZong Li r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
105c816e1ddSZong Li r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
106c816e1ddSZong Li r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
107c816e1ddSZong Li
108c816e1ddSZong Li /* external feedback mode not supported */
109c816e1ddSZong Li r |= PRCI_COREPLLCFG0_FSE_MASK;
110c816e1ddSZong Li
111c816e1ddSZong Li return r;
112c816e1ddSZong Li }
113c816e1ddSZong Li
114c816e1ddSZong Li /**
115732374a0SPragnesh Patel * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
116c816e1ddSZong Li * @pd: PRCI context
117c816e1ddSZong Li * @pwd: PRCI WRPLL metadata
118c816e1ddSZong Li *
119c816e1ddSZong Li * Read the current configuration of the PLL identified by @pwd from
120c816e1ddSZong Li * the PRCI identified by @pd, and store it into the local configuration
121c816e1ddSZong Li * cache in @pwd.
122c816e1ddSZong Li *
123c816e1ddSZong Li * Context: Any context. Caller must prevent the records pointed to by
124c816e1ddSZong Li * @pd and @pwd from changing during execution.
125c816e1ddSZong Li */
__prci_wrpll_read_cfg0(struct __prci_data * pd,struct __prci_wrpll_data * pwd)126732374a0SPragnesh Patel static void __prci_wrpll_read_cfg0(struct __prci_data *pd,
127c816e1ddSZong Li struct __prci_wrpll_data *pwd)
128c816e1ddSZong Li {
129c816e1ddSZong Li __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
130c816e1ddSZong Li }
131c816e1ddSZong Li
132c816e1ddSZong Li /**
133732374a0SPragnesh Patel * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
134c816e1ddSZong Li * @pd: PRCI context
135c816e1ddSZong Li * @pwd: PRCI WRPLL metadata
136c816e1ddSZong Li * @c: WRPLL configuration record to write
137c816e1ddSZong Li *
138c816e1ddSZong Li * Write the WRPLL configuration described by @c into the WRPLL
139c816e1ddSZong Li * configuration register identified by @pwd in the PRCI instance
140c816e1ddSZong Li * described by @c. Make a cached copy of the WRPLL's current
141c816e1ddSZong Li * configuration so it can be used by other code.
142c816e1ddSZong Li *
143c816e1ddSZong Li * Context: Any context. Caller must prevent the records pointed to by
144c816e1ddSZong Li * @pd and @pwd from changing during execution.
145c816e1ddSZong Li */
__prci_wrpll_write_cfg0(struct __prci_data * pd,struct __prci_wrpll_data * pwd,struct wrpll_cfg * c)146732374a0SPragnesh Patel static void __prci_wrpll_write_cfg0(struct __prci_data *pd,
147c816e1ddSZong Li struct __prci_wrpll_data *pwd,
148c816e1ddSZong Li struct wrpll_cfg *c)
149c816e1ddSZong Li {
150c816e1ddSZong Li __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
151c816e1ddSZong Li
152c816e1ddSZong Li memcpy(&pwd->c, c, sizeof(*c));
153c816e1ddSZong Li }
154c816e1ddSZong Li
155732374a0SPragnesh Patel /**
156732374a0SPragnesh Patel * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
157732374a0SPragnesh Patel * into the PRCI
158732374a0SPragnesh Patel * @pd: PRCI context
159732374a0SPragnesh Patel * @pwd: PRCI WRPLL metadata
160732374a0SPragnesh Patel * @enable: Clock enable or disable value
161732374a0SPragnesh Patel */
__prci_wrpll_write_cfg1(struct __prci_data * pd,struct __prci_wrpll_data * pwd,u32 enable)162732374a0SPragnesh Patel static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
163732374a0SPragnesh Patel struct __prci_wrpll_data *pwd,
164732374a0SPragnesh Patel u32 enable)
165732374a0SPragnesh Patel {
166732374a0SPragnesh Patel __prci_writel(enable, pwd->cfg1_offs, pd);
167732374a0SPragnesh Patel }
168732374a0SPragnesh Patel
169c816e1ddSZong Li /*
170c816e1ddSZong Li * Linux clock framework integration
171c816e1ddSZong Li *
172c816e1ddSZong Li * See the Linux clock framework documentation for more information on
173c816e1ddSZong Li * these functions.
174c816e1ddSZong Li */
175c816e1ddSZong Li
sifive_prci_wrpll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)176c816e1ddSZong Li unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw,
177c816e1ddSZong Li unsigned long parent_rate)
178c816e1ddSZong Li {
179c816e1ddSZong Li struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
180c816e1ddSZong Li struct __prci_wrpll_data *pwd = pc->pwd;
181c816e1ddSZong Li
182c816e1ddSZong Li return wrpll_calc_output_rate(&pwd->c, parent_rate);
183c816e1ddSZong Li }
184c816e1ddSZong Li
sifive_prci_wrpll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)185c816e1ddSZong Li long sifive_prci_wrpll_round_rate(struct clk_hw *hw,
186c816e1ddSZong Li unsigned long rate,
187c816e1ddSZong Li unsigned long *parent_rate)
188c816e1ddSZong Li {
189c816e1ddSZong Li struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
190c816e1ddSZong Li struct __prci_wrpll_data *pwd = pc->pwd;
191c816e1ddSZong Li struct wrpll_cfg c;
192c816e1ddSZong Li
193c816e1ddSZong Li memcpy(&c, &pwd->c, sizeof(c));
194c816e1ddSZong Li
195c816e1ddSZong Li wrpll_configure_for_rate(&c, rate, *parent_rate);
196c816e1ddSZong Li
197c816e1ddSZong Li return wrpll_calc_output_rate(&c, *parent_rate);
198c816e1ddSZong Li }
199c816e1ddSZong Li
sifive_prci_wrpll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)200c816e1ddSZong Li int sifive_prci_wrpll_set_rate(struct clk_hw *hw,
201c816e1ddSZong Li unsigned long rate, unsigned long parent_rate)
202c816e1ddSZong Li {
203c816e1ddSZong Li struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
204c816e1ddSZong Li struct __prci_wrpll_data *pwd = pc->pwd;
205c816e1ddSZong Li struct __prci_data *pd = pc->pd;
206c816e1ddSZong Li int r;
207c816e1ddSZong Li
208c816e1ddSZong Li r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
209c816e1ddSZong Li if (r)
210c816e1ddSZong Li return r;
211c816e1ddSZong Li
212c816e1ddSZong Li if (pwd->enable_bypass)
213c816e1ddSZong Li pwd->enable_bypass(pd);
214c816e1ddSZong Li
215732374a0SPragnesh Patel __prci_wrpll_write_cfg0(pd, pwd, &pwd->c);
216c816e1ddSZong Li
217c816e1ddSZong Li udelay(wrpll_calc_max_lock_us(&pwd->c));
218c816e1ddSZong Li
219732374a0SPragnesh Patel return 0;
220732374a0SPragnesh Patel }
221732374a0SPragnesh Patel
sifive_clk_is_enabled(struct clk_hw * hw)222732374a0SPragnesh Patel int sifive_clk_is_enabled(struct clk_hw *hw)
223732374a0SPragnesh Patel {
224732374a0SPragnesh Patel struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
225732374a0SPragnesh Patel struct __prci_wrpll_data *pwd = pc->pwd;
226732374a0SPragnesh Patel struct __prci_data *pd = pc->pd;
227732374a0SPragnesh Patel u32 r;
228732374a0SPragnesh Patel
229732374a0SPragnesh Patel r = __prci_readl(pd, pwd->cfg1_offs);
230732374a0SPragnesh Patel
231732374a0SPragnesh Patel if (r & PRCI_COREPLLCFG1_CKE_MASK)
232732374a0SPragnesh Patel return 1;
233732374a0SPragnesh Patel else
234732374a0SPragnesh Patel return 0;
235732374a0SPragnesh Patel }
236732374a0SPragnesh Patel
sifive_prci_clock_enable(struct clk_hw * hw)237732374a0SPragnesh Patel int sifive_prci_clock_enable(struct clk_hw *hw)
238732374a0SPragnesh Patel {
239732374a0SPragnesh Patel struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
240732374a0SPragnesh Patel struct __prci_wrpll_data *pwd = pc->pwd;
241732374a0SPragnesh Patel struct __prci_data *pd = pc->pd;
242732374a0SPragnesh Patel
243732374a0SPragnesh Patel if (sifive_clk_is_enabled(hw))
244732374a0SPragnesh Patel return 0;
245732374a0SPragnesh Patel
246732374a0SPragnesh Patel __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
247732374a0SPragnesh Patel
248c816e1ddSZong Li if (pwd->disable_bypass)
249c816e1ddSZong Li pwd->disable_bypass(pd);
250c816e1ddSZong Li
251c816e1ddSZong Li return 0;
252c816e1ddSZong Li }
253c816e1ddSZong Li
sifive_prci_clock_disable(struct clk_hw * hw)254732374a0SPragnesh Patel void sifive_prci_clock_disable(struct clk_hw *hw)
255732374a0SPragnesh Patel {
256732374a0SPragnesh Patel struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
257732374a0SPragnesh Patel struct __prci_wrpll_data *pwd = pc->pwd;
258732374a0SPragnesh Patel struct __prci_data *pd = pc->pd;
259732374a0SPragnesh Patel u32 r;
260732374a0SPragnesh Patel
261732374a0SPragnesh Patel if (pwd->enable_bypass)
262732374a0SPragnesh Patel pwd->enable_bypass(pd);
263732374a0SPragnesh Patel
264732374a0SPragnesh Patel r = __prci_readl(pd, pwd->cfg1_offs);
265732374a0SPragnesh Patel r &= ~PRCI_COREPLLCFG1_CKE_MASK;
266732374a0SPragnesh Patel
267732374a0SPragnesh Patel __prci_wrpll_write_cfg1(pd, pwd, r);
268732374a0SPragnesh Patel }
269732374a0SPragnesh Patel
270c816e1ddSZong Li /* TLCLKSEL clock integration */
271c816e1ddSZong Li
sifive_prci_tlclksel_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)272c816e1ddSZong Li unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,
273c816e1ddSZong Li unsigned long parent_rate)
274c816e1ddSZong Li {
275c816e1ddSZong Li struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
276c816e1ddSZong Li struct __prci_data *pd = pc->pd;
277c816e1ddSZong Li u32 v;
278c816e1ddSZong Li u8 div;
279c816e1ddSZong Li
280c816e1ddSZong Li v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
281c816e1ddSZong Li v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
282c816e1ddSZong Li div = v ? 1 : 2;
283c816e1ddSZong Li
284c816e1ddSZong Li return div_u64(parent_rate, div);
285c816e1ddSZong Li }
286c816e1ddSZong Li
287efc91ae4SZong Li /* HFPCLK clock integration */
288efc91ae4SZong Li
sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)289efc91ae4SZong Li unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw,
290efc91ae4SZong Li unsigned long parent_rate)
291efc91ae4SZong Li {
292efc91ae4SZong Li struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
293efc91ae4SZong Li struct __prci_data *pd = pc->pd;
294efc91ae4SZong Li u32 div = __prci_readl(pd, PRCI_HFPCLKPLLDIV_OFFSET);
295efc91ae4SZong Li
296efc91ae4SZong Li return div_u64(parent_rate, div + 2);
297efc91ae4SZong Li }
298efc91ae4SZong Li
299c816e1ddSZong Li /*
300c816e1ddSZong Li * Core clock mux control
301c816e1ddSZong Li */
302c816e1ddSZong Li
303c816e1ddSZong Li /**
304c816e1ddSZong Li * sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
305c816e1ddSZong Li * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
306c816e1ddSZong Li *
307c816e1ddSZong Li * Switch the CORECLK mux to the HFCLK input source; return once complete.
308c816e1ddSZong Li *
309c816e1ddSZong Li * Context: Any context. Caller must prevent concurrent changes to the
310c816e1ddSZong Li * PRCI_CORECLKSEL_OFFSET register.
311c816e1ddSZong Li */
sifive_prci_coreclksel_use_hfclk(struct __prci_data * pd)312c816e1ddSZong Li void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd)
313c816e1ddSZong Li {
314c816e1ddSZong Li u32 r;
315c816e1ddSZong Li
316c816e1ddSZong Li r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
317c816e1ddSZong Li r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
318c816e1ddSZong Li __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
319c816e1ddSZong Li
320c816e1ddSZong Li r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
321c816e1ddSZong Li }
322c816e1ddSZong Li
323c816e1ddSZong Li /**
324c816e1ddSZong Li * sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output
325c816e1ddSZong Li * COREPLL
326c816e1ddSZong Li * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
327c816e1ddSZong Li *
328c816e1ddSZong Li * Switch the CORECLK mux to the COREPLL output clock; return once complete.
329c816e1ddSZong Li *
330c816e1ddSZong Li * Context: Any context. Caller must prevent concurrent changes to the
331c816e1ddSZong Li * PRCI_CORECLKSEL_OFFSET register.
332c816e1ddSZong Li */
sifive_prci_coreclksel_use_corepll(struct __prci_data * pd)333c816e1ddSZong Li void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd)
334c816e1ddSZong Li {
335c816e1ddSZong Li u32 r;
336c816e1ddSZong Li
337c816e1ddSZong Li r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
338c816e1ddSZong Li r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
339c816e1ddSZong Li __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
340c816e1ddSZong Li
341c816e1ddSZong Li r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
342c816e1ddSZong Li }
343c816e1ddSZong Li
344c816e1ddSZong Li /**
345efc91ae4SZong Li * sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output
346efc91ae4SZong Li * FINAL_COREPLL
347efc91ae4SZong Li * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
348efc91ae4SZong Li *
349efc91ae4SZong Li * Switch the CORECLK mux to the final COREPLL output clock; return once
350efc91ae4SZong Li * complete.
351efc91ae4SZong Li *
352efc91ae4SZong Li * Context: Any context. Caller must prevent concurrent changes to the
353efc91ae4SZong Li * PRCI_CORECLKSEL_OFFSET register.
354efc91ae4SZong Li */
sifive_prci_coreclksel_use_final_corepll(struct __prci_data * pd)355efc91ae4SZong Li void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd)
356efc91ae4SZong Li {
357efc91ae4SZong Li u32 r;
358efc91ae4SZong Li
359efc91ae4SZong Li r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
360efc91ae4SZong Li r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
361efc91ae4SZong Li __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
362efc91ae4SZong Li
363efc91ae4SZong Li r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
364efc91ae4SZong Li }
365efc91ae4SZong Li
366efc91ae4SZong Li /**
367efc91ae4SZong Li * sifive_prci_corepllsel_use_dvfscorepll() - switch the COREPLL mux to
368efc91ae4SZong Li * output DVFS_COREPLL
369efc91ae4SZong Li * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
370efc91ae4SZong Li *
371efc91ae4SZong Li * Switch the COREPLL mux to the DVFSCOREPLL output clock; return once complete.
372efc91ae4SZong Li *
373efc91ae4SZong Li * Context: Any context. Caller must prevent concurrent changes to the
374efc91ae4SZong Li * PRCI_COREPLLSEL_OFFSET register.
375efc91ae4SZong Li */
sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data * pd)376efc91ae4SZong Li void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd)
377efc91ae4SZong Li {
378efc91ae4SZong Li u32 r;
379efc91ae4SZong Li
380efc91ae4SZong Li r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);
381efc91ae4SZong Li r |= PRCI_COREPLLSEL_COREPLLSEL_MASK;
382efc91ae4SZong Li __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);
383efc91ae4SZong Li
384efc91ae4SZong Li r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */
385efc91ae4SZong Li }
386efc91ae4SZong Li
387efc91ae4SZong Li /**
388efc91ae4SZong Li * sifive_prci_corepllsel_use_corepll() - switch the COREPLL mux to
389efc91ae4SZong Li * output COREPLL
390efc91ae4SZong Li * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
391efc91ae4SZong Li *
392efc91ae4SZong Li * Switch the COREPLL mux to the COREPLL output clock; return once complete.
393efc91ae4SZong Li *
394efc91ae4SZong Li * Context: Any context. Caller must prevent concurrent changes to the
395efc91ae4SZong Li * PRCI_COREPLLSEL_OFFSET register.
396efc91ae4SZong Li */
sifive_prci_corepllsel_use_corepll(struct __prci_data * pd)397efc91ae4SZong Li void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd)
398efc91ae4SZong Li {
399efc91ae4SZong Li u32 r;
400efc91ae4SZong Li
401efc91ae4SZong Li r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);
402efc91ae4SZong Li r &= ~PRCI_COREPLLSEL_COREPLLSEL_MASK;
403efc91ae4SZong Li __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);
404efc91ae4SZong Li
405efc91ae4SZong Li r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */
406efc91ae4SZong Li }
407efc91ae4SZong Li
408efc91ae4SZong Li /**
409efc91ae4SZong Li * sifive_prci_hfpclkpllsel_use_hfclk() - switch the HFPCLKPLL mux to
410efc91ae4SZong Li * output HFCLK
411efc91ae4SZong Li * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
412efc91ae4SZong Li *
413efc91ae4SZong Li * Switch the HFPCLKPLL mux to the HFCLK input source; return once complete.
414efc91ae4SZong Li *
415efc91ae4SZong Li * Context: Any context. Caller must prevent concurrent changes to the
416efc91ae4SZong Li * PRCI_HFPCLKPLLSEL_OFFSET register.
417efc91ae4SZong Li */
sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data * pd)418efc91ae4SZong Li void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd)
419efc91ae4SZong Li {
420efc91ae4SZong Li u32 r;
421efc91ae4SZong Li
422efc91ae4SZong Li r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);
423efc91ae4SZong Li r |= PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;
424efc91ae4SZong Li __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);
425efc91ae4SZong Li
426efc91ae4SZong Li r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
427efc91ae4SZong Li }
428efc91ae4SZong Li
429efc91ae4SZong Li /**
430efc91ae4SZong Li * sifive_prci_hfpclkpllsel_use_hfpclkpll() - switch the HFPCLKPLL mux to
431efc91ae4SZong Li * output HFPCLKPLL
432efc91ae4SZong Li * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
433efc91ae4SZong Li *
434efc91ae4SZong Li * Switch the HFPCLKPLL mux to the HFPCLKPLL output clock; return once complete.
435efc91ae4SZong Li *
436efc91ae4SZong Li * Context: Any context. Caller must prevent concurrent changes to the
437efc91ae4SZong Li * PRCI_HFPCLKPLLSEL_OFFSET register.
438efc91ae4SZong Li */
sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data * pd)439efc91ae4SZong Li void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd)
440efc91ae4SZong Li {
441efc91ae4SZong Li u32 r;
442efc91ae4SZong Li
443efc91ae4SZong Li r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);
444efc91ae4SZong Li r &= ~PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;
445efc91ae4SZong Li __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);
446efc91ae4SZong Li
447efc91ae4SZong Li r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
448efc91ae4SZong Li }
449efc91ae4SZong Li
450c61287bfSGreentime Hu /* PCIE AUX clock APIs for enable, disable. */
sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw * hw)451c61287bfSGreentime Hu int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw)
452c61287bfSGreentime Hu {
453c61287bfSGreentime Hu struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
454c61287bfSGreentime Hu struct __prci_data *pd = pc->pd;
455c61287bfSGreentime Hu u32 r;
456c61287bfSGreentime Hu
457c61287bfSGreentime Hu r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);
458c61287bfSGreentime Hu
459c61287bfSGreentime Hu if (r & PRCI_PCIE_AUX_EN_MASK)
460c61287bfSGreentime Hu return 1;
461c61287bfSGreentime Hu else
462c61287bfSGreentime Hu return 0;
463c61287bfSGreentime Hu }
464c61287bfSGreentime Hu
sifive_prci_pcie_aux_clock_enable(struct clk_hw * hw)465c61287bfSGreentime Hu int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw)
466c61287bfSGreentime Hu {
467c61287bfSGreentime Hu struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
468c61287bfSGreentime Hu struct __prci_data *pd = pc->pd;
469c61287bfSGreentime Hu u32 r __maybe_unused;
470c61287bfSGreentime Hu
471c61287bfSGreentime Hu if (sifive_prci_pcie_aux_clock_is_enabled(hw))
472c61287bfSGreentime Hu return 0;
473c61287bfSGreentime Hu
474c61287bfSGreentime Hu __prci_writel(1, PRCI_PCIE_AUX_OFFSET, pd);
475c61287bfSGreentime Hu r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */
476c61287bfSGreentime Hu
477c61287bfSGreentime Hu return 0;
478c61287bfSGreentime Hu }
479c61287bfSGreentime Hu
sifive_prci_pcie_aux_clock_disable(struct clk_hw * hw)480c61287bfSGreentime Hu void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw)
481c61287bfSGreentime Hu {
482c61287bfSGreentime Hu struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
483c61287bfSGreentime Hu struct __prci_data *pd = pc->pd;
484c61287bfSGreentime Hu u32 r __maybe_unused;
485c61287bfSGreentime Hu
486c61287bfSGreentime Hu __prci_writel(0, PRCI_PCIE_AUX_OFFSET, pd);
487c61287bfSGreentime Hu r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */
488c61287bfSGreentime Hu
489c61287bfSGreentime Hu }
490c61287bfSGreentime Hu
491efc91ae4SZong Li /**
492c816e1ddSZong Li * __prci_register_clocks() - register clock controls in the PRCI
493c816e1ddSZong Li * @dev: Linux struct device
494c816e1ddSZong Li * @pd: The pointer for PRCI per-device instance data
495c816e1ddSZong Li * @desc: The pointer for the information of clocks of each SoCs
496c816e1ddSZong Li *
497c816e1ddSZong Li * Register the list of clock controls described in __prci_init_clocks[] with
498c816e1ddSZong Li * the Linux clock framework.
499c816e1ddSZong Li *
500c816e1ddSZong Li * Return: 0 upon success or a negative error code upon failure.
501c816e1ddSZong Li */
__prci_register_clocks(struct device * dev,struct __prci_data * pd,const struct prci_clk_desc * desc)502c816e1ddSZong Li static int __prci_register_clocks(struct device *dev, struct __prci_data *pd,
503c816e1ddSZong Li const struct prci_clk_desc *desc)
504c816e1ddSZong Li {
505c816e1ddSZong Li struct clk_init_data init = { };
506c816e1ddSZong Li struct __prci_clock *pic;
507c816e1ddSZong Li int parent_count, i, r;
508c816e1ddSZong Li
509c816e1ddSZong Li parent_count = of_clk_get_parent_count(dev->of_node);
510c816e1ddSZong Li if (parent_count != EXPECTED_CLK_PARENT_COUNT) {
511c816e1ddSZong Li dev_err(dev, "expected only two parent clocks, found %d\n",
512c816e1ddSZong Li parent_count);
513c816e1ddSZong Li return -EINVAL;
514c816e1ddSZong Li }
515c816e1ddSZong Li
516c816e1ddSZong Li /* Register PLLs */
517c816e1ddSZong Li for (i = 0; i < desc->num_clks; ++i) {
518c816e1ddSZong Li pic = &(desc->clks[i]);
519c816e1ddSZong Li
520c816e1ddSZong Li init.name = pic->name;
521c816e1ddSZong Li init.parent_names = &pic->parent_name;
522c816e1ddSZong Li init.num_parents = 1;
523c816e1ddSZong Li init.ops = pic->ops;
524c816e1ddSZong Li pic->hw.init = &init;
525c816e1ddSZong Li
526c816e1ddSZong Li pic->pd = pd;
527c816e1ddSZong Li
528c816e1ddSZong Li if (pic->pwd)
529732374a0SPragnesh Patel __prci_wrpll_read_cfg0(pd, pic->pwd);
530c816e1ddSZong Li
531c816e1ddSZong Li r = devm_clk_hw_register(dev, &pic->hw);
532c816e1ddSZong Li if (r) {
533c816e1ddSZong Li dev_warn(dev, "Failed to register clock %s: %d\n",
534c816e1ddSZong Li init.name, r);
535c816e1ddSZong Li return r;
536c816e1ddSZong Li }
537c816e1ddSZong Li
538c816e1ddSZong Li pd->hw_clks.hws[i] = &pic->hw;
539c816e1ddSZong Li }
540c816e1ddSZong Li
541c816e1ddSZong Li pd->hw_clks.num = i;
542c816e1ddSZong Li
543c816e1ddSZong Li r = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
544c816e1ddSZong Li &pd->hw_clks);
545c816e1ddSZong Li if (r) {
546c816e1ddSZong Li dev_err(dev, "could not add hw_provider: %d\n", r);
547c816e1ddSZong Li return r;
548c816e1ddSZong Li }
549c816e1ddSZong Li
550c816e1ddSZong Li return 0;
551c816e1ddSZong Li }
552c816e1ddSZong Li
553c816e1ddSZong Li /**
554c37f1cddSYang Li * sifive_prci_probe() - initialize prci data and check parent count
555c816e1ddSZong Li * @pdev: platform device pointer for the prci
556c816e1ddSZong Li *
557c816e1ddSZong Li * Return: 0 upon success or a negative error code upon failure.
558c816e1ddSZong Li */
sifive_prci_probe(struct platform_device * pdev)559c816e1ddSZong Li static int sifive_prci_probe(struct platform_device *pdev)
560c816e1ddSZong Li {
561c816e1ddSZong Li struct device *dev = &pdev->dev;
562c816e1ddSZong Li struct __prci_data *pd;
563c816e1ddSZong Li const struct prci_clk_desc *desc;
564c816e1ddSZong Li int r;
565c816e1ddSZong Li
566c816e1ddSZong Li desc = of_device_get_match_data(&pdev->dev);
567c816e1ddSZong Li
568c816e1ddSZong Li pd = devm_kzalloc(dev, struct_size(pd, hw_clks.hws, desc->num_clks), GFP_KERNEL);
569c816e1ddSZong Li if (!pd)
570c816e1ddSZong Li return -ENOMEM;
571c816e1ddSZong Li
572a7a0c7d5SYang Li pd->va = devm_platform_ioremap_resource(pdev, 0);
573c816e1ddSZong Li if (IS_ERR(pd->va))
574c816e1ddSZong Li return PTR_ERR(pd->va);
575c816e1ddSZong Li
576e4d368e0SGreentime Hu pd->reset.rcdev.owner = THIS_MODULE;
577e4d368e0SGreentime Hu pd->reset.rcdev.nr_resets = PRCI_RST_NR;
578e4d368e0SGreentime Hu pd->reset.rcdev.ops = &reset_simple_ops;
579e4d368e0SGreentime Hu pd->reset.rcdev.of_node = pdev->dev.of_node;
580e4d368e0SGreentime Hu pd->reset.active_low = true;
581e4d368e0SGreentime Hu pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;
582e4d368e0SGreentime Hu spin_lock_init(&pd->reset.lock);
583e4d368e0SGreentime Hu
584e4d368e0SGreentime Hu r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev);
585e4d368e0SGreentime Hu if (r) {
586e4d368e0SGreentime Hu dev_err(dev, "could not register reset controller: %d\n", r);
587e4d368e0SGreentime Hu return r;
588e4d368e0SGreentime Hu }
589c816e1ddSZong Li r = __prci_register_clocks(dev, pd, desc);
590c816e1ddSZong Li if (r) {
591c816e1ddSZong Li dev_err(dev, "could not register clocks: %d\n", r);
592c816e1ddSZong Li return r;
593c816e1ddSZong Li }
594c816e1ddSZong Li
595c816e1ddSZong Li dev_dbg(dev, "SiFive PRCI probed\n");
596c816e1ddSZong Li
597c816e1ddSZong Li return 0;
598c816e1ddSZong Li }
599c816e1ddSZong Li
600c816e1ddSZong Li static const struct of_device_id sifive_prci_of_match[] = {
601c816e1ddSZong Li {.compatible = "sifive,fu540-c000-prci", .data = &prci_clk_fu540},
602efc91ae4SZong Li {.compatible = "sifive,fu740-c000-prci", .data = &prci_clk_fu740},
603c816e1ddSZong Li {}
604c816e1ddSZong Li };
605c816e1ddSZong Li
606c816e1ddSZong Li static struct platform_driver sifive_prci_driver = {
607c816e1ddSZong Li .driver = {
608c816e1ddSZong Li .name = "sifive-clk-prci",
609c816e1ddSZong Li .of_match_table = sifive_prci_of_match,
610c816e1ddSZong Li },
611c816e1ddSZong Li .probe = sifive_prci_probe,
612c816e1ddSZong Li };
613c816e1ddSZong Li
sifive_prci_init(void)614c816e1ddSZong Li static int __init sifive_prci_init(void)
615c816e1ddSZong Li {
616c816e1ddSZong Li return platform_driver_register(&sifive_prci_driver);
617c816e1ddSZong Li }
618c816e1ddSZong Li core_initcall(sifive_prci_init);
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