| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | microchip,sparx5-sgpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | mscc_sgpio.txt | 10 - compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio"
11 - clock: Reference clock used to generate clock divider setting. See
12 mscc,sgpio-frequency property.
13 - reg : Physical base address and length of the controller's registers.
14 - #gpio-cells : Should be two. The first cell is the pin number and the
16 - bit 0 specifies polarity (0 for normal, 1 for inverted)
17 - gpio-controller : Marks the device node as a GPIO controller.
18 - gpio-ranges: Standard gpio range(s): phandle, gpio base, pinctrl base
22 - ngpios: See gpio.txt
23 - mscc,sgpio-frequency: The frequency at which the serial bitstream is
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| /openbmc/linux/arch/arm64/boot/dts/microchip/ |
| H A D | sparx5_pcb134_board.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
53 default-state = "off";
58 default-state = "off";
63 default-state = "off";
68 default-state = "off";
73 default-state = "off";
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| H A D | sparx5_pcb125.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "microchip,sparx5-pcb125", "microchip,sparx5";
20 emmc_pins: emmc-pins {
28 drive-strength = <3>;
35 bus-width = <8>;
36 non-removable;
37 pinctrl-0 = <&emmc_pins>;
38 max-frequency = <8000000>;
39 microchip,clock-delay = <10>;
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| H A D | sparx5_pcb135_board.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
17 compatible = "gpio-leds";
21 default-state = "off";
26 default-state = "off";
31 default-state = "off";
36 default-state = "off";
41 default-state = "off";
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| /openbmc/linux/Documentation/devicetree/bindings/mfd/ |
| H A D | mscc,ocelot.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ocelot Externally-Controlled Ethernet Switch
10 - Colin Foster <colin.foster@in-advantage.com>
18 The switch family is a multi-port networking switch that supports many
25 - mscc,vsc7512
30 "#address-cells":
33 "#size-cells":
36 spi-max-frequency:
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| /openbmc/u-boot/arch/mips/dts/ |
| H A D | mscc,luton.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
28 sys_clk: sys-clk {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <250000000>;
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| H A D | mscc,ocelot.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
27 cpuintc: interrupt-controller@0 {
28 #address-cells = <0>;
29 #interrupt-cells = <1>;
30 interrupt-controller;
31 compatible = "mti,cpu-interrupt-controller";
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| /openbmc/u-boot/drivers/gpio/ |
| H A D | mscc_sgpio.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
44 #define __X(bf, x) (((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
46 #define MSCC_M_CFG_SIO_AUTO_REPEAT(p) BIT(p->props->auto_repeat.beg)
47 #define MSCC_F_CFG_SIO_PORT_WIDTH(p, x) __F(p->props->port_width, x)
48 #define MSCC_M_CFG_SIO_PORT_WIDTH(p) __M(p->props->port_width)
49 #define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x) __F(p->props->clk_freq, x)
50 #define MSCC_M_CLOCK_SIO_CLK_FREQ(p) __M(p->props->clk_freq)
51 #define MSCC_F_PORT_CFG_BIT_SOURCE(p, x) __F(p->props->bit_source, x)
52 #define MSCC_X_PORT_CFG_BIT_SOURCE(p, x) __X(p->props->bit_source, x)
81 u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off]; in sgpio_readl()
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| /openbmc/linux/arch/arm/boot/dts/microchip/ |
| H A D | lan966x-pcb8291.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x_pcb8291.dts - Device Tree file for PCB8291
5 /dts-v1/;
7 #include "dt-bindings/phy/phy-lan966x-serdes.h"
10 model = "Microchip EVB - LAN9662";
11 compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966";
14 stdout-path = "serial0:115200n8";
21 gpio-restart {
22 compatible = "gpio-restart";
28 compatible = "gpio-leds";
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| H A D | lan966x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <1>;
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| H A D | lan966x-kontron-kswitch-d10-mmt.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
16 stdout-path = "serial0:115200n8";
19 gpio-restart {
20 compatible = "gpio-restart";
21 pinctrl-0 = <&reset_pins>;
22 pinctrl-names = "default";
29 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
33 pinctrl-0 = <&usart0_pins>;
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| H A D | lan966x-pcb8309.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x_pcb8309.dts - Device Tree file for PCB8309
5 /dts-v1/;
7 #include "dt-bindings/phy/phy-lan966x-serdes.h"
10 model = "Microchip EVB - LAN9662";
11 compatible = "microchip,lan9662-pcb8309", "microchip,lan9662", "microchip,lan966";
20 stdout-path = "serial0:115200n8";
23 gpio-restart {
24 compatible = "gpio-restart";
29 i2c-mux {
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| /openbmc/linux/drivers/pinctrl/ |
| H A D | pinctrl-microchip-sgpio.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
131 u8 port; member
138 addr->port = pin / priv->bitcount; in sgpio_pin_to_addr()
139 addr->bit = pin % priv->bitcount; in sgpio_pin_to_addr()
142 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit) in sgpio_addr_to_pin() argument
144 return bit + port * priv->bitcount; in sgpio_addr_to_pin()
149 return (priv->properties->regoff[rno] + off) * in sgpio_get_addr()
150 regmap_get_reg_stride(priv->regs); in sgpio_get_addr()
159 ret = regmap_read(priv->regs, addr, &val); in sgpio_readl()
160 WARN_ONCE(ret, "error reading sgpio reg %d\n", ret); in sgpio_readl()
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| /openbmc/linux/arch/arm/boot/dts/aspeed/ |
| H A D | aspeed-bmc-tyan-s7106.dts | 1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "tyan,s7106-bmc", "aspeed,ast2500";
13 stdout-path = &uart5;
22 reserved-memory {
23 #address-cells = <1>;
24 #size-cells = <1>;
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| /openbmc/linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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| H A D | opengrok0.0.log | 1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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| H A D | opengrok1.0.log | 1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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| H A D | opengrok2.0.log | 1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)
4 2024-1
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