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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-msm.yaml4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
13 Secure Digital Host Controller Interface (SDHCI) present on
20 - qcom,sdhci-msm-v4
24 - qcom,apq8084-sdhci
25 - qcom,msm8226-sdhci
26 - qcom,msm8953-sdhci
27 - qcom,msm8974-sdhci
28 - qcom,msm8976-sdhci
29 - qcom,msm8916-sdhci
[all …]
H A Dbrcm,sdhci-brcmstb.yaml4 $id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#
7 title: Broadcom BRCMSTB/BMIPS SDHCI Controller
18 - brcm,bcm7216-sdhci
19 - const: brcm,bcm7445-sdhci
20 - const: brcm,sdhci-brcmstb
23 - brcm,bcm7445-sdhci
24 - const: brcm,sdhci-brcmstb
27 - brcm,bcm7425-sdhci
28 - const: brcm,sdhci-brcmstb
44 - description: handle to core clock for the sdhci controller
[all …]
H A Darasan,sdhci.yaml4 $id: http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#
7 title: Arasan SDHCI Controller
18 const: arasan,sdhci-5.1
45 - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
46 - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
47 - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
49 - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
50 - const: arasan,sdhci-5.1
55 - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
56 - const: arasan,sdhci-8.9a
[all …]
H A Dnvidia,tegra20-sdhci.yaml4 $id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
18 mmc-controller.yaml and the properties for the Tegra SDHCI controller.
24 - nvidia,tegra20-sdhci
25 - nvidia,tegra30-sdhci
26 - nvidia,tegra114-sdhci
27 - nvidia,tegra124-sdhci
28 - nvidia,tegra210-sdhci
29 - nvidia,tegra186-sdhci
30 - nvidia,tegra194-sdhci
33 - const: nvidia,tegra132-sdhci
[all …]
H A Dmarvell,xenon-sdhci.yaml4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
7 title: Marvell Xenon SDHCI Controller
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
30 - const: marvell,armada-ap807-sdhci
31 - const: marvell,armada-ap806-sdhci
34 - const: marvell,armada-3700-sdhci
35 - const: marvell,sdhci-xenon
41 For "marvell,armada-3700-sdhci", two register areas. The first one
44 "marvell,armada-3700-sdhci" in below.
[all …]
H A Daspeed,sdhci.yaml5 $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
42 "^sdhci@[0-9a-f]+$":
50 - aspeed,ast2400-sdhci
51 - aspeed,ast2500-sdhci
52 - aspeed,ast2600-sdhci
55 description: The SDHCI registers
62 sdhci,auto-cmd12:
92 sdhci0: sdhci@100 {
93 compatible = "aspeed,ast2500-sdhci";
96 sdhci,auto-cmd12;
[all …]
H A Dsdhci-atmel.txt1 * Atmel SDHCI controller
5 sdhci-of-at91 driver.
8 - compatible: Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci"
9 or "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci".
12 "atmel,sama5d2-sdhci".
13 Must be "hclock", "multclk" for "microchip,sam9x60-sdhci".
14 Must be "hclock", "multclk" for "microchip,sam9x7-sdhci".
28 compatible = "atmel,sama5d2-sdhci";
H A Dbrcm,iproc-sdhci.yaml4 $id: http://devicetree.org/schemas/mmc/brcm,iproc-sdhci.yaml#
7 title: Broadcom IPROC SDHCI controller
20 - brcm,bcm2835-sdhci
22 - brcm,sdhci-iproc-cygnus
23 - brcm,sdhci-iproc
24 - brcm,bcm7211a0-sdhci
35 Handle to core clock for the sdhci controller.
37 sdhci,auto-cmd12:
56 compatible = "brcm,sdhci-iproc-cygnus";
61 sdhci,auto-cmd12;
H A Dsdhci-omap.txt1 * TI OMAP SDHCI Controller
8 - compatible: Should be "ti,omap2430-sdhci" for omap2430 controllers
9 Should be "ti,omap3-sdhci" for omap3 controllers
10 Should be "ti,omap4-sdhci" for omap4 and ti81 controllers
11 Should be "ti,omap5-sdhci" for omap5 controllers
12 Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers
13 Should be "ti,k2g-sdhci" for K2G
14 Should be "ti,am335-sdhci" for am335x controllers
15 Should be "ti,am437-sdhci" for am437x controllers
36 compatible = "ti,dra7-sdhci";
H A Dsdhci.txt7 - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
8 property corresponds to the bits in the sdhci capability register. If the bit
10 turned off, before applying sdhci-caps.
11 - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
12 property corresponds to the bits in the sdhci capability register. If the
H A Dsdhci-st.txt1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
64 mmc0: sdhci@fe81e000 {
65 compatible = "st,sdhci";
77 mmc1: sdhci@9080000 {
78 compatible = "st,sdhci-stih407", "st,sdhci";
93 mmc0: sdhci@9060000 {
94 compatible = "st,sdhci-stih407", "st,sdhci";
H A Dsdhci-common.yaml4 $id: http://devicetree.org/schemas/mmc/sdhci-common.yaml#
7 title: SDHCI Controller Common Properties
13 Common properties present on Secure Digital Host Controller Interface (SDHCI)
17 sdhci-caps:
20 Additionally present SDHCI capabilities - values for SDHCI_CAPABILITIES
23 sdhci-caps-mask:
26 Masked SDHCI capabilities to remove from SDHCI_CAPABILITIES and
H A Dsdhci-am654.yaml5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
14 - $ref: sdhci-common.yaml#
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
22 - ti,am64-sdhci-8bit
23 - ti,am654-sdhci-5.1
24 - ti,j721e-sdhci-4bit
25 - ti,j721e-sdhci-8bit
27 - const: ti,j7200-sdhci-8bit
28 - const: ti,j721e-sdhci-8bit
[all …]
H A Dmicrochip,sdhci-pic32.txt1 * Microchip PIC32 SDHCI Controller
4 and the properties used by the sdhci-pic32 driver.
7 - compatible: Should be "microchip,pic32mzda-sdhci"
14 - pinctrl-0: Phandle referencing pin configuration of the SDHCI controller.
19 sdhci@1f8ec000 {
20 compatible = "microchip,pic32mzda-sdhci";
/openbmc/qemu/hw/sd/
H A Daspeed_sdhci.c41 AspeedSDHCIState *sdhci = opaque; in aspeed_sdhci_read() local
45 val = extract64(sdhci->slots[0].capareg, 0, 32); in aspeed_sdhci_read()
48 val = extract64(sdhci->slots[0].capareg, 32, 32); in aspeed_sdhci_read()
51 val = extract64(sdhci->slots[0].maxcurr, 0, 32); in aspeed_sdhci_read()
54 val = extract64(sdhci->slots[1].capareg, 0, 32); in aspeed_sdhci_read()
57 val = extract64(sdhci->slots[1].capareg, 32, 32); in aspeed_sdhci_read()
60 val = extract64(sdhci->slots[1].maxcurr, 0, 32); in aspeed_sdhci_read()
64 val = sdhci->regs[TO_REG(addr)]; in aspeed_sdhci_read()
80 AspeedSDHCIState *sdhci = opaque; in aspeed_sdhci_write() local
87 sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET; in aspeed_sdhci_write()
[all …]
H A Dnpcm7xx_sdhci.c19 #include "hw/sd/sdhci.h"
22 #include "sdhci-internal.h"
43 qemu_log_mask(LOG_GUEST_ERROR, "SDHCI read of nonexistent reg: 0x%02" in npcm7xx_sdhci_read()
61 qemu_log_mask(LOG_GUEST_ERROR, "SDHCI write of nonexistent reg: 0x%02" in npcm7xx_sdhci_write()
104 SysBusDevice *sbd_sdhci = SYS_BUS_DEVICE(&s->sdhci); in npcm7xx_sdhci_realize()
107 "npcm7xx.sdhci-container", 0x1000); in npcm7xx_sdhci_realize()
119 /* propagate irq and "sd-bus" from generic-sdhci */ in npcm7xx_sdhci_realize()
133 device_cold_reset(DEVICE(&s->sdhci)); in npcm7xx_sdhci_reset()
136 s->sdhci.prnsts = NPCM7XX_PRSNTS_RESET; in npcm7xx_sdhci_reset()
137 s->sdhci.blkgap = NPCM7XX_BLKGAP_RESET; in npcm7xx_sdhci_reset()
[all …]
/openbmc/qemu/docs/devel/testing/
H A Dqgraph.rst11 For example, the sdhci device is supported on both x86_64 and ARM boards,
12 therefore a generic sdhci test should test all machines and drivers that
28 Following the above example, an interface would be ``sdhci``,
29 so the sdhci-test should only care of linking its qgraph node with
30 that interface. In this way, if the command line of a sdhci driver
46 - **QNODE_DRIVER**: for example ``generic-sdhci``
47 - **QNODE_INTERFACE**: for example ``sdhci`` (interface for all ``-sdhci``
54 - **QNODE_TEST**: for example ``sdhci-test``. A test consumes an interface
213 Here we continue the ``sdhci`` use case, with the following scenario:
215 - ``sdhci-test`` aims to test the ``read[q,w], writeq`` functions
[all …]
/openbmc/qemu/tests/qtest/libqos/
H A Dsdhci.c24 #include "sdhci.h"
40 QSDHCI_MemoryMapped *smm = container_of(s, QSDHCI_MemoryMapped, sdhci); in sdhci_mm_readw()
46 QSDHCI_MemoryMapped *smm = container_of(s, QSDHCI_MemoryMapped, sdhci); in sdhci_mm_readq()
52 QSDHCI_MemoryMapped *smm = container_of(s, QSDHCI_MemoryMapped, sdhci); in sdhci_mm_writeq()
59 if (!g_strcmp0(interface, "sdhci")) { in sdhci_mm_get_driver()
60 return &smm->sdhci; in sdhci_mm_get_driver()
62 fprintf(stderr, "%s not present in generic-sdhci\n", interface); in sdhci_mm_get_driver()
66 void qos_init_sdhci_mm(QSDHCI_MemoryMapped *sdhci, QTestState *qts, in qos_init_sdhci_mm() argument
69 sdhci->obj.get_driver = sdhci_mm_get_driver; in qos_init_sdhci_mm()
70 sdhci->sdhci.readw = sdhci_mm_readw; in qos_init_sdhci_mm()
[all …]
/openbmc/linux/drivers/mmc/host/
H A DMakefile13 obj-$(CONFIG_MMC_SDHCI) += sdhci.o
14 obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
15 sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \
16 sdhci-pci-dwc-mshc.o sdhci-pci-gli.o
17 obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o
18 obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
19 obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
20 obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
22 obj-$(CONFIG_MMC_SDHCI_MILBEAUT) += sdhci-milbeaut.o
23 obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
[all …]
H A Dsdhci-spear.c2 * drivers/mmc/host/sdhci-spear.c
4 * Support of SDHCI platform devices for spear soc family
9 * Inspired by sdhci-pltfm.c
29 #include "sdhci.h"
35 /* sdhci ops */
46 struct spear_sdhci *sdhci; in sdhci_probe() local
51 host = sdhci_alloc_host(dev, sizeof(*sdhci)); in sdhci_probe()
54 dev_dbg(&pdev->dev, "cannot allocate memory for sdhci\n"); in sdhci_probe()
65 host->hw_name = "sdhci"; in sdhci_probe()
74 sdhci = sdhci_priv(host); in sdhci_probe()
[all …]
H A DKconfig85 need to overwrite SDHCI IO memory accessors.
93 and performing I/O to a SDHCI controller through a bus that
99 This is the case for the Nintendo Wii SDHCI.
102 tristate "SDHCI support on PCI bus"
121 proprietary controller is unnecessary because the SDHCI driver
130 tristate "SDHCI support for ACPI enumerated SDHCI controllers"
134 This selects support for ACPI enumerated SDHCI controllers,
143 tristate "SDHCI platform and OF driver helper"
154 tristate "SDHCI OF support for the Arasan SDHCI controllers"
161 (SDHCI). This hardware is found e.g. in Xilinx' Zynq SoC.
[all …]
/openbmc/u-boot/drivers/mmc/
H A DKconfig369 need to overwrite SDHCI IO memory accessors.
372 bool "Support SDHCI SDMA"
379 bool "Aspeed SDHCI controller support"
384 This enables support for the Aspeed SDHCI controller, which supports
391 bool "Atmel SDHCI controller support"
396 This enables support for the Atmel SDHCI controller, which supports
403 tristate "SDHCI support for the BCM2835 SD/MMC Controller"
416 tristate "SDHCI support for the BCMSTB SD/MMC Controller"
427 bool "SDHCI support for the Cadence SD/SDIO/eMMC controller"
439 bool "Arasan SDHCI controller for TI's K3 based SoCs"
[all …]
/openbmc/qemu/tests/unit/
H A Dtest-qgraph.c27 #define SDHCI "sdhci" macro
29 #define SDHCI_PCI "sdhci-pci"
30 #define SDHCI_MM "generic-sdhci"
211 check_consumes(I440FX, SDHCI); in test_consumes()
213 g_assert_null(qos_graph_get_machine(SDHCI)); in test_consumes()
215 g_assert_nonnull(qos_graph_get_node(SDHCI)); in test_consumes()
222 check_consumes(I440FX, SDHCI); in test_multiple_consumes()
223 check_consumes(PCIBUS_PC, SDHCI); in test_multiple_consumes()
237 check_test(REGISTER_TEST, SDHCI); in test_test()
263 check_produces(MACHINE_PC, SDHCI); in test_machine_produces_interface()
[all …]
/openbmc/u-boot/doc/device-tree-bindings/mmc/
H A Dmsm_sdhci.txt1 Qualcomm Snapdragon SDHCI controller
4 - compatible : "qcom,sdhci-msm-v4"
6 - Host controller registers (SDHCI)
12 by generic SDHCI code).
18 sdhci@07864000 {
19 compatible = "qcom,sdhci-msm-v4";
/openbmc/u-boot/board/broadcom/bcmstb/
H A Dbcmstb.c12 #include <mach/sdhci.h>
87 char sdhci[16] = { 0 }; in bcmstb_sdhci_address() local
103 sprintf(sdhci, "sdhci%d", alias_index); in bcmstb_sdhci_address()
104 path = fdt_getprop(fdt, node, sdhci, NULL); in bcmstb_sdhci_address()
106 printf("%s: Failed to find alias for %s\n", __func__, sdhci); in bcmstb_sdhci_address()
112 printf("%s: Failed to resolve BCMSTB SDHCI alias\n", __func__); in bcmstb_sdhci_address()
119 printf("%s: Failed to read BCMSTB SDHCI host resource\n", in bcmstb_sdhci_address()
135 printf("%s: Assuming BCMSTB SDHCI address: 0x%p\n", in board_mmc_init()
139 debug("BCMSTB SDHCI base address: 0x%p\n", (void *)sdhci_base_address); in board_mmc_init()

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