1bb5f8ea4Sludovic.desroches@atmel.com* Atmel SDHCI controller
2bb5f8ea4Sludovic.desroches@atmel.com
3bb5f8ea4Sludovic.desroches@atmel.comThis file documents the differences between the core properties in
4bb5f8ea4Sludovic.desroches@atmel.comDocumentation/devicetree/bindings/mmc/mmc.txt and the properties used by the
5bb5f8ea4Sludovic.desroches@atmel.comsdhci-of-at91 driver.
6bb5f8ea4Sludovic.desroches@atmel.com
7bb5f8ea4Sludovic.desroches@atmel.comRequired properties:
8*90ecc29aSVarshini Rajendran- compatible:		Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci"
9*90ecc29aSVarshini Rajendran			or "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci".
10bb5f8ea4Sludovic.desroches@atmel.com- clocks:		Phandlers to the clocks.
11d684be14SLudovic Desroches- clock-names:		Must be "hclock", "multclk", "baseclk" for
12d684be14SLudovic Desroches			"atmel,sama5d2-sdhci".
13d684be14SLudovic Desroches			Must be "hclock", "multclk" for "microchip,sam9x60-sdhci".
14*90ecc29aSVarshini Rajendran			Must be "hclock", "multclk" for "microchip,sam9x7-sdhci".
15bb5f8ea4Sludovic.desroches@atmel.com
165cd41fe8SNicolas FerreOptional properties:
17d684be14SLudovic Desroches- assigned-clocks:	The same with "multclk".
18d684be14SLudovic Desroches- assigned-clock-rates	The rate of "multclk" in order to not rely on the
19d684be14SLudovic Desroches			gck configuration set by previous components.
205cd41fe8SNicolas Ferre- microchip,sdcal-inverted: when present, polarity on the SDCAL SoC pin is
215cd41fe8SNicolas Ferre  inverted. The default polarity for this signal is described in the datasheet.
225cd41fe8SNicolas Ferre  For instance on SAMA5D2, the pin is usually tied to the GND with a resistor
235cd41fe8SNicolas Ferre  and a capacitor (see "SDMMC I/O Calibration" chapter).
24bb5f8ea4Sludovic.desroches@atmel.com
25bb5f8ea4Sludovic.desroches@atmel.comExample:
26bb5f8ea4Sludovic.desroches@atmel.com
27d684be14SLudovic Desrochesmmc0: sdio-host@a0000000 {
28bb5f8ea4Sludovic.desroches@atmel.com	compatible = "atmel,sama5d2-sdhci";
29bb5f8ea4Sludovic.desroches@atmel.com	reg = <0xa0000000 0x300>;
30bb5f8ea4Sludovic.desroches@atmel.com	interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
31bb5f8ea4Sludovic.desroches@atmel.com	clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
32bb5f8ea4Sludovic.desroches@atmel.com	clock-names = "hclock", "multclk", "baseclk";
33d684be14SLudovic Desroches	assigned-clocks = <&sdmmc0_gclk>;
34d684be14SLudovic Desroches	assigned-clock-rates = <480000000>;
35bb5f8ea4Sludovic.desroches@atmel.com};
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